Low-power-consumption scheduling method and system for RK main control chip

Abstract

The invention relates to the technical field of microelectronics, and discloses a low-power-consumption scheduling method and system for an RK main control chip, and the method comprises the steps: analyzing the static power consumption of the RK main control chip, carrying out the circuit optimization of the RK main control chip, obtaining an optimized RK main control chip, and building a power consumption feature library of the optimized RK main control chip; obtaining a chip task for optimizing the RK main control chip, and performing task reconstruction on the chip task to obtain a reconstructed chip task; calculating the task priority of the reconstruction chip task, constructing a sequence chip task of the reconstruction chip task, configuring a task processing unit of the sequence chip task, and calculating the task load of the reconstruction chip task in the task processing unit; the chip optimization voltage and the chip optimization frequency of the RK main control chip are analyzed and optimized, and low-power-consumption scheduling of the RK main control chip is optimized based on the chip optimization voltage and the chip optimization frequency. According to the invention, the power consumption optimization effect of the RK main control chip can be improved.

Description

Technical Field

[0001] The present invention relates to a low-power scheduling method and system for an RK main control chip, belonging to the field of microelectronics technology. Background Art

[0002] The low-power scheduling of the RK main control chip refers to the process of managing and optimizing the operating state of the chip through a series of hardware and software strategies to reduce its power consumption. The RK main control chip can achieve longer battery life and lower heat generation without sacrificing performance, which is particularly important for applications such as mobile devices and embedded systems.

[0003] Traditional low-power scheduling of the RK main control chip usually adopts fixed voltage and frequency settings, as well as simple task polling or timed wake-up mechanisms. This approach is not flexible enough to handle dynamic load changes, resulting in power consumption waste in low-load states and inability to effectively improve performance in high-load states, thus making it impossible to perform refined power management according to task characteristics. Summary of the Invention

[0004] The present invention provides a low-power scheduling method and system for an RK main control chip, and its main purpose is to improve the power consumption optimization effect of the RK main control chip.

[0005] To achieve the above object, a low-power scheduling method for an RK main control chip provided by the present invention includes:

[0006] Analyze the static power consumption of the RK main control chip, and according to the static power consumption, perform circuit optimization on the RK main control chip to obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip;

[0007] Define the working mode of the optimized RK main control chip in the chip application scenario, and record the power consumption data of the working mode. Through the power consumption data, establish a power consumption feature library of the optimized RK main control chip;

[0008] Obtain the chip tasks of the optimized RK main control chip, calculate the task similarity and task complexity of the chip tasks, and based on the task similarity and task complexity, perform task reconstruction on the chip tasks to obtain reconstructed chip tasks;

[0009] Calculate the task priority of the reconstructed chip tasks, according to the task priority, construct a sequence of the reconstructed chip tasks, configure the task processing unit of the sequence of chip tasks, and according to the power consumption feature library, use a preset load analysis algorithm to calculate the task load of the reconstructed chip tasks on the task processing unit;

[0010] According to the task load, analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip, and perform low-power scheduling of the optimized RK main control chip based on the chip optimization voltage and chip optimization frequency.

[0011] Optionally, the analysis of the static power consumption of the RK main control chip includes:

[0012] Construct a circuit model of the RK main control chip;

[0013] Define the simulation parameters of the circuit model, and analyze the circuit behavior under the simulation parameters through the circuit model;

[0014] Extract the leakage current data of the RK main control chip through the circuit behavior;

[0015] Analyze the leakage current of the RK main control chip according to the leakage current data;

[0016] Determine the static power consumption of the RK main control chip based on the leakage current.

[0017] Optionally, the analysis of the leakage current of the RK main control chip according to the leakage current data includes:

[0018] Determine the chip circuit parameters of the RK main control chip according to the leakage current data;

[0019] Based on the chip circuit parameters, calculate the subthreshold leakage current of the RK main control chip using the following formula:

[0020] I sub = μ n C ox (W / L)(V th - V in ) n (1 + θ(V ds - V dsSAT ))

[0021] Where, I sub represents the subthreshold leakage current of the RK main control chip, μ n represents the electron mobility corresponding to the chip circuit parameters, C ox represents the gate oxide capacitance per unit area corresponding to the chip circuit parameters, W represents the transistor channel width corresponding to the chip circuit parameters, L represents the channel length corresponding to the chip circuit parameters, V th represents the transistor threshold voltage corresponding to the chip circuit parameters, V in represents the transistor gate voltage corresponding to the chip circuit parameters, n represents the transistor subthreshold slope factor corresponding to the chip circuit parameters, θ represents the channel length modulation parameter corresponding to the chip circuit parameters, Vds Denotes the drain-source voltage corresponding to the chip circuit parameters, V dssAT Denotes the value of the drain-source voltage corresponding to the chip circuit parameters in the saturation region;

[0022] Analyze the leakage current of the RK main control chip according to the subthreshold leakage current.

[0023] Optionally, the circuit optimization of the RK main control chip according to the static power consumption to obtain an optimized RK main control chip includes:

[0024] Determine the high-power consumption area of the RK main control chip according to the static power consumption;

[0025] Mark the discontinuous working area of the high-power consumption area;

[0026] Construct the power gating logic of the RK main control chip based on the discontinuous working area;

[0027] Calculate the chip performance loss of the power gating logic;

[0028] When the chip performance loss meets the preset chip performance threshold, perform circuit optimization on the RK main control chip according to the power gating logic to obtain the optimized RK main control chip.

[0029] Optionally, the calculation of the chip performance loss of the power gating logic includes:

[0030] Determine the power gating area of the power gating logic;

[0031] Analyze the active state performance of the power gating area;

[0032] Based on the active state performance and the power gating area, use the following formula to calculate the chip performance loss of the power gating logic:

[0033] P loss = C perform × ((T tran / T act ) + F switch × T tran )

[0034] Where, Ploss represents the chip performance loss of the power gating logic, C perform represents the performance loss coefficient, T tran represents the time for the power gating area corresponding to the power gating logic to transition from the active state to the non-active state, F switch represents the switching frequency of the power gating area corresponding to the power gating logic, T act represents the active state performance of the power gating area corresponding to the power gating logic.

[0035] Optionally, calculating the task similarity and task complexity of the chip tasks includes:

[0036] Defining a task feature vector for the chip tasks;

[0037] Calculating the task similarity of the chip tasks according to the task feature vector;

[0038] Defining a task complexity index for the chip tasks;

[0039] Calculating the task complexity of the chip tasks according to the task complexity index.

[0040] Optionally, performing task reconstruction on the chip tasks based on the task similarity and task complexity to obtain reconstructed chip tasks, including:

[0041] Clustering the chip tasks according to the task similarity to obtain clustered chip tasks;

[0042] Determining the tasks to be decomposed in the clustered chip tasks through the task complexity;

[0043] Identifying the task entities of the tasks to be decomposed;

[0044] Defining decomposition indexes for the tasks to be decomposed based on the task entities;

[0045] Decomposing the tasks to be decomposed through the decomposition indexes to obtain decomposed chip tasks;

[0046] Combining the decomposed chip tasks and the clustered chip tasks to construct the reconstructed chip tasks of the chip tasks.

[0047] Optionally, calculating the task load of the reconstructed chip tasks on the task processing unit according to the power consumption feature library by using a preset load analysis algorithm includes:

[0048] Determining the key performance indicators of the task processing unit;

[0049] Determining the power consumption features of the reconstructed chip tasks in the power consumption feature library;

[0050] Determining the algorithm parameters of the load analysis algorithm according to the key performance indicators;

[0051] Analyzing the task load of the reconstructed chip tasks on the task processing unit by using the load analysis algorithm based on the power consumption features and the algorithm parameters.

[0052] Optionally, analyzing the chip optimization voltage and chip optimization frequency of the optimized RK main control chip according to the task load includes:

[0053] Determine the current chip voltage and current chip frequency of the optimized RK main control chip;

[0054] Analyze the voltage-frequency characteristics of the optimized RK main control chip according to the current chip voltage and current chip frequency;

[0055] Based on the voltage-frequency characteristics, establish a voltage-frequency-performance relationship model of the optimized RK main control chip;

[0056] Define the load optimization target of the optimized RK main control chip;

[0057] Through the task load and the load optimization target, use the voltage-frequency-performance relationship model to analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip.

[0058] To solve the above problems, the present invention also provides a low-power scheduling system for an RK main control chip, and the system includes:

[0059] An application scenario analysis module, configured to analyze the static power consumption of the RK main control chip, perform circuit optimization on the RK main control chip according to the static power consumption to obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip;

[0060] A power consumption characteristic library construction module, configured to define the working mode of the optimized RK main control chip in the chip application scenario, record the power consumption data of the working mode, and establish a power consumption characteristic library of the optimized RK main control chip through the power consumption data;

[0061] A chip task reconstruction module, configured to obtain the chip tasks of the optimized RK main control chip, calculate the task similarity and task complexity of the chip tasks, and perform task reconstruction on the chip tasks based on the task similarity and task complexity to obtain reconstructed chip tasks;

[0062] A task load analysis module, configured to calculate the task priority of the reconstructed chip tasks, construct a sequence of chip tasks for the reconstructed chip tasks according to the task priority, configure the task processing unit of the sequence of chip tasks, and calculate the task load of the reconstructed chip tasks on the task processing unit according to the power consumption characteristic library using a preset load analysis algorithm;

[0063] The low power consumption scheduling module is used to analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip according to the task load, and perform low power consumption scheduling of the optimized RK main control chip based on the chip optimization voltage and chip optimization frequency.

[0064] Compared with the problems described in the background technology, firstly, through the in-depth analysis of static power consumption, the unnecessary power consumption loss in the chip is effectively identified, and then the circuit is optimized, the power consumption of the optimized RK main control chip is reduced, and the energy efficiency ratio is improved, which helps to extend the battery life, reduce the heating of the equipment, and improve the user experience. Secondly, the application scenario of the optimized RK main control chip is determined and the working mode is defined, which helps to construct a power consumption feature library in a targeted manner. The feature library provides accurate power consumption data support for chip task scheduling, making the scheduling strategy more efficient and reasonable. Thirdly, by calculating the task similarity and task complexity, the chip task is reconstructed, and the flexibility and efficiency of task processing are improved. The calculation of task priority and the construction of sequential chip tasks enable the task processing unit to prioritize key tasks according to actual needs, ensuring the stability and real-time performance of the system. Finally, the power consumption feature library and the load analysis algorithm are used to optimize the voltage and frequency of the RK main control chip in combination with the task load analysis, and low-power scheduling is realized. This scheduling strategy not only reduces the overall power consumption, but also ensures the performance requirements of the chip under different working modes, and achieves a balance between performance and power consumption. Therefore, the present invention can improve the power consumption optimization effect of the RK main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A schematic flow chart of a low power consumption scheduling method for an RK master control chip provided by an embodiment of the present invention;

[0066] Figure 2 A schematic diagram of a module for implementing a low-power scheduling method for the RK master control chip provided in an embodiment of the present invention.

[0067] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0068] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0069] The embodiments of the present application provide a low-power scheduling method for an RK main control chip. The execution subject of the low-power scheduling method for the RK main control chip includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiments of the present application. In other words, the low-power scheduling method for the RK main control chip can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0070] Embodiment 1:

[0071] Referring to Figure 1 As shown, it is a flowchart of the low-power scheduling method for the RK main control chip provided by an embodiment of the present invention. In this embodiment, the low-power scheduling method for the RK main control chip includes:

[0072] S1. Analyze the static power consumption of the RK main control chip, optimize the circuit of the RK main control chip according to the static power consumption to obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip.

[0073] The present invention can comprehensively analyze the static power consumption of the RK main control chip by analyzing the static power consumption of the RK main control chip and provide a basis for reducing power consumption.

[0074] Specifically, the analysis of the static power consumption of the RK main control chip includes:

[0075] Construct a circuit model of the RK main control chip;

[0076] Define the simulation parameters of the circuit model, and analyze the circuit behavior under the simulation parameters through the circuit model;

[0077] Extract the leakage current data of the RK main control chip through the circuit behavior;

[0078] Analyze the leakage current of the RK main control chip according to the leakage current data;

[0079] Based on the leakage current, determine the static power consumption of the RK main control chip.

[0080] Among them, the circuit model refers to a model that simulates the actual circuit structure and behavior of the RK main control chip. The simulation parameters refer to a set of parameters used for circuit simulation, including but not limited to power supply voltage, temperature, process deviation, transistor size, threshold voltage and other parameters. The circuit behavior refers to the response of the circuit model under given simulation parameters, including characteristics such as current, voltage, and power changing with time. The leakage current data refers to the quantified information about current leakage extracted from circuit simulation, including subthreshold leakage current, gate leakage current, and reverse bias leakage current, etc. The leakage current refers to the tiny current flow that still exists in the circuit when there is no external signal input (i.e., the chip is in a static state). The static power consumption refers to the power consumed by the chip in an inactive state (i.e., when no logical operations are being performed).

[0081] Further, analyzing the leakage current of the RK main control chip according to the leakage current data includes:

[0082] Determining the chip circuit parameters of the RK main control chip according to the leakage current data;

[0083] Based on the chip circuit parameters, calculating the subthreshold leakage current of the RK main control chip using the following formula:

[0084] I sub =μ n C ox (W / L)(V th -V in ) n (1+θ(V ds -V dsSAT ))

[0085] Among them, I sub represents the subthreshold leakage current of the RK main control chip, μ n represents the electron mobility corresponding to the chip circuit parameters, C ox represents the gate oxide capacitance per unit area corresponding to the chip circuit parameters, W represents the transistor channel width corresponding to the chip circuit parameters, L represents the channel length corresponding to the chip circuit parameters, V th represents the transistor threshold voltage corresponding to the chip circuit parameters, V in represents the transistor gate voltage corresponding to the chip circuit parameters, n represents the transistor subthreshold slope factor corresponding to the chip circuit parameters, θ represents the channel length modulation parameter corresponding to the chip circuit parameters, V ds represents the drain-source voltage corresponding to the chip circuit parameters, V dssAT represents the value of the drain-source voltage in the saturation region corresponding to the chip circuit parameters;

[0086] Analyzing the leakage current of the RK main control chip according to the subthreshold leakage current.

[0087] Among them, the subthreshold leakage current refers to the tiny current existing between the drain and source of a transistor when the chip operates in the subthreshold region. The electron mobility refers to the migration ability of electrons under the action of an electric field. The gate oxide capacitance per unit area refers to the gate oxide capacitance per unit area. The transistor channel width refers to the width of the transistor channel. The channel length refers to the length of the transistor channel. The transistor threshold voltage refers to the minimum gate voltage required for the transistor to change from the off state to the on state. The transistor gate voltage refers to the voltage applied to the transistor gate. The transistor subthreshold slope factor refers to the factor describing the relationship between the gate voltage and the drain-source current of the transistor in the subthreshold region. The channel length modulation parameter reflects the channel length modulation effect. The drain-source voltage refers to the voltage between the drain and source of the transistor. The drain-source voltage value in the saturation region refers to the drain-source voltage value when the transistor operates in the saturation region.

[0088] According to the static power consumption, the present invention optimizes the circuit of the RK main control chip, and the optimized RK main control chip obtained can effectively reduce the static power consumption of the RK main control chip while maintaining its performance and reliability.

[0089] Specifically, the optimizing the circuit of the RK main control chip according to the static power consumption to obtain the optimized RK main control chip includes:

[0090] Determining the high-power consumption region of the RK main control chip according to the static power consumption;

[0091] Marking the discontinuous working regions of the high-power consumption region;

[0092] Constructing the power gating logic of the RK main control chip based on the discontinuous working regions;

[0093] Calculating the chip performance loss of the power gating logic;

[0094] When the chip performance loss meets the preset chip performance threshold, optimizing the circuit of the RK main control chip according to the power gating logic to obtain the optimized RK main control chip.

[0095] Among them, the high-power consumption area refers to the part that consumes the most static power in the RK main control chip. The discontinuous working area refers to the area that does not need to work during certain time periods during chip operation. The power gating logic refers to the circuit used to control the power switches of different areas in the chip. The chip performance loss refers to the value of the chip performance degradation caused by implementing the power gating logic. The chip performance threshold refers to the acceptable range of chip performance degradation. The optimized RK main control chip refers to the chip design that reduces static power consumption through implementing power gating logic and other circuit optimization technologies while maintaining or minimizing performance loss.

[0096] Specifically, calculating the chip performance loss of the power gating logic includes:

[0097] Determining the power gating area of the power gating logic;

[0098] Analyzing the active state performance of the power gating area;

[0099] Based on the active state performance and the power gating area, calculating the chip performance loss of the power gating logic using the following formula:

[0100] P loss =C perform ×((T tran / T act )+F switch ×T tran )

[0101] Where, P loss represents the chip performance loss of the power gating logic, C perrform represents the performance loss coefficient, T tran represents the time for the power gating area corresponding to the power gating logic to transition from the active state to the non-active state, F switch represents the switching frequency of the power gating area corresponding to the power gating logic, and T act represents the active state performance of the power gating area corresponding to the power gating logic.

[0102] Among them, the power gating area refers to the specific part in the chip controlled by the power gating logic. The active state performance refers to the performance of the power gating area in the active state. The performance loss coefficient refers to the adjustment factor used to adjust the performance loss according to design requirements and priorities. The switching frequency refers to the number of transitions of the power gating area from the active state to the non-active state (or vice versa) per unit time.

[0103] It should be explained that the chip application scenario refers to the specific environment and use for which the chip will be used, such as consumer electronics, smart home, computer, vehicle-mounted, etc. scenarios.

[0104] S2. Define the working modes of the optimized RK main control chip in the chip application scenarios, record the power consumption data of the working modes, and establish a power consumption characteristic library of the optimized RK main control chip based on the power consumption data.

[0105] It should be explained that the working modes refer to different working states of the optimized RK main control chip in the chip application scenarios, such as active mode, idle mode, sleep mode, standby mode, etc. The power consumption data refers to the measured values of the current and voltage consumed by the chip in different working modes.

[0106] By establishing the power consumption characteristic library of the optimized RK main control chip based on the power consumption data, the present invention can establish a comprehensive, accurate and easily accessible power consumption characteristic library of the RK main control chip, providing data support for chip design and power management optimization. The power consumption characteristic library is a database that contains information about the power consumption of electronic devices or components under different operating conditions and states.

[0107] S3. Obtain the chip tasks of the optimized RK main control chip, calculate the task similarity and task complexity of the chip tasks, and reconstruct the chip tasks based on the task similarity and task complexity to obtain reconstructed chip tasks.

[0108] It should be explained that the chip tasks refer to determining and defining the specific operations and functions that the chip needs to perform in a specific application scenario.

[0109] Calculating the task similarity and task complexity of the chip tasks by the present invention can optimize the tasks, thereby improving the task processing efficiency.

[0110] Specifically, calculating the task similarity and task complexity of the chip tasks includes:

[0111] Define the task feature vector of the chip tasks;

[0112] Calculate the task similarity of the chip tasks according to the task feature vector;

[0113] Define the task complexity index of the chip tasks;

[0114] Calculate the task complexity of the chip tasks according to the task complexity index.

[0115] Among them, the task feature vector is a multi-dimensional vector that contains quantization values in each dimension describing the characteristics of the chip task. The task similarity is a parameter that quantifies the similarity degree between two task feature vectors. The task complexity index refers to a set of quantization criteria for evaluating the complexity of a task, such as algorithm complexity, data complexity, and control complexity. The task complexity refers to comprehensively evaluating the complexity of a task based on the task complexity index. The complexity scoring function is a function used to calculate the score of a task on a specific complexity index. The score is the quantization result of a task on a specific complexity index. The weight refers to the relative importance assigned to each complexity index.

[0116] Based on the task similarity and task complexity, the present invention performs task reconstruction on the chip task, and the obtained reconstructed chip task can improve the processing effect of the task, thereby reducing the power consumption of the chip.

[0117] Specifically, the performing task reconstruction on the chip task based on the task similarity and task complexity to obtain a reconstructed chip task includes:

[0118] Clustering the chip task according to the task similarity to obtain a clustered chip task;

[0119] Determining the task to be decomposed in the clustered chip task through the task complexity;

[0120] Identifying the task entity of the task to be decomposed;

[0121] Defining the decomposition index of the task to be decomposed based on the task entity;

[0122] Decomposing the task to be decomposed through the decomposition index to obtain a decomposed chip task;

[0123] Combining the decomposed chip task and the clustered chip task to construct the reconstructed chip task of the chip task.

[0124] Among them, the clustered chip task refers to a task set obtained by grouping tasks with similar characteristics according to the task similarity. The task to be decomposed refers to a task with relatively high complexity identified during the clustering process. The task entity refers to the specific operation or computing unit in the task to be decomposed. The decomposition index refers to the criteria for evaluating and guiding task decomposition, including criteria such as the granularity of the task, dependency relationship, and parallelism. The decomposed chip task refers to splitting the task to be decomposed into smaller and more manageable subtasks according to the decomposition index. The reconstructed chip task refers to combining the decomposed subtasks and the original clustered tasks to reconstruct an optimized task set.

[0125] Optionally, clustering the chip tasks to obtain clustered chip tasks can be implemented through a K-means clustering function.

[0126] Optionally, the task entity for identifying the task to be decomposed can be determined by an abstract syntax tree to identify basic execution units such as functions, loops, and conditional statements in the task code to be decomposed.

[0127] S4. Calculate the task priority of the reconstructed chip task. According to the task priority, construct a sequence of chip tasks for the reconstructed chip task, configure the task processing unit for the sequence of chip tasks, and calculate the task load of the reconstructed chip task on the task processing unit using a preset load analysis algorithm according to the power consumption feature library.

[0128] The present invention calculates the task priority of the reconstructed chip task to provide a basis for task scheduling and resource allocation. Among them, the task priority refers to the urgency of each task relative to other tasks when the reconstructed chip task needs to be executed. The sequence of chip tasks refers to a set of tasks arranged in the order of task priority.

[0129] The present invention configures the task processing unit for the sequence of chip tasks, which can effectively configure the task processing unit for the sequence of chip tasks to ensure that tasks can be executed efficiently and reliably. Among them, the task processing unit refers to a unit that optimizes the RK main control chip for corresponding application scenarios for task processing (such as an arithmetic logic unit (ALU), a floating-point unit (FPU), a vector processing unit, etc.).

[0130] The present invention calculates the task load of the reconstructed chip task on the task processing unit using a preset load analysis algorithm according to the power consumption feature library, which can effectively calculate the task load of the reconstructed chip task on the task processing unit and provide decision support for task scheduling and resource management.

[0131] Specifically, calculating the task load of the reconstructed chip task on the task processing unit using a preset load analysis algorithm according to the power consumption feature library includes:

[0132] Determine the key performance indicators of the task processing unit;

[0133] Determine the power consumption characteristics of the reconstructed chip task in the power consumption feature library;

[0134] Determine the algorithm parameters of the load analysis algorithm according to the key performance indicators;

[0135] Based on the power consumption characteristics and the algorithm parameters, analyze the task load of the reconstructed chip task on the task processing unit using the load analysis algorithm.

[0136] Among them, the key performance indicators refer to a series of quantitative indicators for measuring the performance of the task processing unit, such as CPU processing speed, memory bandwidth, I / O throughput rate, energy efficiency ratio (such as performance per watt), etc. The power consumption characteristics refer to the power consumption behavior of the task processing unit when executing a specific task. The algorithm parameters refer to the variables used in the load analysis algorithm to adjust the algorithm behavior and output. The load analysis algorithm refers to the algorithm for calculating the load generated by the reconstruction chip task on the task processing unit. The analyzed load refers to the load of the reconstruction chip task on the task processing unit calculated after applying the load analysis algorithm.

[0137] S5. Analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip according to the task load, and perform low-power scheduling of the optimized RK main control chip based on the chip optimization voltage and chip optimization frequency.

[0138] According to the task load, the present invention can effectively analyze and determine the optimization voltage and frequency of the RK main control chip by analyzing the chip optimization voltage and chip optimization frequency of the optimized RK main control chip, so as to achieve better performance and energy efficiency ratio.

[0139] Specifically, the analyzing the chip optimization voltage and chip optimization frequency of the optimized RK main control chip according to the task load includes:

[0140] Determine the current chip voltage and current chip frequency of the optimized RK main control chip;

[0141] Analyze the voltage-frequency characteristics of the optimized RK main control chip according to the current chip voltage and current chip frequency;

[0142] Based on the voltage-frequency characteristics, establish a voltage-frequency-performance relationship model of the optimized RK main control chip;

[0143] Define the load optimization target of the optimized RK main control chip;

[0144] Through the task load and the load optimization target, analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip by using the voltage-frequency-performance relationship model.

[0145] Among them, the current chip voltage refers to the voltage level actually used by the RK main control chip when performing a task, the current chip frequency refers to the clock speed actually used by the RK main control chip when performing a task, the voltage-frequency characteristic refers to the different frequency ranges in which the chip can stably operate under different voltages, the voltage-frequency-performance relationship model refers to the description of the relationship between chip voltage, frequency and performance (such as processing speed, energy efficiency ratio), the load optimization target refers to the optimization purpose set according to task requirements and system design goals, such as reducing power consumption, the chip optimization voltage refers to the most suitable chip operating voltage determined to achieve the load optimization target, and the chip optimization frequency refers to the most suitable chip operating frequency determined to achieve the load optimization target.

[0146] Optionally, the voltage-frequency-performance relationship model of the optimized RK main control chip based on the voltage-frequency characteristics can be constructed by a dynamic system model based on differential equations or difference equations.

[0147] Compared with the problems described in the background technology, firstly, through the in-depth analysis of static power consumption, the unnecessary power consumption loss in the chip is effectively identified, and then the circuit is optimized, the power consumption of the optimized RK main control chip is reduced, and the energy efficiency ratio is improved, which helps to extend the battery life, reduce the heating of the equipment, and improve the user experience. Secondly, the application scenario of the optimized RK main control chip is determined and the working mode is defined, which helps to construct a power consumption feature library in a targeted manner. The feature library provides accurate power consumption data support for chip task scheduling, making the scheduling strategy more efficient and reasonable. Thirdly, by calculating the task similarity and task complexity, the chip task is reconstructed, and the flexibility and efficiency of task processing are improved. The calculation of task priority and the construction of sequential chip tasks enable the task processing unit to prioritize key tasks according to actual needs, ensuring the stability and real-time performance of the system. Finally, the power consumption feature library and the load analysis algorithm are used to optimize the voltage and frequency of the RK main control chip in combination with the task load analysis, and low-power scheduling is realized. This scheduling strategy not only reduces the overall power consumption, but also ensures the performance requirements of the chip under different working modes, and achieves a balance between performance and power consumption. Therefore, the present invention can improve the power consumption optimization effect of the RK main control chip.

[0148] Embodiment 2:

[0149] like Figure 2 The figure shows a functional module diagram of a low power consumption scheduling system of an RK main control chip of the present invention.

[0150] The low-power scheduling system 200 of an RK main control chip described in the present invention can be installed in an electronic device. According to the functions achieved, the low-power scheduling system of the RK main control chip may include an application scenario analysis module 201, a power consumption feature library construction module 202, a chip task reconstruction module 203, a task load analysis module 204, and a low-power scheduling module 205. The modules described in the present invention may also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0151] In the embodiments of the present invention, the functions of each module / unit are as follows:

[0152] The application scenario analysis module 201 is used to analyze the static power consumption of the RK main control chip, optimize the circuit of the RK main control chip according to the static power consumption to obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip;

[0153] The power consumption feature library construction module 202 is used to define the working modes of the optimized RK main control chip in the chip application scenario, record the power consumption data of the working modes, and establish a power consumption feature library of the optimized RK main control chip through the power consumption data;

[0154] The chip task reconstruction module 203 is used to obtain the chip tasks of the optimized RK main control chip, calculate the task similarity and task complexity of the chip tasks, and reconstruct the chip tasks based on the task similarity and task complexity to obtain reconstructed chip tasks;

[0155] The task load analysis module 204 is used to calculate the task priorities of the reconstructed chip tasks, construct sequence chip tasks of the reconstructed chip tasks according to the task priorities, configure task processing units of the sequence chip tasks, and calculate the task loads of the reconstructed chip tasks on the task processing units according to the power consumption feature library by using a preset load analysis algorithm;

[0156] The low-power scheduling module 205 is used to analyze the chip optimized voltage and chip optimized frequency of the optimized RK main control chip according to the task loads, and perform low-power scheduling of the optimized RK main control chip based on the chip optimized voltage and chip optimized frequency.

[0157] Specifically, each module in the low-power scheduling system 200 of the RK main control chip described in the embodiments of the present invention uses the same technical means as the Figure 1 low-power scheduling method of the RK main control chip described above and can produce the same technical effects, which will not be elaborated here.

[0158] It is obvious to those skilled in the art that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0159] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A low power consumption scheduling method for an RK master control chip, characterized in that: The method comprises: Analyze the static power consumption of the RK main control chip, optimize the circuit of the RK main control chip according to the static power consumption, obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip; Define the working mode of the optimized RK main control chip in the chip application scenario, and record the power consumption data of the working mode, and establish the power consumption feature library of the optimized RK main control chip through the power consumption data; Obtaining the chip task of the optimized RK main control chip, calculating the task similarity and task complexity of the chip task, and reconstructing the chip task based on the task similarity and task complexity to obtain the reconstructed chip task; Calculate the task priority of the reconstruction chip task, construct a sequence chip task of the reconstruction chip task according to the task priority, configure a task processing unit of the sequence chip task, and calculate the task load of the reconstruction chip task in the task processing unit according to the power consumption feature library using a preset load analysis algorithm; According to the task load, the chip optimization voltage and chip optimization frequency of the optimized RK main control chip are analyzed, and low power consumption scheduling of the optimized RK main control chip is performed based on the chip optimization voltage and chip optimization frequency.

2. The low power consumption scheduling method of the RK master control chip as claimed in claim 1, characterized in that: The analysis of the static power consumption of the RK main control chip includes: Constructing a circuit model of the RK main control chip; Defining simulation parameters of the circuit model, and analyzing circuit behavior under the simulation parameters through the circuit model; Extracting leakage current data of the RK main control chip through the circuit behavior; Analyzing the leakage current of the RK main control chip according to the leakage current data; Based on the leakage current, the static power consumption of the RK main control chip is determined.

3. The low power consumption scheduling method of the RK master control chip as claimed in claim 2, characterized in that: The step of analyzing the leakage current of the RK main control chip according to the leakage current data includes: Determining chip circuit parameters of the RK main control chip according to the leakage current data; Based on the chip circuit parameters, the subthreshold leakage current of the RK master chip is calculated using the following formula: I sub =μ n C ox (W / L)(V th -V in ) n (1+θ(V ds -V dsSAT )) Among them, I sub Represents the subthreshold leakage current of the RK main control chip, μ n Indicates the electron mobility corresponding to the chip circuit parameters, C ox represents the gate oxide capacitance per unit area corresponding to the chip circuit parameters, W represents the transistor channel width corresponding to the chip circuit parameters, L represents the channel length corresponding to the chip circuit parameters, V th Indicates the transistor threshold voltage corresponding to the chip circuit parameters, V in represents the transistor gate voltage corresponding to the chip circuit parameters, n represents the transistor subthreshold slope factor corresponding to the chip circuit parameters, θ represents the channel length modulation parameter corresponding to the chip circuit parameters, V ds Indicates the drain-source voltage corresponding to the chip circuit parameters, V dsSAT Indicates that the drain-source voltage corresponding to the chip circuit parameters is in the saturation region; According to the subthreshold leakage current, the leakage current of the RK main control chip is analyzed.

4. The low power consumption scheduling method of the RK master control chip as claimed in claim 3, characterized in that: The circuit optimization of the RK main control chip is performed according to the static power consumption to obtain an optimized RK main control chip, including: According to the static power consumption, determining the high power consumption area of ​​the RK main control chip; Marking discontinuous working areas of the high power consumption area; Based on the discontinuous working area, construct the power gating logic of the RK main control chip; Calculating chip performance loss of the power gating logic; When the chip performance loss meets a preset chip performance threshold, the RK main control chip is circuit optimized according to the power gating logic to obtain the optimized RK main control chip.

5. The low power consumption scheduling method of the RK master control chip as claimed in claim 4, characterized in that: The calculating the chip performance loss of the power gating logic includes: Determining a power gating region of the power gating logic; analyzing activity state performance of the power-gated region; Based on the active state performance and the power gating area, the chip performance loss of the power gating logic is calculated using the following formula: P loss =C perform ×((T tran / T act )+F switch ×T tran ) Among them, P loss represents the chip performance loss of power gating logic, C perform represents the performance loss coefficient, T tran Indicates the time it takes for the power gating logic corresponding to the power gating region to change from an active state to an inactive state, F switch Indicates the switching frequency of the power gating logic corresponding to the power gating region, T act Indicates the active state performance of the power-gated logic corresponding to the power-gated region.

6. The low power consumption scheduling method of the RK master control chip as claimed in claim 5, characterized in that: The calculating the task similarity and task complexity of the chip task includes: Defining a task feature vector of the chip task; Calculating the task similarity of the chip task according to the task feature vector; Defining a task complexity index of the chip task; The task complexity of the chip task is calculated according to the task complexity index.

7. The low power consumption scheduling method of the RK master control chip as claimed in claim 6, characterized in that: The step of reconstructing the chip task based on the task similarity and the task complexity to obtain the reconstructed chip task includes: Clustering the chip tasks according to the task similarities to obtain clustered chip tasks; Determining the tasks to be decomposed in the cluster chip task according to the task complexity; Identify the task entity of the task to be decomposed; Based on the task entity, defining the decomposition index of the task to be decomposed; Decomposing the task to be decomposed by using the decomposition index to obtain a decomposed chip task; The chip decomposition task and the chip clustering task are combined to construct a chip reconstruction task of the chip task.

8. The low power consumption scheduling method of the RK master control chip as claimed in claim 7, characterized in that: The calculating the task load of the reconstruction chip task in the task processing unit by using a preset load analysis algorithm according to the power consumption feature library includes: Determining key performance indicators of the task processing unit; Determine the power consumption characteristics of the chip reconstruction task in the power consumption characteristics library; Determining algorithm parameters of the load analysis algorithm according to the key performance indicators; Based on the power consumption characteristics and the algorithm parameters, the load analysis algorithm is used to analyze the task load of the chip reconstruction task on the task processing unit.

9. The low power consumption scheduling method of the RK master control chip as claimed in claim 8, characterized in that: The step of analyzing the chip optimization voltage and chip optimization frequency of the RK main control chip according to the task load includes: Determine the current chip voltage and current chip frequency of the optimized RK main control chip; Analyze and optimize the voltage-frequency characteristics of the RK main control chip according to the current chip voltage and the current chip frequency; Based on the voltage-frequency characteristics, a voltage-frequency-performance relationship model of the optimized RK main control chip is established; Defining the load optimization target of the optimized RK main control chip; The chip optimization voltage and chip optimization frequency of the optimized RK main control chip are analyzed by using the task load and the load optimization target and the voltage-frequency-performance relationship model.

10. A low power consumption scheduling system for an RK master control chip, characterized in that: The system comprises: An application scenario analysis module is used to analyze the static power consumption of the RK main control chip, optimize the circuit of the RK main control chip according to the static power consumption, obtain an optimized RK main control chip, and determine the chip application scenario of the optimized RK main control chip; A power consumption feature library construction module is used to define the working mode of the optimized RK main control chip in the chip application scenario, and record the power consumption data of the working mode, and establish the power consumption feature library of the optimized RK main control chip through the power consumption data; A chip task reconstruction module is used to obtain the chip task of the optimized RK main control chip, calculate the task similarity and task complexity of the chip task, and reconstruct the chip task based on the task similarity and task complexity to obtain a reconstructed chip task; A task load analysis module, used to calculate the task priority of the reconstruction chip task, construct a sequence chip task of the reconstruction chip task according to the task priority, configure a task processing unit of the sequence chip task, and calculate the task load of the reconstruction chip task in the task processing unit according to the power consumption feature library using a preset load analysis algorithm; The low power consumption scheduling module is used to analyze the chip optimization voltage and chip optimization frequency of the optimized RK main control chip according to the task load, and perform low power consumption scheduling of the optimized RK main control chip based on the chip optimization voltage and chip optimization frequency.

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