Topological island-based circuit identification method, system and equipment, and medium

Abstract

The invention provides a circuit identification method, system and device based on a topological island and a medium, and is applied to the technical field of power electronic electromagnetic transient simulation. The circuit identification method based on the topological island comprises the following steps: acquiring all hierarchical circuit diagrams in a graphical interface; determining a first topological island corresponding to the circuit simulation model according to a connection relationship among elements in all hierarchical circuit diagrams; according to the first topology island corresponding to the circuit simulation model, port node numbers of elements in the circuit diagrams of all levels are determined, and the port node numbers are used for determining a matrix in the circuit simulation model. According to the method, the connection relationship between the elements in the graphical interface circuit diagram is abstracted into a topological island, and the port node numbers of the elements in the circuit diagram are identified and marked, so that input data are provided for a circuit simulation model, and a required simulation result is obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic electromagnetic transient simulation, and particularly to a circuit identification method, system, device and medium based on topological islands. Background Art

[0002] Power electronic electromagnetic transient simulation technology is one of the tools for power system analysis. The electromagnetic transient simulation technology can be used to analyze the operating state of the power system, establish a model of the power system, predict the power flow condition when a fault occurs in the power system, and improve the safety performance, reliability and stability of the power system.

[0003] Currently, in the process of power electronic electromagnetic transient simulation analysis, a circuit simulation model is generally built through a graphical interface. After the simulation model is built, it is necessary to establish a connection between the interface and the calculation program through a topology identification method, and then convert the circuit topology connection relationship in the interface into matrix parameters required for calculation, which are used as the input of the calculation program for iterative solution, so as to obtain the required simulation results.

[0004] However, there is currently a lack of technical means to convert the circuit topology connection relationship in the interface into matrix parameters. Summary of the Invention

[0005] In order to overcome the above defect that there is currently a lack of technical means to convert the circuit topology connection relationship in the interface into matrix parameters, the present invention provides a circuit identification method based on topological islands, and the method includes:

[0006] Obtain all hierarchical circuit diagrams in the graphical interface;

[0007] Determine the first topological island corresponding to the circuit simulation model according to the connection relationship between components in all the hierarchical circuit diagrams;

[0008] Determine the port node numbers of the components in all the hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, and the port node numbers are used to determine the matrix in the circuit simulation model.

[0009] Further, the determining the first topological island corresponding to the circuit simulation model according to the connection relationship between components in all the hierarchical circuit diagrams includes:

[0010] For each hierarchical circuit diagram in all the hierarchical circuit diagrams, traverse the connecting lines between components in the hierarchical circuit diagram to determine the second topological island corresponding to the connecting line; link the ports of the components corresponding to the connecting line to the second topological island;

[0011] Determine the first topological island corresponding to the circuit simulation model according to the second topological island corresponding to the connecting line in each hierarchical circuit diagram.

[0012] Further, determining the second topological island corresponding to the connection line includes:

[0013] If the existing topological island contains the connection line, add the connection line to the existing topological island;

[0014] If the current saved topological island does not contain the connection line, create a new topological island and add the connection line to the new topological island;

[0015] Further, adding the connection line to the existing topological island includes:

[0016] If there is another topological island other than the existing topological island that contains the connection line, merge the existing topological island and the other topological island, and add the connection line to the merged topological island.

[0017] Further, the existing topological island contains the connection line, which means that the rectangle where the existing topological island is located contains the connection line, and there are other connection lines in the existing topological island that intersect with the connection line.

[0018] Further, the first topological island corresponding to the circuit simulation model includes a grounding topological island, and the grounding topological island is linked to the grounding ports in all hierarchical circuit diagrams.

[0019] Further, linking the ports of the components corresponding to the connection line to the second topological island includes:

[0020] If there are components including multi-phase ports in the hierarchical circuit diagram, traverse each phase port of the component; for each phase port, perform the following operations:

[0021] If there is a second topological island that the phase port is not linked to, link the phase port to the second topological island corresponding to the connection line;

[0022] Otherwise, clone the second topological island corresponding to the connection line and link the phase port to the cloned second topological island.

[0023] Further, linking the ports of the components corresponding to the connection line to the second topological island includes:

[0024] If there are short-circuit components in the hierarchical circuit diagram, perform short-circuit processing on the short-circuit components and merge the second topological islands linked by the ports of the short-circuit components.

[0025] Further, determining the port node numbers of the components in all hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model includes:

[0026] Number all the topological islands in the first topological island;

[0027] According to the numbers of each topological island among all the topological islands, determine the port node numbers of the components in each topological island.

[0028] Further, the determining the port node numbers of the components in each topological island according to the numbers of each topological island among all the topological islands includes:

[0029] For each topological island, determine the number of the topological island as the port node numbers of the components in the topological island.

[0030] On the other hand, the present invention also provides a circuit recognition system based on topological islands, including:

[0031] An acquisition module, configured to acquire all hierarchical circuit diagrams in the graphical interface;

[0032] A determination module, configured to determine the first topological island corresponding to the circuit simulation model according to the connection relationships between components in all the hierarchical circuit diagrams;

[0033] A numbering module, configured to determine the port node numbers of the components in all the hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, where the port node numbers are used to determine the matrix in the circuit simulation model.

[0034] Further, the determination module is specifically configured to, for each hierarchical circuit diagram among all the hierarchical circuit diagrams, traverse the connection lines between components in the hierarchical circuit diagram, determine the second topological island corresponding to the connection line; link the port of the component corresponding to the connection line to the second topological island; and determine the first topological island corresponding to the circuit simulation model according to the second topological islands corresponding to the connection lines in each hierarchical circuit diagram.

[0035] Further, the first topological island corresponding to the circuit simulation model includes a grounding topological island, and the grounding topological island is linked with the grounding ports in all the hierarchical circuit diagrams.

[0036] Further, the determination module is specifically configured to, if there is a component including multi-phase ports in the hierarchical circuit diagram, traverse each phase port of the component; for each phase port, perform the following operations: if there is a second topological island that the phase port is not linked to, link the phase port to the second topological island corresponding to the connection line; otherwise, clone the second topological island corresponding to the connection line, and link the phase port to the cloned second topological island.

[0037] Further, the determining module is specifically configured to, if a short - circuit element is included in the hierarchical circuit diagram, perform a short - circuit process on the short - circuit element and merge the second topological islands linked by the ports of the short - circuit element.

[0038] Further, the numbering module is specifically configured to number all the topological islands in the first topological island; and determine the port node numbers of the components in each topological island according to the numbers of each topological island in all the topological islands.

[0039] On the other hand, the present invention also provides a computer device, which is characterized by including: one or more processors;

[0040] The processor is used to store one or more programs;

[0041] When the one or more programs are executed by the one or more processors, the circuit recognition method based on topological islands described in any one of the above is implemented.

[0042] On the other hand, the present invention also provides a computer - readable storage medium, which is characterized in that a computer program is stored thereon, and when the computer program is executed, the circuit recognition method based on topological islands described in any one of the above is implemented.

[0043] Compared with the prior art, the beneficial effects of the present invention are:

[0044] The present invention provides a circuit recognition method based on topological islands, including: obtaining all hierarchical circuit diagrams in a graphical interface; determining a first topological island corresponding to a circuit simulation model according to the connection relationships between components in all hierarchical circuit diagrams; and determining the port node numbers of components in all hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, where the port node numbers are used to determine a matrix in the circuit simulation model. In the present invention, the connection relationships between components in the graphical - interface circuit diagram are abstracted into topological islands, and the port node numbers of components in the circuit diagram are identified and marked, so as to provide input data for the circuit simulation model and obtain the required simulation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic flowchart of the circuit recognition method based on topological islands of the present invention;

[0046] Figure 2 is a schematic flowchart of the process of adding connection lines to topological islands of the present invention;

[0047] Figure 3 is a schematic flowchart of the algorithm for whether a topological island contains a connection line of the present invention;

[0048] Figure 4 is a schematic flowchart of the process of processing poly - phase circuit components of the present invention;

[0049] Figure 5 It is a schematic structural diagram of the circuit recognition system based on topological islands of the present invention. Specific embodiments

[0050] The following further elaborates on the specific embodiments of the present invention with reference to the accompanying drawings.

[0051] Embodiment 1:

[0052] A circuit recognition method based on topological islands provided by the present invention has a flow schematic diagram as Figure 1 shown, including:

[0053] Step 101: Obtain all hierarchical circuit diagrams in the graphical interface.

[0054] Step 102: Determine the first topological island corresponding to the circuit simulation model according to the connection relationship between components in all hierarchical circuit diagrams.

[0055] Step 103: Determine the port node numbers of the components in all hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, and the port node numbers are used to determine the matrix in the circuit simulation model.

[0056] In the embodiment of the present invention, the connection relationship between components in the circuit diagram of the graphical interface is abstracted into a topological island, and the port node numbers of the components in the circuit diagram are identified and marked, so as to provide input data for the circuit simulation model and obtain the required simulation results.

[0057] At least one hierarchical circuit diagram is displayed in the graphical interface. Generally, multiple hierarchical circuit diagrams are displayed in the graphical interface. In the embodiment of the present invention, all hierarchical circuit diagrams are processed. When processing each hierarchical circuit diagram, the circuit diagram can be identified by traversing the circuit diagram page. In the embodiment of the present invention, no limitation is imposed on the obtaining process in the above step 101.

[0058] In one implementation, in step 102 above, for each hierarchical circuit diagram in all hierarchical circuit diagrams, traverse the connection lines between components in the hierarchical circuit diagram, determine the second topological island corresponding to the connection line; link the ports of the components corresponding to the connection line to the second topological island; according to the second topological islands corresponding to the connection lines in each hierarchical circuit diagram, determine the first topological island corresponding to the circuit simulation model. In this implementation, by traversing the current circuit diagram page, identifying the connection lines in the current hierarchical circuit diagram, and then adding the connection lines to the topological islands, the topological island system of the current hierarchical circuit diagram is constructed. A topological island can be understood as aggregating components with direct or indirect connection relationships, and the topological island can reflect the connection relationships between components in the circuit diagram of the power grid. Optionally, the topological island can include information for identifying components (such as but not limited to the port coordinates of the components), and can also include information for identifying the connection lines between components (such as but not limited to the coordinates of the connection lines).

[0059] Exemplarily, the process of determining the second topological island corresponding to the connection line includes:

[0060] If the existing topological island contains the connection line, add the connection line to the existing topological island;

[0061] If the currently saved topological island does not contain the connection line, create a new topological island and add the connection line to the new topological island.

[0062] When adding the connection line to the existing topological island, it can also be determined whether the connection line is also included in other topological islands. If there are other topological islands outside the existing topological island that contain the connection line, merge the existing topological island and the other topological islands, and add the connection line to the merged topological island.

[0063] See Figure 2 , which is a schematic flow diagram for determining the second topological island corresponding to the connection line, including the following steps:

[0064] Determine whether the existing topological island contains the connection line;

[0065] If not, create a new topological island and add the connection line to the new topological island;

[0066] If so, determine whether there are multiple topological islands that all contain the connection line; if not, add the connection line to the existing topological island; if so, merge the multiple topological islands and add the connection line to the merged topological island.

[0067] Exemplarily, the existing topological island contains the connection line includes: the rectangle where the existing topological island is located contains the connection line, and there are other connection lines in the existing topological island that intersect with the connection line. The schematic flow diagram can be as Figure 3As shown, this process is also applicable to the judgment process of whether other topological islands contain connection lines, including the following steps:

[0068] Judge whether the rectangle where the topological island (such as the existing topological island) is located contains the connection line;

[0069] If not, it is determined that the topological island does not contain the connection line;

[0070] If so, judge whether the connection line inside the topological island intersects with the connection line; if not, it is determined that the topological island does not contain the connection line; if so, it is determined that the topological island contains the connection line.

[0071] In step 102 above, by traversing the circuit elements, the ports of the elements can be linked to the corresponding second topological islands.

[0072] In some scenarios, some components include ground ports. Optionally, the first topological island corresponding to the circuit simulation model includes a ground topological island, and the ground topological island is linked to the ground ports in all hierarchical circuit diagrams, that is, all ground ports are linked to the same ground topological island.

[0073] In some scenarios, the ports of some components are polyphase ports. At this time, all the second topological islands on the associated circuit paths can be cloned according to the number of phases. For example, linking the ports of the component corresponding to the connection line to the second topological island includes: if there are components with polyphase ports in the hierarchical circuit diagram, traverse each phase port of the component; for each phase port, perform the following operations: if there is a second topological island that the phase port is not linked to, link the phase port to the second topological island corresponding to the connection line; otherwise, clone the second topological island corresponding to the connection line and link the phase port to the cloned second topological island. For example, if a certain component includes three-phase ports, each phase port is linked to the corresponding topological island, which is beneficial to subsequent simulation calculations.

[0074] The schematic diagram of the process of this example can be as Figure 4 shown, including the following steps:

[0075] First, traverse the polyphase circuit components;

[0076] Then, traverse the topological islands connected to the polyphase ports;

[0077] Then, traverse the ports connected to the topological islands;

[0078] Finally, traverse the components where the ports are located.

[0079] In some scenarios, some components are treated as short - circuited during simulation calculations, and such components are called short - circuit components. When connecting the ports of the components corresponding to the connection lines to the second topological island, if the circuit diagram at this level includes short - circuit components, the short - circuit components can be short - circuited, and the second topological islands linked by the ports of the short - circuit components can be merged. Optionally, a set of short - circuit components can be pre - saved. If it is recognized that there are components in the circuit diagram at this level in the set of short - circuit components, it can be considered that the circuit diagram at this level includes short - circuit components. The set of short - circuit components includes, but is not limited to, ammeters and / or wattmeters.

[0080] In the embodiments of the present invention, the same processing flow is performed for each level of the circuit diagram, and the similarities will not be elaborated.

[0081] In one implementation, in step 103 above, all topological islands in the first topological island can be numbered; according to the numbers of each topological island in all topological islands, the port node numbers of the components in each topological island are determined. For example, all topological islands are numbered sequentially incrementally or decrementally starting from a set value. The set value is, for example but not limited to, 1, that is, all topological islands can be numbered sequentially starting from 1.

[0082] Optionally, if the first topological island includes a grounded topological island, the grounded topological island can be numbered with a value different from the above - mentioned set value, for example but not limited to 0.

[0083] Exemplarily, when determining the port node numbers of the components in each topological island according to the numbers of each topological island in all topological islands, for each topological island, the number of the topological island can be determined as the port node number of the components in the topological island. That is, in this example, the number of the topological island connected to the circuit component port is the port node number of the circuit component port.

[0084] In another example, when determining the port node numbers of the components in each topological island according to the numbers of each topological island in all topological islands, for each topological island, an element identifier and / or a port identifier can be added to the basis of the number of the topological island, so as to determine the port node number of the component.

[0085] The embodiments of the present invention will be described below with a specific example, including the following process:

[0086] 5.1 Construct topological islands

[0087] Traverse the current circuit diagram page, identify the connection lines, and add the connection lines to the existing topological islands or create new topological islands, so as to construct the topological island system of the current circuit diagram. The specific process is as described above Figure 2 shown. Optionally, the algorithm flow for determining whether a topological island contains connection lines is as described above Figure 3 shown.

[0088] 5.2 Linking Circuit Elements to Corresponding Topological Islands

[0089] Traverse the circuit elements and link the ports of the elements to the corresponding topological islands. All ground ports are linked to the same ground topological island.

[0090] 5.3 Processing Polyphase Circuit Elements

[0091] In the circuit diagram, the ports of some elements are polyphase ports. It is necessary to clone all the topological islands on the associated circuit paths according to the number of phases, and the processing flow is as described above. Figure 4 As shown.

[0092] 5.4 Processing Short-Circuited Circuit Elements

[0093] Elements such as ammeters and wattmeters need to be treated as short-circuited during simulation calculations, and the topological islands at both ends are merged.

[0094] 5.5 Processing the Next-Level Circuit Diagram

[0095] When there is a next-level circuit diagram on the current circuit diagram page, the processes of 5.1 to 5.5 are executed sequentially for each level of the circuit diagram.

[0096] 5.6 Topological Island Numbering

[0097] After the processing of 5.1 to 5.5, the ground topological island is numbered 0, and all other topological islands are numbered sequentially from 1. The number of the topological island connected to the port of the circuit element is the node number of the circuit element port.

[0098] The embodiment of the present invention proposes a circuit recognition method based on topological islands, which recognizes the circuit topological connection relationship of the simulation model built by the graphical interface. The basic idea is: constructing the topological islands of the circuit simulation model, linking the circuit elements to the corresponding topological islands, processing polyphase circuit elements, short-circuited circuit elements, and traversing all levels of circuit diagrams, obtaining the topological islands corresponding to the circuit simulation model, and finally numbering the topological islands to obtain the node numbers of the circuit element ports. By abstracting the connection relationship between elements into topological islands, identifying and marking the node numbers of the circuit element ports, input data can be provided for the simulation calculation program. The present invention provides a circuit recognition method for power electronics electromagnetic transient simulation analysis, which can be applied to the actual application of power electronics electromagnetic transient simulation analysis.

[0099] Embodiment 2:

[0100] Based on the same inventive concept, the present invention also provides a circuit recognition system based on topological islands. The structural schematic diagram is as Figure 5 shown, including:

[0101] An acquisition module for acquiring all levels of circuit diagrams in the graphical interface;

[0102] A determining module, configured to determine a first topological island corresponding to a circuit simulation model according to the connection relationships between components in circuit diagrams of all levels.

[0103] A numbering module, configured to determine port node numbers of components in circuit diagrams of all levels according to the first topological island corresponding to the circuit simulation model, where the port node numbers are used to determine a matrix in the circuit simulation model.

[0104] In a possible implementation manner, the determining module is specifically configured to, for each circuit diagram of all levels of circuit diagrams, traverse the connection lines between components in the circuit diagram of the level, determine a second topological island corresponding to the connection line; link the ports of the components corresponding to the connection line to the second topological island; and determine the first topological island corresponding to the circuit simulation model according to the second topological islands corresponding to the connection lines in each circuit diagram of the level.

[0105] In a possible implementation manner, the determining module is specifically configured to, if a connection line is included in the existing topological island saved, add the connection line to the existing topological island; if the connection line is not included in the currently saved topological island, create a new topological island and add the connection line to the new topological island.

[0106] In a possible implementation manner, the determining module is specifically configured to, if a connection line is included in other topological islands outside the existing topological island, merge the existing topological island and the other topological islands, and add the connection line to the merged topological island.

[0107] In a possible implementation manner, that a connection line is included in the existing topological island includes: the connection line is included within the rectangle where the existing topological island is located, and there are other connection lines in the existing topological island that intersect with the connection line.

[0108] In a possible implementation manner, the first topological island corresponding to the circuit simulation model includes a grounding topological island, and the grounding topological island is linked to grounding ports in circuit diagrams of all levels.

[0109] In a possible implementation manner, the determining module is specifically configured to, if there are components including multi-phase ports in the circuit diagram of the level, traverse each phase port of the component; for each phase port, perform the following operations: if there is a second topological island to which the phase port is not linked, link the phase port to the second topological island corresponding to the connection line; otherwise, clone the second topological island corresponding to the connection line, and link the phase port to the cloned second topological island.

[0110] In a possible implementation manner, the determining module is specifically configured to, if there are short-circuit components in the circuit diagram of the level, perform a short-circuit process on the short-circuit components, and merge the second topological islands to which the ports of the short-circuit components are linked.

[0111] In a possible implementation, the numbering module is specifically configured to number all the topological islands in the first topological island; and determine the port node numbers of the components in each topological island according to the numbers of each topological island among all the topological islands.

[0112] In a possible implementation, the numbering module is specifically configured to, for each topological island, determine the number of the topological island as the port node numbers of the components in the topological island.

[0113] Embodiment 3:

[0114] Based on the same inventive concept, the present invention further provides a computer device, which includes a processor and a memory. The memory is used to store a computer program, and the computer program includes program instructions. The processor is used to execute the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, and is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the computer storage medium to implement the corresponding method flow or corresponding function, so as to implement the steps of a circuit recognition method based on topological islands in the above embodiments.

[0115] Embodiment 4:

[0116] Based on the same inventive concept, the present invention also provides a storage medium, specifically a computer-readable storage medium (Memory). A computer-readable storage medium is a memory device in a computer device, used to store programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and, of course, the extended storage medium supported by the computer device. The computer-readable storage medium provides a storage space, and the operating system of the terminal is stored in this storage space. Moreover, one or more instructions suitable for being loaded and executed by the processor are stored in this storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. The one or more instructions stored in the computer-readable storage medium can be loaded and executed by the processor to implement the steps of a circuit recognition method based on topological islands in the above embodiments.

[0117] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0118] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0119] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the specified functions in Figure 1 one flow or multiple flows and / or blocks Figure 1The functions specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in one Figure 1 One process or more processes and / or boxes Figure 1 step of the functions specified in one or more boxes.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the scope of its protection. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that after reading the present invention, various changes, modifications or equivalent replacements can still be made to the specific implementation manners of the application. However, these changes, modifications or equivalent replacements are all within the scope of the protection of the claims pending for approval of the application.

Claims

1. A circuit recognition method based on topological islands, characterized in that, Including: Obtain all hierarchical circuit diagrams in the graphical user interface; Determine the first topological island corresponding to the circuit simulation model according to the connection relationship between components in the all hierarchical circuit diagrams; Determine the port node numbers of components in the all hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, and the port node numbers are used to determine the matrix in the circuit simulation model.

2. The method according to claim 1, characterized in that, The determining the first topological island corresponding to the circuit simulation model according to the connection relationship between components in the all hierarchical circuit diagrams includes: For each hierarchical circuit diagram in the all hierarchical circuit diagrams, traverse the connection lines between components in the hierarchical circuit diagram to determine the second topological island corresponding to the connection line; link the ports of the components corresponding to the connection line to the second topological island; Determine the first topological island corresponding to the circuit simulation model according to the second topological island corresponding to the connection line in each hierarchical circuit diagram.

3. The method according to claim 2, characterized in that, The determining the second topological island corresponding to the connection line includes: If the existing topological island contains the connection line, add the connection line to the existing topological island; If the current saved topological island does not contain the connection line, create a new topological island and add the connection line to the new topological island.

4. The method according to claim 3, characterized in that, The adding the connection line to the existing topological island includes: If there is another topological island other than the existing topological island that contains the connection line, merge the existing topological island and the other topological island, and add the connection line to the merged topological island.

5. The method according to claim 3 or 4, characterized in that, The existing topological island contains the connection line includes: the rectangle where the existing topological island is located contains the connection line, and there are other connection lines intersecting with the connection line in the existing topological island.

6. The method according to any one of claims 1 - 4, characterized in that, The first topological island corresponding to the circuit simulation model includes a grounding topological island, and the grounding topological island is linked to the grounding ports in the all hierarchical circuit diagrams.

7. The method according to any one of claims 2 - 4, characterized in that, The linking the ports of the components corresponding to the connection line to the second topological island includes: If there are components including multi-phase ports in the hierarchical circuit diagram, traverse each phase port of the component; for each phase port, perform the following operations: If there is a second topological island that the phase port is not linked to, link the phase port to the second topological island corresponding to the connection line; Otherwise, clone the second topological island corresponding to the connection line and link the phase port to the cloned second topological island.

8. The method according to any one of claims 2 - 4, characterized in that, The linking the ports of the components corresponding to the connection line to the second topological island includes: If there are short-circuit components in the hierarchical circuit diagram, perform short-circuit processing on the short-circuit components and merge the second topological islands linked by the ports of the short-circuit components.

9. The method according to any one of claims 1 - 4, characterized in that, The determining the port node numbers of components in the all hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model includes: Number all topological islands in the first topological island; Determine the port node numbers of components in each topological island according to the numbers of each topological island in the all topological islands.

10. The method according to claim 9, characterized in that, The determining the port node numbers of components in each topological island according to the numbers of each topological island in the all topological islands includes: For each of the topological islands, determine the number of the topological island as the port node numbers of the components in the topological island.

11. A circuit recognition system based on topological islands, characterized in that, Comprising: An acquisition module, configured to acquire all hierarchical circuit diagrams in the graphical interface; A determination module, configured to determine a first topological island corresponding to the circuit simulation model according to the connection relationships between components in all the hierarchical circuit diagrams; A numbering module, configured to determine the port node numbers of the components in all the hierarchical circuit diagrams according to the first topological island corresponding to the circuit simulation model, where the port node numbers are used to determine the matrix in the circuit simulation model.

12. The system according to claim 11, wherein The determination module is specifically configured to, for each hierarchical circuit diagram in all the hierarchical circuit diagrams, traverse the connection lines between components in the hierarchical circuit diagram to determine a second topological island corresponding to the connection line; link the ports of the components corresponding to the connection line to the second topological island; and determine a first topological island corresponding to the circuit simulation model according to the second topological islands corresponding to the connection lines in each hierarchical circuit diagram.

13. The system according to claim 11 or 12, wherein The first topological island corresponding to the circuit simulation model includes a grounding topological island, and the grounding topological island is linked to the grounding ports in all the hierarchical circuit diagrams.

14. The system according to claim 12, wherein The determination module is specifically configured to, if there is a component including polyphase ports in the hierarchical circuit diagram, traverse each phase port of the component; for each phase port, perform the following operations: if there is a second topological island to which the phase port is not linked, link the phase port to the second topological island corresponding to the connection line; otherwise, clone the second topological island corresponding to the connection line and link the phase port to the cloned second topological island.

15. The system according to claim 12, wherein The determination module is specifically configured to, if the hierarchical circuit diagram includes a short-circuit component, perform a short-circuit process on the short-circuit component and merge the second topological islands to which the ports of the short-circuit component are linked.

16. The system according to claim 11 or 12, wherein The numbering module is specifically configured to number all the topological islands in the first topological island; and determine the port node numbers of the components in each topological island according to the numbers of each topological island in all the topological islands.

17. A computer device, wherein Comprising: One or more processors; The processor is configured to store one or more programs; When the one or more programs are executed by the one or more processors, implement the topological island-based circuit recognition method according to any one of claims 1 to 10.

18. A computer-readable storage medium, wherein There is a computer program stored thereon, and when the computer program is executed, implement the topological island-based circuit recognition method according to any one of claims 1 to 10.

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