Multi-core particle system cost quantitative analysis and optimization method

Abstract

The invention belongs to the technical field of core particle systems, and discloses a multi-core particle system cost quantitative analysis and optimization method, which comprises the following steps of: 1, decomposing SoC (System on Chip) into core particles; 2, constructing a cost model; 3, defining model initialization parameters; and 4, executing an optimization strategy: after defining the initialization parameters of the model, executing the optimization strategy to solve the optimal cost, carrying out iteration for multiple times until the cost calculation result reaches the minimum value, and outputting a total cost evaluation result and a multi-core particle system process node selection and particle size division scheme. According to the method, the quantitative analysis model of the multi-core-particle system is constructed and can cover the whole process of the multi-core-particle system based on 2.5 D packaging, the whole process comprises a design cost model, a manufacturing model, a packaging model and a testing model, NRE cost, D2D interface cost and testing cost are considered at the same time, the cost of the multi-core-particle system is analyzed more accurately, and the method is suitable for large-scale popularization and application. And scheme guidance in the aspects of core particle division granularity and core particle process node selection is provided.

Description

Technical Field

[0001] The present invention belongs to the technical field of chiplet systems, and particularly relates to a method for cost quantification analysis and optimization of a multi-chiplet system. Background Art

[0002] In the post-Moore era, the design of single-chip large-scale integrated circuits (SoCs) faces huge challenges in terms of manufacturing cost and scalability. By dividing an SoC into multiple small chiplets and integrating them into a multi-chiplet system using 2.5D advanced packaging, the manufacturing yield can be significantly improved and the system cost can be reduced. The multi-chiplet system divides the SoC into functional chiplets with different areas and quantities according to application requirements. Different chiplets can be manufactured using heterogeneous process nodes. Chiplets pursuing performance adopt advanced process nodes, and cost-sensitive chiplets adopt mature process nodes.

[0003] For cost-sensitive multi-chiplet systems, cost quantification analysis is crucial for guiding early design decisions. The granularity of chiplet division and the selection of process nodes are the main factors affecting the system cost. The division granularity determines the number and size of chiplets in the system. Fine-grained division will result in higher interface and bonding costs, while coarse-grained division provides a relatively limited improvement in chiplet yield. The process node will affect the area of the chiplet and thus the interposer cost, and the non-recurring engineering (NRE) costs of chiplets with different process nodes vary significantly. However, existing cost models for multi-chiplet systems do not consider the impact of mixed multi-process nodes on cost, and only discuss the single-level division granularity for system cost optimization methods.

[0004] On the one hand, in terms of the accuracy of cost modeling models, these models do not consider the impact of multi-process nodes on costs. For example, in the cost model in the literature [A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma, A. Narayan, and V. Srinivas, "Cross-layer co-optimization of network design and chiplet placement in 2.5-d systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 12, pp. 5183 - 5196, 2020.], the cost model analyzes the area of the micro-bump region of the interface, considers the network topology and link solutions, but ignores the non-recurring engineering (NRE) cost. In the literature [D. Stow, I. Akgun, R. Barnes, P. Gu, and Y. Xie, "Cost analysis and cost-driven ip reuse methodology for soc design based on 2.5d / 3d integration," in 2016 IEEE / ACM International Conference on Computer Aided Design (ICCAD), pp. 1–6, 2016.], the model evaluates the total cost based on the metal layer and the number of gates to estimate the wafer cost, but does not mention the interface area overhead in system design. The literature [P. Ehrett, T. Austin, and V. Bertacco, "Chopin: Composing cost-effective custom chips with algorithmic chiplets," in 2021 IEEE 39th International Conference on Computer Design (ICCD), pp. 395–399, 2021.] considers both the recurring engineering (RE) cost and the non-recurring engineering (NRE) cost, but ignores the die-to-die (D2D) overhead when evaluating the optimal partitioning granularity, resulting in inaccurate estimation of the area overhead in fine-grained partitioning.In contrast, the literature [Y.Feng and K.Ma, "Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration," in Proceedings of the 59th ACM / IEEE Design Automation Conference, DAC’22, (New York, NY, USA), p.121–126, Association for Computing Machinery, 2022.] first introduced the D2D overhead and NRE cost, but its cost analysis was limited to the case of a small number of chiplets.

[0005] On the other hand, it is reflected in cost optimization. The cost optimization of existing methods is limited to a single dimension. The previous cost models have limited discussions on the costs of multiple process nodes. The chiplet quantization model assumes that all chiplets are manufactured using the same process node, such as in the literature [Y. Feng and K. Ma, "Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration," in Proceedings of the 59th ACM / IEEE Design Automation Conference, DAC’22, (New York, NY, USA), p. 121–126, Association for Computing Machinery, 2022.]. This assumption ignores the different requirements of performance-critical cores and non-performance-critical cores in terms of process nodes, which may lead to performance overkill or cost waste. Similarly, the Chopin model assumes that all algorithmic chiplets use the 40nm node, such as in the literature [P. Ehrett, T. Austin, and V. Bertacco, "Chopin: Composing cost-effective custom chips with algorithmic chiplets," in 2021 IEEE 39th International Conference on Computer Design (ICCD), pp. 395–399, 2021.].These models lack a comprehensive quantitative analysis of multi-process node designs and mainly focus on single-dimensional cost factors, such as partitioning granularity (e.g., in the literature [P. Ehrett, T. Austin, and V. Bertacco, “Chopin: Composing cost-effective custom chips with algorithmic chiplets,” in 2021 IEEE 39th International Conference on Computer Design (ICCD), pp. 395–399, 2021.]) or wafer metal layers (e.g., in the literature [D. Stow, I. Akgun, R. Barnes, P. Gu, and Y. Xie, “Cost analysis and cost-driven ip reuse methodology for soc design based on 2.5d / 3d integration,” in 2016 IEEE / ACM International Conference on Computer Aided Design (ICCAD), pp. 1–6, 2016.]). Although the model in the literature [Y. Feng and K. Ma, “Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration,” in Proceedings of the 59th ACM / IEEE Design Automation Conference, DAC’22, (New York, NY, USA), p. 121–126, Association for Computing Machinery, 2022.] considers the impact of the number of chiplets or process node selection on the system cost, its analysis scope is limited to designs with 2 to 5 chiplets and three process nodes. Such single-dimensional cost optimization methods are prone to falling into local cost optima and cannot solve for the global optimal cost of multi-chiplet systems.

[0006] Therefore, it is necessary to construct a cost model for heterogeneous node multi-chiplet systems and use multi-dimensional optimization methods to reduce the total system cost. Summary of the Invention

[0007] The object of the present invention is to provide a method for quantitative cost analysis and optimization of a multi-chiplet system to solve the above technical problems.

[0008] To solve the above technical problems, the specific technical solution of a multi-die system cost quantification analysis and optimization method of the present invention is as follows:

[0009] A multi-die system cost quantification analysis and optimization method includes the following steps:

[0010] Step 1: Decompose the SoC into dies: Input the system function requirements, and divide them into multiple functional dies according to the system requirements;

[0011] Step 2: Build a cost model: Model the multi-die system cost according to the 2.5D advanced packaging design process and divide it into four parts, respectively build a design cost model, a manufacturing cost model, a packaging cost model, and a test cost model, and add the cost calculation results of the four links to obtain the final total cost of the multi-die system;

[0012] Step 3: Define the model initialization parameters: Define the system chip production volume and the process nodes of each die, configure the number of dies in the system according to the division result of Step 1, and define the reuse factor value for different functional dies;

[0013] Step 4: Execute the optimization strategy: After defining the model initialization parameters, execute the optimization strategy to solve for the optimal cost, perform multiple iterations until the cost calculation result reaches the minimum value, and output the total cost evaluation result and the multi-die system process node selection and division granularity scheme.

[0014] Further, Step 1 includes the following steps:

[0015] Step 1.1: Due to the differences in the application scenarios of chip products, the dies need to be reusable. First, decompose the original SoC design of a certain area scale into a multi-die system. When designing, first clarify the system function requirements and design a multi-die architecture scheme according to the requirements;

[0016] Step 1.2: After completing the multi-die architecture scheme, divide it into multiple functional dies according to the system requirements; the original SoC design is divided into multiple dies with different functions, and the dies are interconnected through an interposer. The micro-bumps of the die and the physical layer of the D2D interface are bonded to the interposer, and the interposer is connected to the packaging substrate through C4-bumps. Finally, the multi-die system uses solder balls as pins; the number and area of the dies in the multi-die system are modified according to the requirements, and the process nodes of the dies and the interposer can also be heterogeneous nodes. Further, in Step 2, a design cost model C design , a manufacturing cost model C mfg , a packaging cost model C package , and a test cost model C test, add up the cost calculation results of the four links to obtain the total cost of the final multi-die system. The total cost of the final multi-die system is:

[0017] C total = C design + C mfg + C package + C test .

[0018] Furthermore, the design cost model described in step 2 is as follows. According to the die area, the NRE design cost corresponding to the process node, the reuse factor, and the production volume of the multi-die system chips, the unit chip design cost is calculated using the weighted allocation method:

[0019]

[0020] where n = 4, which is the number of dies divided in the system, w i is the weight of the total design cost of the system occupied by each die, C NRE is the 10nm design NRE cost, R i = 10, which is the reuse factor corresponding to each die representing the number of reusable products, V chip is the production volume of the multi-die system chips. The calculation of the w i is shown in the following formula:

[0021]

[0022] where S i = 25mm 2 is the area of each die, d i is the design complexity of the die corresponding to the process node.

[0023] Furthermore, the manufacturing cost model described in step 2 is as follows. Considering the wafer price of manufacturing the die, the number and yield of the dies manufactured on the wafer, the number and yield of the interposers manufactured on the wafer, and the 2.5D advanced packaging bonding cost and yield, calculate the cost involved in the manufacturing process. The manufacturing cost is:

[0024]

[0025] where C mfg_2.5D is the manufacturing cost of the 2.5D packaged multi-die system, C interposer is the unit cost of the interposer, Y interposer is the manufacturing yield of the interposer, C chiplet is the unit cost of the die, Y chiplet is the manufacturing yield of the die, C bond_2.5D is the bonding cost of the 2.5D packaging, Ybond_2.5D is the bonding yield in 2.5D packaging;

[0026] The unit cost C of the die chiplet and the unit cost C of the interposer interposer The calculation formulas are as follows:

[0027]

[0028] where C wafer is the wafer cost in the die manufacturing process, N chiplet is the number of dice that can be manufactured and processed from a single wafer, C int_wafer is the wafer cost in the interposer manufacturing process, N int is the number of interposers that can be manufactured and processed from a single wafer;

[0029] The number of dice N chiplet and the number of interposers N int The calculation formulas are as follows:

[0030]

[0031] where is the diameter of the circular wafer used for die manufacturing, A chiplet is the die area, A D2D is the interface area between dice, is the diameter of the circular wafer used for interposer manufacturing, A int is the interposer area;

[0032] The die yield Y chiplet and the interposer yield Y interposer The calculation formulas are as follows:

[0033]

[0034]

[0035] where D0 is the defect density coefficient of the die manufacturing wafer, ∈ is the failure parameter of the corresponding die, D1 is the defect density coefficient of the interposer manufacturing wafer, and α is the failure parameter of the corresponding die. Further, the packaging cost model described in step 2 is as follows. The packaging cost is determined by the 2.5D advanced packaging type, the chip packaging area, and the number of chip pins. The calculation formula for the packaging cost is as follows:

[0036]

[0037] where N p is the number of packaging pins, A packis the encapsulation area, Y pack is the yield of 2.5D advanced packaging. The coefficient μ, coefficient a, coefficient b, and exponent c are cost factors corresponding to 2.5D packaging.

[0038] Furthermore, the test model described in step 2 is as follows. Wafer testing is to test each die on the wafer. The final chip testing occurs after the chip is fully encapsulated and is used for the final functional verification of the encapsulated chip. Stack testing is to test the interconnection between dies and the interposer or the vertical interconnection between dies. The formula for calculating the testing cost in the entire multi-die system production process is as follows:

[0039]

[0040] Among them, C wt is the cost of wafer testing, C st is the stack testing, C ct is the final chip testing, FC wt and FC st and FC ct are the fault coverage rates of the corresponding tests respectively.

[0041] Furthermore, step 3 includes the following specific steps:

[0042] Step 3.1: In the cost model constructed in step 2, input and define the area of the original SoC design chip, the chip production volume V chip , and the process node of the die;

[0043] Step 3.2: In the cost model constructed in step 2, decompose the SoC into the number of dies, and set the reuse factor of all dies after decomposition. The reuse factor is determined according to the number of different products in which the designed die can be reused.

[0044] Furthermore, step 4 includes the following specific steps:

[0045] Step 4.1: Use the Bayesian optimization algorithm to explore the design space of the cost model, solve the cost value of the multi-die system, and execute the collaborative optimization strategy of partitioning granularity and process node;

[0046] Step 4.2: For the optimized granularity partitioning, the size of the die partitioning granularity n can be adjusted;

[0047] Step 4.3: For the optimized heterogeneous nodes, adjust the most suitable process node to reduce the total cost;

[0048] After executing the optimization strategy, the calculated cost result will be obtained. Determine whether it is the lowest cost. If the cost is not the lowest value, the optimization strategy will continue to be executed. If the lowest cost is iterated, the total cost result and the process node and granularity scheme of the multi-die system will be output.

[0049] A method for cost quantification analysis and optimization of a multi-die system of the present invention has the following advantages:

[0050] (1) The present invention supports cost quantification comparison between SoC design and multi-die design, and provides cost advantage analysis for the design of a multi-die system with 2.5D packaging for designers.

[0051] (2) The present invention constructs a multi-die system quantification analysis model that can cover the entire process of a multi-die system based on 2.5D packaging, including a design cost model, a manufacturing model, a packaging model, and a test model. Moreover, compared with other cost models, it simultaneously considers NRE costs, D2D interface costs, and test costs, and more accurately analyzes the cost of the multi-die system.

[0052] (3) The cost optimization method proposed by the present invention supports multi-level collaborative optimization of die partitioning granularity and process node selection, avoiding falling into a local optimal solution of multi-die cost. Compared with the unoptimized multi-die system, the total cost of the multi-die system after optimization iteration can be further reduced.

[0053] (4) The cost quantification model and cost optimization method of the present invention provide early design decisions for the design of a multi-die system, and provide scheme guidance for die partitioning granularity and die process node selection. Description of the Drawings

[0054] Figure 1 is a flowchart for constructing and optimizing a cost quantification analysis model of a multi-die system of the present invention;

[0055] Figure 2 is a schematic structural diagram of a multi-die system based on 2.5D advanced packaging. Detailed Embodiments

[0056] In order to better understand the purpose, structure, and function of the present invention, the following further describes in detail a method for cost quantification analysis and optimization of a multi-die system of the present invention with reference to the accompanying drawings.

[0057] As Figure 1 shown, a method for cost quantification analysis and optimization of a multi-die system of the present invention includes the following steps:

[0058] Step 1: Decompose the SoC into dies, input the system function requirements, and divide various functional dies according to the system requirements. The specific steps are as follows:

[0059] Step 1.1: Due to differences in the application scenarios of chip products, the dies need to be reusable. First, the original area of 100 mm 2The 10nm process node SoC design is decomposed into a multi-die system. When designing, it is necessary to first clarify the system function requirements and design a multi-die architecture solution according to the requirements.

[0060] Step 1.2: After completing the multi-die architecture solution, divide it into four functional dies according to the system requirements.

[0061] The schematic diagram of the multi-die system structure is as Figure 2 shown. The original SoC design is divided into multiple dies with different functions, and the dies are interconnected through an interposer; the micro-bumps of the die and the physical layer of the D2D interface are bonded to the interposer, and the interposer is connected to the package substrate through C4-bumps. Finally, the multi-die system uses solder balls as pins; different from the SoC design, the number and area of the dies in the multi-die system can be modified according to requirements, and the process nodes of the dies and the interposer can also be heterogeneous nodes.

[0062] Step 2: Build a cost model: Model the cost of the multi-die system according to the 2.5D advanced packaging design process and divide it into four types of costs for modeling, namely, build a design cost model C design , a manufacturing cost model C mfg , a packaging cost model C package and a test cost model C test . Add the cost calculation results of the four links to obtain the total cost of the final multi-die system. The total cost of the final multi-die system is:

[0063] C total = C design + C mfg + C package + C test .

[0064] The design cost model described in Step 2 is as follows. According to the die area, the NRE design cost corresponding to the process node, the reuse factor, and the chip production volume of the multi-die system, the unit chip design cost is calculated using the weighted allocation method:

[0065]

[0066] where n = 4, which is the number of dies divided in the system, w i is the weight of the total design cost of each die in the system, C NRE is the 10nm design NRE cost, R i = 10, which is the reuse factor corresponding to each die representing the number of reusable products, V chip is the chip production volume of the multi-die system. The calculation of the w i is shown in the following formula:

[0067]

[0068] where S i = 25 mm 2 is the area of each die, and d i is the design complexity of the die corresponding to the process node.

[0069] The manufacturing cost model described in step 2 is as follows. Considering the wafer price of the manufactured die, the number and yield of the dies manufactured on the wafer, the number and yield of the interposers manufactured on the wafer, and the 2.5D advanced packaging bonding cost and yield, the cost involved in the manufacturing process is calculated. The manufacturing cost is:

[0070]

[0071] where C mfg_2.5D is the manufacturing cost of the multi-die system for 2.5D packaging, C interposer is the unit cost of the interposer, Y interposer is the manufacturing yield of the interposer, C chiplet is the unit cost of the die, Y chiplet is the manufacturing yield of the die, C bond_2.5D = 1.5$, is the bonding cost for 2.5D packaging, and Y bond_2.5D = 95%, which is the bonding yield in 2.5D packaging.

[0072] The unit cost C chiplet of the die and the unit cost C interposer of the interposer are calculated as follows:

[0073]

[0074] where C wafer is the cost of a 300 mm wafer in the manufacturing process of a 10 nm die, C wafer = 11000$, N chiplet is the number of dies that can be manufactured and processed on a single wafer, C int_wafer is the cost of the wafer in the manufacturing process of the interposer, and N int is the number of interposers that can be manufactured and processed on a single wafer.

[0075] The number of dies N chiplet and the number of interposers N int are calculated as follows:

[0076]

[0077] Among them is the diameter of the circular wafer used to manufacture the die, which is 300mm, A chiplet is the die area, A D2D is the interface area between dies, which is approximately 10% of A chiplet in size, is the diameter of the circular wafer used to manufacture the interposer, which is 300mm, A int is the interposer area.

[0078] The die yield Y chiplet and the interposer yield Y interposer are calculated as follows:

[0079]

[0080] Among them, D0 = 0.2 / cm^2, which is the defect density coefficient of the die manufacturing wafer, ∈ = 10, which is the failure parameter corresponding to the die, D1 = 0.06 / cm^2, which is the defect density coefficient of the interposer manufacturing wafer, and α = 6, which is the failure parameter corresponding to the die.

[0081] The packaging cost model described in step 2 is as follows. The packaging cost is determined by the 2.5D advanced packaging type, the chip packaging area, and the number of chip pins. The calculation formula for the packaging cost is as follows:

[0082]

[0083] Among them, N p = 1800, which is the number of packaging pins, A pack The packaging area is the total area of 4 dies plus the D2D interface, Y pack = 95% is the 2.5D advanced packaging yield, the coefficient μ = 3, the coefficient a = 0.00515, the coefficient b = 0.141, and the exponent c = 0.35, which are the cost factors corresponding to the 2.5D packaging;

[0084] The test model described in step 2 is as follows. Wafer testing is to test each die on the wafer. The final chip test occurs after the chip is fully packaged and is used for the final functional verification of the packaged chip; Stack testing is to test the interconnection between dies and the interposer or the vertical interconnection between dies. The calculation formula for the test cost in the entire multi-die system production process is as follows:

[0085]

[0086] Among them, C wt = 0.2$, which is the cost of wafer testing, C st = 0.05$, which is the stack testing cost, C ct= 1.5$, for the final test of the chip, FC wt = 0.99 and FC st = 0.99 and FC ct = 0.95 are the fault coverage rates for the corresponding tests respectively.

[0087] Step 3: Define the model initialization parameters: Define the system chip yield and the process nodes of each die. Configure the number of dice in the system according to the partitioning result of Step 1, and define the reuse factor values for different functional dice;

[0088] Step 3.1: In the cost model constructed in Step 2, input and define the chip area of the original SoC design as 100 mm 2 , the chip yield V chip = 10K, and the process nodes of the dice are all set to 10 nm, the same as the original SoC design. The process node parameters input this time are only initialization parameters and do not represent the process node selection of the final multi-die solution.

[0089] Step 3.2: In the cost model constructed in Step 2, the number of dice after decomposing the SoC is set, and the reuse factor of all dice after decomposition is set. The reuse factor is determined according to the number of different products in which the designed dice can be reused. The number of dice input this time is only an initialization parameter and does not represent the die partitioning result of the final multi-die solution. In this embodiment, there are 4 dice, and the reuse factor of all dice after decomposition is 10, indicating that all dice can be reused in 10 different chip products.

[0090] Step 4: Execute the optimization strategy: After defining the model initialization parameters, execute the optimization strategy to solve for the optimal cost, perform multiple iterations until the cost calculation result reaches the minimum value, and output the total cost evaluation result and the process node selection and partitioning granularity scheme of the multi-die system;

[0091] Step 4.1: Use the Bayesian optimization algorithm to explore the design space of the cost model, solve the cost value of the multi-die system, and execute the collaborative optimization strategy of the partitioning granularity and the process node.

[0092] Step 4.2: For the optimized granularity partitioning, the size of the die partitioning granularity n can be adjusted. Finally, N chiplet and N int , A chiplet , and the final package area A pack and other parameters will all be affected. A smaller number of partitioned dice will result in a decrease in the die yield Y chiplet , but the required number of bonding times and A D2D overhead are lower. When the number of partitioned dice is large, although the yield of a single die is increased, more interface overhead and die bonding times are required, which will increase the system cost.

[0093] Step 4.3: The optimized heterogeneous nodes adjust the most suitable process node to reduce the total cost. The process node affects the die NRE cost and ω i weight value in the design cost model, and also affects the wafer cost price in the manufacturing cost model. Adjusting to a suitable process can optimize the total system cost. In this embodiment, the interposer can be adjusted to the most suitable process node of 65nm. The other functional die of 10nm can be adjusted to calculate the die of 5nm or 7nm. The simulation or IO part adopts 65nm, and the digital logic can adopt mature process nodes such as 16nm / 22nm / 28nm or 40nm.

[0094] After executing the optimization strategy, the calculated cost result will be judged to determine whether it is the lowest cost expenditure. If the cost is not the lowest value, the optimization strategy will continue to be executed. If the lowest cost is iterated, the total cost result and the process node and granularity scheme of the multi-die system will be output. In this embodiment, finally, for this 100mm 2 SoC design is transformed into a multi-die system design. When the partitioning granularity n is 2, the functional die respectively select the process nodes of 7nm and 65nm, and the interposer selects the process node of 65nm, the lowest cost expenditure under the performance constraint can be achieved, and finally the total cost result and the process node and granularity scheme of the multi-die system are output.

[0095] The comparison of different models is shown in the following table:

[0096]

[0097] It can be understood that the present invention is described through some embodiments. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent substitutions can be made to these features and embodiments. In addition, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A multi-chip system cost quantification analysis and optimization method, characterized in that: The steps include: Step 1: Decompose SoC into core particles: Input system functional requirements and divide multiple functional core particles according to the system requirements; Step 2: Construct a cost model: Divide the multi-chip system cost into four parts according to the 2.5D advanced packaging design process for modeling. Construct a design cost model, a manufacturing cost model, a packaging cost model, and a testing cost model respectively. Add the cost calculation results of the four links to obtain the final total cost of the multi-chip system. Step 3: Define model initialization parameters: define the system chip output and each core grain process node, configure the number of core grains in the system according to the division result of step 1, and define the reuse factor value for different functional core grains; Step 4: Execute the optimization strategy: After defining the model initialization parameters, execute the optimization strategy to solve the optimal cost, perform multiple iterations until the cost calculation result reaches the minimum value, and output the total cost evaluation result and the multi-core system process node selection and granularity division plan.

2. The multi-chip system cost quantification analysis and optimization method according to claim 1, characterized in that: The step 1 comprises the following steps: Step 1.1: The differences in chip product application scenarios require that cores can be reused. First, the original SoC design of a certain area scale is decomposed into a multi-core system. When designing, the system function requirements are first clarified, and the multi-core architecture solution is designed according to the requirements; Step 1.2: After completing the multi-chip architecture solution, multiple functional chiplets are divided according to system requirements; the original SoC design is divided into multiple chiplets with different functions, and the chiplets are interconnected through the intermediate layer interposer; the chiplet is bonded to the micro-bump of the D2D interface physical layer and the interposer, and the interposer is connected to the packaging substrate substrate through the C4-bump, and finally the multi-chip system uses solder balls as pins; the number and area of ​​the chiplets in the multi-chip system are modified according to the requirements, and the process nodes of the chiplets and interposers can also be heterogeneous nodes.

3. The multi-chip system cost quantification analysis and optimization method according to claim 1, characterized in that: The step 2 constructs the design cost model C design , Manufacturing Cost Model C mfg , Packaging Cost Model C package And the test cost model C test , add up the cost calculation results of the four links to get the final total cost of the multi-core particle system, and the final total cost of the multi-core particle system is: C total =C design +C mfg +C package +C test 。 4. The multi-core system cost quantification analysis and optimization method according to claim 3, characterized in that: The design cost model described in step 2 is as follows. The unit chip design cost is calculated using a weighted allocation method based on the chip area, NRE design cost corresponding to the process node, reuse factor, and multi-chip system chip production volume: Where n = 4 is the number of core particles divided in the system, w i is the weight of each chip in the total system design cost, C NRE is the 10nm design NRE cost, R i =10, is the reuse factor of each core particle, indicating the number of reusable products, V chip is the multi-chip system chip output, the w i The calculation of is shown in the following formula: Where S i =25mm 2 is the area of ​​each core particle, d i It is the design complexity of the core particle corresponding to the process node.

5. The multi-chip system cost quantification analysis and optimization method according to claim 3, characterized in that: The manufacturing cost model described in step 2 is as follows. Taking into account the price of the wafer for manufacturing the core particles, the number and yield of the core particles manufactured by the wafer, the number and yield of the interposer manufactured by the wafer, and the 2.5D advanced packaging bonding cost and yield, the cost involved in the manufacturing process is calculated. The manufacturing cost is: Among them C mfg_2.5D is the manufacturing cost of the multi-chip system of 2.5D packaging, C interposer is the interposer unit cost, Y interposer is the interposer manufacturing yield, C chiplet is the unit cost of the core, Y chiplet is the manufacturing yield of the core particles, C bond_2.5D is the bonding cost of 2.5D packaging, Y bond_2.5D It is the bonding yield in 2.5D packaging; The unit cost of the core particle is C chiplet and the interposer unit cost C interposer The calculation formula is as follows: Among them C wafer is the wafer cost during the chip manufacturing process, N chiplet is the number of cores that can be manufactured and processed by a single wafer, C int_wafer is the wafer cost of the interposer manufacturing process, N int The number of interposers that can be manufactured on a single wafer; The number of core particles N chiplet and the number of intermediary layers N int The calculation formula is as follows: in is the diameter of the circular wafer used to make the core particles, A chiplet is the core area, A D2D is the interface area between core particles, is the diameter of the circular wafer used to make the interposer, A int is the interposer area; The core particle yield Y chiplet and interposer yield Y interposer The calculation formula is as follows: Where D0 is the defect density coefficient of the wafer manufactured by the core particle, ∈ is the failure parameter of the corresponding core particle, D1 is the defect density coefficient of the wafer manufactured by the interposer, and α is the failure parameter of the corresponding core particle.

6. The multi-chip system cost quantification analysis and optimization method according to claim 3, characterized in that: The packaging cost model described in step 2 is as follows. The packaging cost is determined by the 2.5D advanced packaging type, chip packaging area and chip pin number. The packaging cost calculation formula is as follows: Where N p A is the number of package pins, pack is the package area, Y pack is the yield of 2.5D advanced packaging, coefficient μ, coefficient a, coefficient b and index c are the cost factors corresponding to 2.5D packaging.

7. The multi-chip system cost quantification analysis and optimization method according to claim 3, characterized in that: The test model described in step 2 is as follows: wafer test is to test the die of each die on the wafer, and the chip final test occurs after the chip is fully packaged, which is used to perform the final functional verification of the packaged chip; Stacking test is to test the interconnection between the chiplet and the interposer or the vertical interconnection between the chiplets. The test cost calculation formula in the entire multi-chiplet system production process is as follows: Among them, C wt is the cost of wafer testing, C st For stacking test, C ct For the final test of the chip, FC wt With FC st and FC ct are the fault coverage of the corresponding tests respectively.

8. The multi-chip system cost quantification analysis and optimization method according to claim 1, characterized in that: The step 3 comprises the following specific steps: Step 3.1: In the cost model constructed in step 2, input the original SoC design chip area, chip output V chip , and the process node of the core particle; Step 3.2: In the cost model constructed in step 2, the SoC is decomposed into the number of core particles, and the reuse factor of all the core particles after decomposition is set. The reuse factor is determined according to the number of designed core particles that can be reused in different products.

9. The multi-chip system cost quantification analysis and optimization method according to claim 1, characterized in that: The step 4 comprises the following specific steps: Step 4.1: Use the Bayesian optimization algorithm to explore the cost model design space, solve the cost value of the multi-core system, and implement the partition granularity and process node collaborative optimization strategy; Step 4.2: The optimized granularity division can adjust the size of the core particle division granularity n; Step 4.3: Optimize heterogeneous nodes as described above and adjust the most suitable process node to reduce the total cost; After executing the optimization strategy, the cost result will be calculated to determine whether it is the lowest cost. If the cost is not the lowest value, the optimization strategy will continue to be executed. If the lowest cost is iterated, the total cost result and the multi-core system process node and particle size solution will be output.

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