Prediction method for temperature continuity characteristic of low-temperature MOSFET and model thereof

Abstract

The invention provides a method and a model for predicting the temperature continuity characteristic of a low-temperature MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the method comprises the following steps: designing and preparing a verification structure which covers a full box of the model based on the process size range of the MOSFET; performing direct current characteristic test on the verification structure at a plurality of test temperatures, acquiring actual measurement data, and completing low-temperature characteristic characterization of the verification structure; the method comprises the following steps: defining a sub-circuit based on a cryo-BSIM model architecture, and establishing a sub-circuit temperature dependent model driven by sub-box parameters; according to the low-temperature electrical characteristic parameters, through parameter fitting and discrete model integration, establishing a sub-circuit temperature continuous intensive model for low-temperature electrical characteristic simulation; when the consistency verification of the fitting result and the measured data fails, backtracking and adjusting the sub-box parameters, and completing the model iteration of the sub-circuit temperature dependent model; and when the consistency verification of the fitting result and the measured data is successful, obtaining the temperature continuous model of the low-temperature MOSFET. According to the invention, the electrical characteristics of the transistor in a full-temperature zone can be reflected more accurately.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a prediction method and model for the continuous temperature characteristics of a low-temperature MOSFET. Background Art

[0002] The MOSFET device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The performance of the MOSFET device can be significantly improved at low temperatures, such as enhancing the driving ability, reducing the subthreshold swing, and decreasing the leakage current. Therefore, it shows great potential in fields such as quantum computing, space exploration, and medical science. Especially in quantum computing, low-temperature MOSFET technology is crucial for realizing the control, amplification, and readout modules of quantum processors. The modules of low-temperature MOSFETs need to be closely adjacent to the quantum gate array to minimize thermal noise and communication delay.

[0003] Current Electronic Design Automation (EDA) tools do not support circuit simulation below -40°C, which greatly limits the application of low-temperature MOSFET technology in fields such as quantum computing. And the foundry only provides MOSFET models and parameters at room temperature, which cannot fully match the true operating characteristics of MOSFET devices at low temperatures. In EDA simulation, commercial models are limited to a narrow temperature range, restricting the accurate description of the electrical characteristics of MOSFETs in a low-temperature environment. Summary of the Invention

[0004] The purpose of the present invention is to provide a prediction method and model for the continuous temperature characteristics of a low-temperature MOSFET, which expands the temperature range of the DC temperature model of the MOSFET device and can more accurately reflect the electrical characteristics in the full temperature range from 4.2K to 398K, overcoming the defect of the discontinuous low-temperature BSIM DC temperature model of the original MOSFET device.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a prediction method for the continuous temperature characteristics of a low-temperature MOSFET, including the following steps:

[0007] Based on the process size range of the MOSFET, design and fabricate a verification structure covering all bins of the model;

[0008] Conduct DC characteristic tests on the verification structure at multiple test temperatures, collect the measured data, and complete the low-temperature characteristic characterization of the verification structure;

[0009] Based on the cryo-BSIM model architecture, define sub-circuits and establish a sub-circuit temperature-dependent model driven by binning parameters;

[0010] According to the low-temperature electrical characteristic parameters, through parameter fitting and discrete model integration, establish a sub-circuit temperature continuous intensive model for low-temperature electrical characteristic simulation;

[0011] When the consistency check between the fitting result and the measured data fails, backtrack and adjust the binning parameters, and complete the model iteration of the sub-circuit temperature-dependent model; and

[0012] When the consistency check between the fitting result and the measured data is successful, obtain the temperature continuous model of the low-temperature MOSFET.

[0013] In an embodiment of the present invention, in the step of designing a verification structure covering all bins of the model, set a plurality of the bins to cover the size range of the model parameter set and the size range of the mature process, wherein the types of device parameters in the bins include device channel length and device width, and the device parameters in the bins include the minimum value of the device channel length, the maximum value of the device channel length, the minimum value of the device width, and the maximum value of the device width.

[0014] In an embodiment of the present invention, in the step of designing a verification structure covering all bins of the model, the verification structure includes all critical dimensions provided by the process manufacturer and the cryo-BSIM parameter binning model.

[0015] In an embodiment of the present invention, the step of establishing the sub-circuit temperature-dependent model includes extracting binning parameters, and the step of extracting the binning parameters includes:

[0016] Obtain the original parameters of the boundary devices, where the boundary devices are the verification structures at the boundaries of each bin, and the original parameters are model parameters not related to the bin characteristics;

[0017] According to the actual channel length and actual channel width of the verification structure, interpolate to obtain the in-bin parameters of each bin, and the in-bin parameters within each bin are continuous;

[0018] Set the binning parameters in each bin, where the binning parameters in each bin are located between any two adjacent original parameters, and the binning parameters in two adjacent bins are continuous at the boundary.

[0019] In an embodiment of the present invention, the step of interpolating to obtain the in-bin parameters follows the following formula:

[0020]

[0021] Wherein, W is the channel width, L is the channel length, and P(L, W) i is the interpolation parameter at the channel length L and channel width W, and P i is the original parameter, is the parameter related to the channel length, is the parameter related to the channel width, is the parameter related to the product of the channel length and channel width.

[0022] In an embodiment of the present invention, the steps of establishing the sub-circuit temperature-dependent model at any of the test temperatures include:

[0023] Set multiple sub-circuit pch, where the nodes of the sub-circuit include the gate n1, source n2, drain n3, and substrate n4 of the MOSFET;

[0024] Set the geometric parameters, resistance parameters, device parameters, and process-related parameters of the sub-circuit, and preset the parameter variables;

[0025] Set the low-temperature electrical characteristic parameter sets of each model bin, where the parameters in the low-temperature electrical characteristic parameter sets include the low-temperature low-field mobility, the gate voltage coefficient of the low-temperature bulk charge effect, and the low-temperature saturated carrier velocity;

[0026] Obtain the low-temperature electrical characteristic parameters of the model bin at the test temperature, where the value of the binned low-temperature model parameters at a test temperature is based on the following formula:

[0027]

[0028] Wherein, A cryo is the low-temperature electrical characteristic parameter at a temperature, A0 cryo is the initial quantity and is taken from a preset fitting parameter set, AL cryo is the model parameter related to the device channel length and is taken from a preset fitting parameter set, AW cryo is the model parameter related to the device channel width and is taken from a preset fitting parameter set, AP cryo is the model parameter related to the product of the device channel length and device channel width and is taken from a preset fitting parameter set, L is the device channel length, and W is the device channel width.

[0029] In an embodiment of the present invention, the geometric parameters include the device channel width, device channel length, diffusion area of the drain and source, and diffusion perimeter of the drain and drain. The device parameters include the number of parallel devices and the number of finger gates. The resistance parameters include the diffusion resistance of the drain and source. The process-related parameters include the distance from the source to the gate, the distance from the source to the body terminal, the distance from the drain to the gate, and the process deviation parameter.

[0030] In an embodiment of the present invention, the prediction method includes, after establishing the sub-circuit temperature-dependent model, fitting the model parameters of all model bins at all the test temperatures, integrating the relationship between each model parameter and the test temperature into a temperature-continuous model parameter, and establishing a sub-circuit temperature-continuous intensive model;

[0031] In the sub-circuit temperature-continuous intensive model, the sub-circuit temperature model parameters of the model bins are based on the following formula:

[0032]

[0033] where T is the test temperature and T is the thermodynamic temperature, A cryo (T) is the low-temperature electrical performance parameter of the device at temperature T, A0 cryo (T) is a preset initial quantity at temperature T and is taken from a preset fitting parameter set, L is the device channel length, W is the device channel width, AL cryo (T) is a temperature-continuous model parameter related to the device channel length, AW cryo (T) is a temperature-continuous model parameter related to the device channel width and is taken from a preset fitting parameter set, AP cryo (T) is a temperature-continuous model parameter related to the product of the device channel length and the device channel width and is taken from a preset fitting parameter set.

[0034] In an embodiment of the present invention, in the consistency verification of the fitting result and the measured data, the electrical characteristic parameters for verification include the linear current, saturation current, linear threshold voltage, and saturation threshold voltage of the device.

[0035] The present invention provides a low-temperature MOSFET temperature-continuous model. Based on any one of the above-described prediction methods for the temperature-continuous characteristics of a low-temperature MOSFET, the temperature-continuous model has a cryo-BSIM model architecture as the underlying architecture, and the temperature-continuous model includes a sub-circuit temperature-dependent model and a sub-circuit temperature-continuous intensive model, wherein the sub-circuit temperature-continuous intensive model is constructed according to the low-temperature electrical characteristics of the device and the integration consistency of the fitting parameters and the discrete model.

[0036] As described above, the present invention provides a method for predicting the continuous temperature characteristics of a low-temperature MOSFET and its model. Based on the general and mature BSIM binning model of the manufacturing process, a cryo-BSIM sub-circuit temperature continuous intensive model for simulating low-temperature electrical characteristics is added, expanding the temperature range of the DC temperature model of the MOSFET device and being able to more accurately reflect the electrical characteristics in the full temperature range from 4.2K to 398K, overcoming the defect of the discontinuous low-temperature BSIM DC temperature model of the original MOSFET device. Moreover, the prediction method provided by the present invention can be extended to any binning parameters.

[0037] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0039] Figure 1 It is a schematic flowchart of a method for predicting the continuous temperature characteristics of a low-temperature MOSFET in an embodiment of the present invention.

[0040] Figure 2 It is a schematic diagram of model binning in an embodiment of the present invention.

[0041] Figure 3 It is a schematic flowchart of steps S110 to S130 in an embodiment of the present invention.

[0042] Figure 4 It is a schematic flowchart of steps S310 to S340 in an embodiment of the present invention.

[0043] Figure 5 It is a fitting curve graph of the correlation between the saturation current Idsat and temperature in an embodiment of the present invention.

[0044] Figure 6 It is a fitting curve graph of the correlation between the linear current Idlin and temperature in an embodiment of the present invention.

[0045] Figure 7 It is a fitting curve graph of the correlation between the threshold voltage and temperature when the drain-source voltage Vds is 1.8V and the body-source voltage Vbs is 0v in an embodiment of the present invention.

[0046] Figure 8This is a fitting curve graph of the threshold voltage and temperature correlation when the drain-source voltage Vds is 0.05V and the body-source voltage Vbs is 0V in an embodiment of the present invention. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] Please refer to Figure 1 As shown, the present invention provides a method for predicting the continuous temperature characteristics of a low-temperature MOSFET, including step S100 to step S500.

[0049] Step S100: Based on the process dimension range of the MOSFET, design and fabricate a verification structure covering all bins of the model.

[0050] Step S200: Conduct DC characteristic tests on the verification structure at multiple test temperatures, collect the measured data, and complete the characterization of the low-temperature characteristics of the verification structure.

[0051] Step S300: Based on the cryo-BSIM model architecture, define a sub-circuit, and establish a sub-circuit temperature-dependent model driven by bin parameters.

[0052] Step S400: According to the low-temperature electrical characteristic parameters, establish a sub-circuit temperature continuous intensive model for low-temperature electrical characteristic simulation through parameter fitting and discrete model integration.

[0053] Step S500: Verify the consistency between the fitting result and the measured data.

[0054] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, in step S100, multiple bins are set, and all the bins cover the dimension range of the model parameter set and the dimension range of the mature process. Thus, different model parameter sets can be provided for the scalable model according to the device dimensions. The scalable model is, for example, a MOSFET device. In this embodiment, the device parameter types in the bins include the device channel length and the device width, and the device parameters in the bins include the minimum device channel length LMIN, the maximum device channel length LMAX, the minimum device width WMIN, and the maximum device width WMAX. As Figure 2As shown, bins bin1 to bin16 are set according to the device channel length range and device channel width range of the MOSFET. Let L represent the device channel length of the MOSFET and W represent the device channel width of the MOSFET. For example, the device channel length of bin4 is from L1 to L2, and the device channel width is from W1 to W2. The device channel length and device channel width of each bin are different. And in the present invention, all the set bins can cover all the dimensional parameters that the model can cover. It should be noted that when performing simulation modeling, the simulation tools that can be used include HSPICE, Spectre, and ADS.

[0055] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, when setting bins, the dimensional range to be covered by the model bins is obtained according to the process dimensions and modeling dimensional parameters. Specifically, the process dimensions are the dimensions provided by the process manufacturer, and the process dimensions include all the critical dimensions provided by the process manufacturer. In this embodiment, the process is a common mature CMOS process, such as the 28nm process of TSMC and the 180nm process of TSMC. The specific dimensional range of the relevant process can be provided by the process manufacturer. Among them, the process is the modeling dimensional parameter, and the verification structure includes the cryo-BSIM parameter bin model. Correspondingly, the cryo-BSIM parameter bin model is also consistent with the process manufacturer of the corresponding process.

[0056] Please refer to Figure 2 As shown, it should be noted that during the chip manufacturing process, due to the complexity of the process, there will inevitably be some chips with slightly different performances. Through the binning strategy, these chips can be classified according to their performances, and the chips that meet different specification requirements can be screened out, thereby improving the overall yield and reducing the production cost. And it can also enable the manufacturer to provide chips with different performance levels according to the specific needs of customers, meet the diverse needs of the market, and improve the market competitiveness. In an embodiment of the present invention, in the binning strategy, the range of the input features is calculated by subtracting the minimum value from the maximum value, and then according to the preset binning criteria, the tested chips are classified to ensure that the chips are accurately assigned to the corresponding bins. In the present invention, multiple bins can be numbered, and each bin number is different to distinguish different bins and facilitate the calling of bins. For each data sample, according to the value of its input features, the data sample is divided into the corresponding bin. In this embodiment, a marking function can be used to achieve the division of the data sample. For example, for the binned channel length feature, define the function bin_label(L), where L is the channel length, and the function returns the bin number to which L belongs.

[0057] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, the steps of establishing a sub-circuit temperature-dependent model include extracting binning parameters, and the steps of extracting binning parameters include steps S110 to S130.

[0058] Step S110: Obtain the original parameters of the boundary devices, where the boundary devices are verification structures at each bin boundary, and the original parameters are model parameters not related to bin characteristics.

[0059] Step S120: Interpolate to obtain the in-bin parameters of each bin according to the actual channel length and actual channel width of the verification structure, and the in-bin parameters within each bin are continuous.

[0060] Step S130: Set the binning parameters in each bin, where the binning parameters in each bin are located between any two adjacent original parameters, and the binning parameters in two adjacent bins are continuous at the boundary.

[0061] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in step S110, the boundary devices are MOSFETs at the bin size boundary. For example, in bin1, the verification structure of the device channel length L5 is a boundary device, and the verification structure of the device channel width W1 is also a boundary device. And the original parameters are parameters not assigned to any bin. Taking D i to represent the device, taking P i to represent the original parameters, and taking P oi to represent the original model parameters. Among them, the original model parameters are parameters directly related to the physical characteristics and process conditions of the device, such as the geometric parameters of the device, the electrical parameters of the device, temperature parameters, process parameters of the manufacturing process, and parasitic parameters, etc. The geometric parameters of the device include device channel length, device channel width, diffusion area, and diffusion perimeter, etc. The electrical parameters of the device include threshold voltage, mobility, saturation current, and subthreshold swing, etc. Among them, the threshold voltage is the threshold voltage of the MOSFET. The mobility is the mobility of carriers in the channel. The saturation current is the current of the MOSFET in the saturation region. The subthreshold swing is used to describe the current change in the subthreshold region. Among them, P i is a constant model parameter, and has the same type of parameters as P oi .

[0062] Please refer to Figures 1 to 3 As shown, in step S120, the steps of interpolating to obtain the in-bin parameters follow Equation (1).

[0063]

[0064] In Equation (1), W is the channel width, L is the channel length, P(L, W) iis an interpolation parameter for channel length L and channel width W, P i is the original parameter, is a parameter related to the channel length, is a parameter related to the channel width, is a parameter related to the product of the channel length and the channel width.

[0065] Please refer to Figures 1 to 3 As shown, in step S130, in the binning, the binning parameter P i 、 takes the value of the original model parameter Poi or Poi + 1. This ensures that the parameter P is continuous at the boundary of two adjacent bins. After designing the binning, a MOSFET device for modeling verification is manufactured as a verification structure, where the size and type of the MOSFET device cover the preset full binning of the model.

[0066] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, in step S200, the DC characteristics of the verification structure are tested. At multiple test temperatures, measured data for modeling is obtained through low-temperature testing. Specifically, at different DC biases and different temperatures, based on the characteristic test circuit, the voltage data is adjusted to obtain the transfer characteristic curve, output characteristic curve, and substrate current curve of the MOSFET in each bin. In this embodiment, the DC electrical characterization data of the devices in each bin at each test temperature is obtained. Among them, the DC electrical characterization data includes the transfer characteristic curve, output characteristic curve, and substrate current curve of the MOSFET device. In this embodiment, the transfer characteristic curve is the IDS-VGS curve of the MOSFET device to represent the relationship between the drain current and the gate voltage of the MOSFET device. According to the voltage data and current data obtained from the DC characteristic test, the transfer characteristic curve of the MOSFET device is plotted. In this embodiment, the output characteristic curve is the IDS-VDS curve of the MOSFET device to represent the relationship between the drain current and the drain voltage of the MOSFET device. According to the voltage data and current data obtained from the DC characteristic test, the output characteristic curve of the MOSFET device is plotted. In this embodiment, the substrate current curve is the Isub-VGS curve of the MOSFET device to represent the relationship between the substrate current and the gate voltage of the MOSFET device. According to the voltage data and current data obtained from the DC characteristic test, the substrate current curve of the MOSFET device is plotted.

[0067] Please refer to Figure 1 and Figure 2 、 Figure 4As shown, in an embodiment of the present invention, in step S300, a sub-circuit temperature dependence model is established at any test temperature. Specifically, step S300 includes steps S310 to S340.

[0068] Step S310: Set the main circuit and multiple sub-circuits, where the nodes of the sub-circuit include the gate n1, source n2, drain n3, and substrate n4 of the MOSFET.

[0069] Step S320: Set the geometric parameters, resistance parameters, device parameters, and process-related parameters of the sub-circuit, and preset parameter variables.

[0070] Step S330: Set the low-temperature electrical characteristic parameter sets for each model bin, where the parameters in the low-temperature electrical characteristic parameter sets include low-temperature low-field mobility, gate voltage coefficient of low-temperature bulk charge effect, and low-temperature saturation carrier velocity.

[0071] Step S340: Obtain the low-temperature electrical characteristic parameters of the model bin at the test temperature.

[0072] Please refer to Figure 1 and Figure 2 、 Figure 4 As shown, in an embodiment of the present invention, in step S320, the method of defining a sub-circuit is illustrated by taking bin1 as an example. Specifically, the statement for defining a sub-circuit can be.subckt pch n1 n2 n3 n4 l=length w=width multi='1'nf='1'scale='1'sigma='1'. Among them,.subckt pch n1 n2 n3 n4 represents defining the sub-circuit gate n1, defining the sub-circuit source n2, defining the sub-circuit drain n3, and defining the sub-circuit substrate n4. Where pch represents the sub-circuit. length represents the device channel length, and the initial amount of the device channel length is l. width represents the device channel width, and the initial amount of the device channel width is w. multi='1' represents the number of parallel devices, and the initial amount of the parallel devices is, for example, 1. nf='1' represents the number of finger gates, and the initial amount of the finger gates is, for example, 1. scale='1' represents the scaling factor of the model, and the initial amount of the scaling factor is, for example, 1. sigma='1' represents the process deviation parameter, and the initial amount of the process deviation parameter is, for example, 1.

[0073] Please refer to Figure 1 and Figure 2 、 Figure 4As shown, in an embodiment of the present invention, in step S320, the geometric parameters of the sub-circuit include the device channel width, device channel length, diffusion region areas of the drain and source, and diffusion region perimeters of the drain and source. The device parameters of the sub-circuit include the number of parallel devices and the number of finger gates. The resistance parameters of the sub-circuit include the diffusion region resistances of the drain and source. The process-related parameters of the sub-circuit include the source-to-gate distance, source-to-body distance, drain-to-gate distance, and process deviation parameters. The statement defining the sub-circuit parameters can be main n1 n2 n3 n4 pch w=w l=l ad=ad as=as pd=pd ps=ps nrd=nrd nrs=nrs m=multi nf=nf sa=sa sb=sb sd=sd sca=sca scb=scb scc=scc. Among them, main n1 n2 n3 n4 pch represents defining the gate n1, source n2, drain n3, and substrate n4 of the sub-circuit. Among them, pch represents the sub-circuit. The device channel width is w, and the device channel length is l. ad is the diffusion region area of the drain, and as is the diffusion region area of the source. pd is the diffusion region perimeter of the drain, and ps is the diffusion region perimeter of the source. nrd represents the lateral diffusion resistance of the drain, and nrs represents the lateral diffusion resistance of the source. multi represents the number of parallel devices. nf represents the number of finger gates. The additional area of the source is sa, the additional area of the drain is sb, and the additional area of the substrate is sd. sca represents the additional perimeter of the source, scb represents the additional perimeter of the drain, and scc represents the additional perimeter of the substrate.

[0074] Please refer to Figure 1 and Figure 2 、 Figure 4 As shown, in an embodiment of the present invention, in step S330, taking bin1 as an example, the set of fitted low-temperature electrical characteristic parameters is, for example, {a1, a2, a3, a4}. Define the initial amount of the model parameters of the devices in the bin at a test temperature as A0_cryo_bin1, the model parameter related to the device channel length as AL_cryo_bin1, the model parameter related to the device channel width as AW_cryo_bin1, and the model parameter related to the product of the device channel length and device channel width as AP_cryo_bin1. The specific values of the model parameters in the bin can be taken from the set of low-temperature electrical characteristic parameters. For example, the value of A0_cryo_bin1 is a1, the value of AL_cryo_bin1 is a2, the value of AW_cryo_bin1 is a3, and the value of AP_cryo_bin1 is a4. And in this embodiment, in step S340, the values of the bin low-temperature model parameters at a test temperature are based on Equation (2).

[0075]

[0076] In formula (2), A cryo is a low-temperature electrical characteristic parameter at a test temperature, A0 cryo is the initial quantity and is taken from a preset set of fitting parameters, AL cryo is a model parameter related to the device channel length and is taken from a preset set of fitting parameters, AW cryo is a model parameter related to the device channel width and is taken from a preset set of fitting parameters, AP cryo is a model parameter related to the product of the device channel length and the device channel width and is taken from a preset set of fitting parameters, L is the device channel length, and W is the device channel width.

[0077] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, in step S400, the model parameters of all model bins at all test temperatures are fitted, the relationship between each model parameter and the test temperature is integrated into a model parameter that is continuous with respect to temperature, and a sub-circuit temperature continuous intensive model is established. In this embodiment, in the sub-circuit temperature continuous intensive model, the sub-circuit temperature model parameters of the model bins are based on formula (3).

[0078]

[0079] In formula (3), T is the test temperature and T is the thermodynamic temperature, where the unit of T is K, A cryo (T) is the low-temperature electrical performance parameter of the device at temperature T, A0 cryo (T) is the preset initial quantity at temperature T and is taken from a preset set of fitting parameters, L is the device channel length, W is the device channel width, AL cryo (T) is the temperature continuous model parameter related to the device channel length, AW cryo (T) is the temperature continuous model parameter related to the device channel width and is taken from a preset set of fitting parameters, AP cryo (T) is the temperature continuous model parameter related to the product of the device channel length and the device channel width and is taken from a preset set of fitting parameters. Through the sub-circuit temperature continuous intensive model, the electrical characteristic parameters of each bin at low temperature can be obtained.

[0080] Please refer to Figure 1 and Figure 2As shown in Equation (3), in an embodiment of the present invention, taking bin1 as an example, when the test temperature is T, the preset initial quantity A0_cryo_bin1_T of the devices in bin1 is '(a1 + a2*(temper + 273) + a3*pwr(temper + 273, 2)) + a4'. The temperature continuous model parameter AL_cryo_bin1_T related to the device channel length in bin1 is '(a5 + a6*(temper + 273) + a7*pwr(temper + 273, 3) + a8*pwr(temper + 273, 2 / 3)) + a9'. The temperature continuous model parameter AW_cryo_bin1_T related to the device channel width in bin1 is '(a10 + a11*(temper + 273) + a12*pwr(temper + 273, 2) + a13*pwr(temper + 273, a14)) + a15'. The temperature continuous model parameter AP_cryo_bin1_T related to the product of the device channel length and the device channel width in bin1 is '(a16 + a17*pwr(temper + 273, a18) + a19*pwr(temper + 273, 3) / (1 + a20*pwr(temper + 273, a21))) + a22'. In this embodiment, the fitting parameter set is {a1, a2, a3, a4 to a22}.

[0081] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, in step S500, in the consistency check of the fitting result and the measured data, the electrical characteristic parameters to be checked include the linear current, saturation current, linear threshold voltage, and saturation threshold voltage of the device. Among them, step S500 includes step S510 and step S520.

[0082] Step S510: When the consistency check of the fitting result and the measured data is successful, obtain the temperature continuous model of the low-temperature MOSFET.

[0083] Step S520: When the consistency check of the fitting result and the measured data fails, adjust the low-temperature electrical characteristic parameters of the model bin and re-obtain the sub-circuit temperature continuous intensive model.

[0084] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, in step S500, the saturation current Idsat is the value of the drain current Ids when the drain-source voltage Vds is equal to the power supply voltage Vdd, the gate-source voltage Vgs is equal to the power supply voltage Vdd, and the body-source voltage Vbs is 0V. The linear current Idlin is the value of the drain current Ids when the drain-source voltage Vds is 50mV, the gate-source voltage Vgs is equal to the power supply voltage Vdd, and the body-source voltage Vbs is 0V. The linear threshold voltage Vtlin is the value of the gate-source voltage Vgs when the drain current Ids is 100nA*(W / L) and the drain-source voltage Vds is 50mV. The saturation threshold voltage Vtsat is the value of the gate-source voltage Vgs when the drain current Ids is 100nA*(W / L) and the drain-source voltage Vds is the power supply voltage Vdd. Where W is the device channel width and L is the device channel length.

[0085] Please refer to Figure 1 and Figure 2 、 Figures 5 to 8 As shown, in an embodiment of the present invention, in step S500, taking the aspect ratio W / L = 20 / 15 in bin1 as an example, after completing the low-temperature MOSFET temperature continuous model modeling of cryo-BSIM, the comparison between the model curves and the measured data of four electrical characteristic parameters at different temperatures is shown. Figures 5 to 8 The abscissa in Figure 5 is the temperature T. Figure 6 The ordinate in Figure 7 is the saturation current Idsat. Figure 8 The ordinate in Figures 5 to 8 is the linear current Idlin.

[0086] The present invention provides a low-temperature MOSFET temperature continuous model. The temperature continuous model uses the cryo-BSIM model architecture as the underlying architecture, and the temperature continuous model includes a sub-circuit temperature dependence model and a sub-circuit temperature continuous intensive model. Among them, according to the low-temperature electrical characteristics of the device, as well as the integration consistency of fitting parameters and discrete models, the sub-circuit temperature continuous intensive model is constructed.

[0087] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for predicting the temperature continuity characteristics of a low-temperature MOSFET, characterized in that: The following steps are involved: Design and prepare a verification structure that covers all bins of the model based on the process size range of MOSFET; Performing a DC characteristic test on the verification structure at multiple test temperatures, collecting and obtaining measured data, and completing the low-temperature characteristic characterization of the verification structure; Based on the cryo-BSIM model architecture, subcircuits are defined and subcircuit temperature dependency models driven by binning parameters are established; According to the low-temperature electrical characteristic parameters, a sub-circuit temperature continuous intensive model for low-temperature electrical characteristic simulation is established through parameter fitting and discrete model integration; When the consistency check between the fitting result and the measured data fails, the binning parameters are adjusted retroactively, and the model iteration of the sub-circuit temperature dependence model is completed; and When the consistency check between the fitting result and the measured data is successful, the temperature continuity model of the low-temperature MOSFET is obtained.

2. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 1, characterized in that: In the step of designing a verification structure that covers all bins of the model, a plurality of bins are set to cover the size range of the model parameter set and the size range of the mature process, wherein the device parameter types in the bins include device channel length and device width, and the device parameters in the bins include a minimum device channel length, a maximum device channel length, a minimum device width, and a maximum device width.

3. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 2, characterized in that: In the step of designing a verification structure covering all binning of the model, the verification structure includes all critical dimensions and cryo-BSIM parameter binning models provided by the process manufacturer.

4. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 1, characterized in that: The step of establishing the sub-circuit temperature dependence model includes extracting bin parameters, wherein the step of extracting the bin parameters includes: Acquire original parameters of boundary devices, wherein the boundary devices are the verification structures at the boundaries of each bin, and the original parameters are model parameters that are irrelevant to bin characteristics; According to the actual channel length and the actual channel width of the verification structure, interpolation is performed to obtain the in-box parameters of each bin, and the in-box parameters in each bin are continuous; The binning parameters in each bin are set, wherein the binning parameters in each bin are located between any two adjacent original parameters, and the binning parameters in two adjacent bins are continuous at a boundary.

5. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 4, characterized in that: The step of interpolating to obtain the box parameters is in accordance with the following formula: Where W is the channel width, L is the channel length, P(L, W) i is the interpolation parameter under channel length L and channel width W, P i is the original parameter, is a parameter related to the channel length, is a parameter related to the channel width, It is a parameter related to the product of channel length and channel width.

6. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 1, characterized in that: The step of establishing the sub-circuit temperature dependence model at any of the test temperatures comprises: A plurality of sub-circuits pch are set, wherein nodes of the sub-circuits include a gate n1, a source n2, a drain n3 and a substrate n4 of a MOSFET; Set the geometric parameters, resistance parameters, device parameters and process-related parameters of the sub-circuit, and preset parameter variables; Setting a low-temperature electrical characteristic parameter set for each model sub-box, wherein the parameters in the low-temperature electrical characteristic parameter set include low-temperature low-field mobility, a gate voltage coefficient of a body charge effect at low temperature, and a low-temperature saturated carrier velocity; The low-temperature electrical characteristic parameters of the model bin at the test temperature are obtained, wherein the value of the bin low-temperature model parameter at the test temperature is based on the following formula: Among them, A cryo is the low temperature electrical characteristic parameter at a certain temperature, A0 cryo is the initial quantity and is taken from the preset fitting parameter set, AL cryo is a model parameter related to the device channel length and is taken from a preset fitting parameter set. cryo is a model parameter related to the device channel width and is taken from a preset fitting parameter set. cryo is a model parameter related to the product of the device channel length and the device channel width and is taken from a preset fitting parameter set, L is the device channel length, and W is the device channel width.

7. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 6, characterized in that: The geometric parameters include the device channel width, the device channel length, the diffusion area of ​​the drain and the source, and the perimeter of the diffusion area of ​​the drain and the drain; the device parameters include the number of parallel devices and the number of finger gates; the resistance parameters include the diffusion area resistance of the drain and the source; the process-related parameters include the distance from the source to the gate, the distance from the source to the body end, the distance from the drain to the gate, and the process deviation parameters.

8. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 1, characterized in that: The prediction method includes fitting the model parameters of all model bins at all the test temperatures after establishing the sub-circuit temperature dependence model, integrating the relationship between each model parameter and the test temperature into a model parameter about temperature continuity, and establishing a sub-circuit temperature continuity intensive model; In the sub-circuit temperature continuous intensive model, the sub-circuit temperature model parameters of the model bin are based on the following formula: Where T is the test temperature and T is the thermodynamic temperature, A cryo (T) is the low temperature electrical performance parameter of the device at temperature T, A0 cryo (T) is the preset initial value at temperature T and is taken from the preset fitting parameter set, L is the device channel length, W is the device channel width, AL cryo (T) is the temperature continuity model parameter related to the device channel length, AW cryo (T) is the temperature continuity model parameter related to the device channel width and is taken from the preset fitting parameter set, AP cryo (T) is a temperature continuity model parameter related to the product of the device channel length and the device channel width and is taken from a preset fitting parameter set.

9. The method for predicting the temperature continuity characteristics of a low-temperature MOSFET according to claim 1, characterized in that: In the consistency check between the fitting result and the measured data, the checked electrical characteristic parameters include the linear current, saturation current, linear threshold voltage and saturation threshold voltage of the device.

10. A low-temperature MOSFET temperature continuity model, based on a method for predicting the temperature continuity characteristics of a low-temperature MOSFET as claimed in any one of claims 1 to 9, characterized in that: The temperature continuity model uses the cryo-BSIM model architecture as its underlying architecture, and the temperature continuity model includes a sub-circuit temperature dependence model and a sub-circuit temperature continuity intensive model, wherein the sub-circuit temperature continuity intensive model is constructed based on the low-temperature electrical characteristics of the device and the integration consistency of the fitting parameters and the discrete model.

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