Gate driver and display panel

Abstract

According to the gate driver and the display panel, a second pull-up control circuit is arranged to be electrically connected with an (n-m) th-level first scanning signal input end, a second reference high level signal input end and a first node, and a pull-up circuit is electrically connected with the first node, the first reference high level signal input end and an nth-level second scanning signal output end; the pull-down circuit is electrically connected with a second node, a second reference low-level signal input end and an nth-stage second scanning signal output end, and the voltage of the second reference high-level signal input end is smaller than that of the first reference high-level signal input end; the voltage of the second reference high-level signal input end can flow to the pull-down circuit, so that the voltage input to the pull-down circuit is changed from the voltage input by the first reference high-level signal input end to the voltage input by the second reference high-level signal input end, and the voltage difference between the input end and the output end of the pull-down circuit is reduced. And the problem of short-circuit burn of the gate driver is improved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and particularly relates to a gate driver and a display panel. Background Art

[0002] The gate-driver on array (GOA) technology for an array substrate is to dispose a gate driver on the array substrate of a display panel to implement a driving technology for progressive scanning.

[0003] In order to implement the threshold voltage compensation function of the pixel circuit of a medium-sized OLED display panel, the gate-driving technology of the array substrate needs to output a wide pulse signal. Since both the pull-up circuit and the pull-down circuit of the gate driver are electrically connected to the scan signal output terminal, the transistor connected to the reference high-level signal input terminal in the pull-up circuit is directly electrically connected to the transistor connected to the reference low-level signal input terminal in the pull-down circuit. Therefore, during the output of the signal by the transistor in the pull-down circuit, the reference high-level signal input terminal and the reference low-level signal input terminal are turned on, resulting in a short-circuit burn phenomenon in the gate driver and dark lines appearing on the display panel. Summary of the Invention

[0004] Embodiments of the present application provide a gate driver and a display panel to improve the problem of dark lines appearing on the display panel.

[0005] In a first aspect, embodiments of the present application provide a gate driver, including cascaded shift registers at multiple levels. The nth-level shift register includes a first pull-up control circuit, a second pull-up control circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit;

[0006] The first pull-up control circuit is electrically connected to the first driving signal input terminal of the nth level, the first reference high-level signal input terminal, and the first node;

[0007] The second pull-up control circuit is electrically connected to the first scan signal input terminal of the (n - m)th level, the second reference high-level signal input terminal, and the first node;

[0008] The pull-up circuit is electrically connected to the first node, the first reference high-level signal input terminal, and the second scan signal output terminal of the nth level;

[0009] The pull-down circuit is electrically connected to the first scan signal input terminal of the (n - 1)th level, the first reference low-level signal input terminal, the first node, the second node, the second reference low-level signal input terminal, and the second scan signal output terminal of the nth level;

[0010] The pull-down control circuit is electrically connected to the (n-1)-th stage level transfer signal input terminal, the (n-1)-th stage first scan signal input terminal, the first reference high-level signal input terminal, and the second node;

[0011] Wherein, the voltage of the second reference high-level signal input terminal is less than the voltage of the first reference high-level signal input terminal.

[0012] Further, the second pull-up control circuit includes a first transistor. The control terminal of the first transistor is electrically connected to the (n-m)-th stage first scan signal input terminal. The first end of the first transistor is electrically connected to the second reference high-level signal input terminal. The second end of the first transistor is electrically connected to the first node;

[0013] The pull-up circuit includes a second transistor. The control terminal of the second transistor is electrically connected to the first node. The first end of the second transistor is electrically connected to the first reference high-level signal input terminal. The second end of the second transistor is electrically connected to the (n)-th stage second scan signal output terminal;

[0014] The pull-down circuit includes a third transistor. The control terminal of the third transistor is electrically connected to the second node. The first end of the third transistor is electrically connected to the second reference low-level signal input terminal. The second end of the third transistor is electrically connected to the (n)-th stage second scan signal output terminal.

[0015] Further, the pull-down circuit further includes a fourth transistor. The control terminal of the fourth transistor is electrically connected to the (n-1)-th stage first scan signal input terminal. The first end of the fourth transistor is electrically connected to the first reference low-level signal input terminal. The second end of the fourth transistor is electrically connected to the first node.

[0016] Further, the pull-down control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The control terminals of the fifth transistor and the sixth transistor are both electrically connected to the (n-1)-th stage level transfer signal input terminal. The first end of the fifth transistor is electrically connected to the (n-1)-th stage first scan signal input terminal. The second end of the fifth transistor is electrically connected to the first end of the sixth transistor. The second end of the sixth transistor is electrically connected to the third node. The control terminal of the seventh transistor is electrically connected to the third node. The first end of the seventh transistor is electrically connected to the first reference high-level signal input terminal. The second end of the seventh transistor is electrically connected to the second end of the fifth transistor. The control terminal of the eighth transistor is electrically connected to the third node. The first end of the eighth transistor is electrically connected to the first reference high-level signal input terminal. The second end of the eighth transistor is electrically connected to the second node.

[0017] Further, the first pull-up control circuit includes a ninth transistor and a tenth transistor. The control terminals of the ninth transistor and the tenth transistor are both electrically connected to the input terminal of the nth-stage first driving signal. The first terminal of the ninth transistor is electrically connected to the first reference high-level signal input terminal. The second terminal of the ninth transistor is electrically connected to the first terminal of the tenth transistor. The second terminal of the tenth transistor is electrically connected to the first node.

[0018] Further, the nth-stage shift register further includes an anti-leakage circuit. The anti-leakage circuit includes an eleventh transistor. The control terminal of the eleventh transistor is electrically connected to the first node. The first terminal of the eleventh transistor is electrically connected to the first reference high-level signal input terminal. The second terminal of the eleventh transistor is electrically connected to the fourth node.

[0019] The pull-down circuit further includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The control terminal of the twelfth transistor is electrically connected to the input terminal of the (n - 1)th-stage first scanning signal. The first terminal of the twelfth transistor is electrically connected to the first node. The second terminal of the twelfth transistor is electrically connected to the second terminal of the fourth transistor and is also electrically connected to the fourth node. The control terminals of the thirteenth transistor and the fourteenth transistor are both electrically connected to the second node. The first terminal of the thirteenth transistor is electrically connected to the first node. The second terminal of the thirteenth transistor is electrically connected to the first terminal of the fourteenth transistor and is also electrically connected to the fourth node. The second terminal of the fourteenth transistor is electrically connected to the first reference low-level signal input terminal.

[0020] Further, the pull-down circuit includes a fifteenth transistor and a sixteenth transistor. The control terminal of the fifteenth transistor is electrically connected to the input terminal of the nth-stage first driving signal. The first terminal of the fifteenth transistor is electrically connected to the first reference low-level signal input terminal. The second terminal of the fifteenth transistor is electrically connected to the second node. The control terminal of the sixteenth transistor is electrically connected to the first node. The first terminal of the sixteenth transistor is electrically connected to the first reference low-level signal input terminal. The second terminal of the sixteenth transistor is electrically connected to the second node.

[0021] Further, the nth-stage shift register further includes a first capacitor. The first terminal of the first capacitor is electrically connected to the control terminal of the second transistor. The second terminal of the first capacitor is electrically connected to the output terminal of the nth-stage second scanning signal.

[0022] Further, the pull-down control circuit further includes a second capacitor, a first end of the second capacitor is electrically connected to a control end of the eighth transistor, and a second end of the second capacitor is electrically connected to a first end of the eighth transistor.

[0023] In a second aspect, an embodiment of the present application provides a display panel, and the display panel includes the above-mentioned gate driver.

[0024] Advantages of the present application:

[0025] The present application provides a gate driver, which includes cascaded shift registers at multiple levels. The nth-level shift register includes a first pull-up control circuit, a second pull-up control circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit; the first pull-up control circuit is electrically connected to the first driving signal input terminal of the nth level, the first reference high-level signal input terminal, and a first node; the second pull-up control circuit is electrically connected to the first scanning signal input terminal of the (n - m)th level, the second reference high-level signal input terminal, and the first node; the pull-up circuit is electrically connected to the first node, the first reference high-level signal input terminal, and the second scanning signal output terminal of the nth level; the pull-down circuit is electrically connected to the first scanning signal input terminal of the (n - 1)th level, the first reference low-level signal input terminal, the first node, a second node, the second reference low-level signal input terminal, and the second scanning signal output terminal of the nth level; the pull-down control circuit is electrically connected to the stage transmission signal input terminal of the (n - 1)th level, the first scanning signal input terminal of the (n - 1)th level, the first reference high-level signal input terminal, and the second node; wherein, the voltage of the second reference high-level signal input terminal is less than the voltage of the first reference high-level signal input terminal. By setting the second pull-up control circuit to be electrically connected to the first scanning signal input terminal of the (n - m)th level, the second reference high-level signal input terminal, and the first node, the pull-up circuit to be electrically connected to the first node, the first reference high-level signal input terminal, and the second scanning signal output terminal of the nth level, the pull-down circuit to be electrically connected to the second node, the second reference low-level signal input terminal, and the second scanning signal output terminal of the nth level, and the voltage of the second reference high-level signal input terminal is less than the voltage of the first reference high-level signal input terminal, after the transistor in the pull-up circuit is turned on, the voltage of the second reference high-level signal input terminal can flow to the pull-down circuit, so that the voltage input to the pull-down circuit changes from the voltage input from the first reference high-level signal input terminal to the voltage input from the second reference high-level signal input terminal, reducing the pressure difference between the input end and the output end of the pull-down circuit. On the one hand, it can improve the problem of short-circuit burning of the gate driver, and on the other hand, it can enhance the compensation ability of the gate driver for the pixel circuit. Description of the Drawings

[0026] Figure 1It is a schematic diagram of the first structure of the gate driver in this application;

[0027] Figure 2 It is a schematic diagram of the second structure of the gate driver in this application;

[0028] Figure 3 It is a timing diagram of the gate driver in this application.

[0029] 100 - First pull-up control circuit; 200 - Second pull-up control circuit; 300 - Pull-up circuit; 400 - Pull-down circuit; 500 - Pull-down control circuit; 600 - Anti-leakage circuit. Detailed implementation manners

[0030] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings in the embodiments of this application. The technical solutions described below are only used to explain and illustrate the idea of this application, and should not be regarded as a limitation on the protection scope of this application.

[0031] In addition, terms such as "first", "second" and similar words do not represent any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0032] An embodiment of this application provides a display panel, including a gate driver. Refer to Figure 1 and Figure 3 , the gate driver includes cascaded shift registers. The nth shift register includes a first pull-up control circuit 100, a second pull-up control circuit 200, a pull-up circuit 300, a pull-down circuit 400 and a pull-down control circuit 500.

[0033] Specifically, the first pull-up control circuit 100 is electrically connected to the nth-stage first driving signal input terminal RD[n], the first reference high-level signal input terminal VGH1, and the first node Q; the second pull-up control circuit 200 is electrically connected to the (n - m)th-stage first scanning signal input terminal WR1[n - m], the second reference high-level signal input terminal VGH2, and the first node Q; the pull-up circuit 300 is electrically connected to the first node Q, the first reference high-level signal input terminal VGH1, and the nth-stage second scanning signal output terminal WR2[n]; the pull-down circuit 400 is electrically connected to the (n - 1)th-stage first scanning signal input terminal WR1[n - 1], the first reference low-level signal input terminal VGL1, the first node Q, the second node QB, the second reference low-level signal input terminal VGL2, and the nth-stage second scanning signal output terminal WR2[n]; the pull-down control circuit 500 is electrically connected to the (n - 1)th-stage stage transmission signal input terminal Cout[n - 1], the (n - 1)th-stage first scanning signal input terminal WR1[n - 1], the first reference high-level signal input terminal VGH1, and the second node QB; wherein, the voltage of the second reference high-level signal input terminal VGH2 is less than the voltage of the first reference high-level signal input terminal VGH1.

[0034] By setting the second pull-up control circuit 200 to be electrically connected to the (n - m)th-stage first scanning signal input terminal WR1[n - m], the second reference high-level signal input terminal VGH2, and the first node Q, the pull-up circuit 300 to be electrically connected to the first node Q, the first reference high-level signal input terminal VGH1, and the nth-stage second scanning signal output terminal WR2[n], the pull-down circuit 400 to be electrically connected to the second node QB, the second reference low-level signal input terminal VGL2, and the nth-stage second scanning signal output terminal WR2[n], and the voltage of the second reference high-level signal input terminal VGH2 to be less than the voltage of the first reference high-level signal input terminal VGH1, after the transistor of the pull-up circuit 300 is turned on, the voltage of the second reference high-level signal input terminal VGH2 can flow to the pull-down circuit 400, so that the voltage input to the pull-down circuit 400 changes from the voltage input from the first reference high-level signal input terminal VGH1 to the voltage input from the second reference high-level signal input terminal VGH2, reducing the pressure difference between the input end and the output end of the pull-down circuit 400. On the one hand, it can improve the problem of short-circuit burning of the gate driver, and on the other hand, it can also enhance the compensation ability of the gate driver for the pixel circuit.

[0035] In this embodiment, the second pull-up control circuit 200 includes a first transistor T1. The control terminal of the first transistor T1 is electrically connected to the (n - m)-th first scan signal input terminal WR1[n - m]. The first terminal of the first transistor T1 is electrically connected to the second reference high-level signal input terminal VGH2. The second terminal of the first transistor T1 is electrically connected to the first node Q. The pull-up circuit 300 includes a second transistor T2. The control terminal of the second transistor T2 is electrically connected to the first node Q. The first terminal of the second transistor T2 is electrically connected to the first reference high-level signal input terminal VGH1. The second terminal of the second transistor T2 is electrically connected to the n-th second scan signal output terminal WR2[n]. The pull-down circuit 400 includes a third transistor T3. The control terminal of the third transistor T3 is electrically connected to the second node QB. The first terminal of the third transistor T3 is electrically connected to the second reference low-level signal input terminal VGL2. The second terminal of the third transistor T3 is electrically connected to the n-th second scan signal output terminal WR2[n].

[0036] When the shift register is operating, a high level is input to the (n - m)-th first scan signal input terminal WR1[n - m], the first transistor T1 is turned on, and a high-level signal is input to the second reference high-level signal input terminal VGH2, pulling up the first node Q to a high level, enabling the second transistor T2 to be turned on. Thus, the voltage of the n-th scan signal output terminal WR2[n] is VGH2 - Vth.

[0037] Therefore, when the third transistor T3 is turned on, the voltage difference of the third transistor T3 changes from VGH1 - Vth - VGL2 to VGH2 - Vth - VGL2, thereby improving the problem of short-circuit burning of the gate driver.

[0038] It should be noted that when the shift register is operating, high levels are input to both the n-th first drive signal input terminal RD[n] and the (n - m)-th first scan signal input terminal WR1[n - m], and low levels are input to both the (n - 1)-th stage transfer signal input terminal Cout[n - 1] and the (n - 1)-th first scan signal input terminal WR1[n - 1]. Among them, a high level is first input to the n-th first drive signal input terminal RD[n], then a high level is input to the (n - m)-th first scan signal input terminal WR1[n - m], and finally high levels are input to both the (n - 1)-th first scan signal input terminal WR1[n - 1] and the (n - 1)-th stage transfer signal input terminal Cout[n - 1].

[0039] In this embodiment, the pull-down circuit 400 further includes a fourth transistor T4. The control terminal of the fourth transistor T4 is electrically connected to the (n - 1)-th first scan signal input terminal WR1[n - 1]. The first terminal of the fourth transistor T4 is electrically connected to the first reference low-level signal input terminal VGL1. The second terminal of the fourth transistor T4 is electrically connected to the first node Q.

[0040] When the shift register is operating, a high level is input to the first scan signal input terminal WR1[n-1] of the (n-1)th stage, the fourth transistor T4 is turned on, and thus the first reference low level signal input terminal VGL1 pulls down the potential of the first node Q to a low level.

[0041] In this embodiment, the pull-down control circuit 500 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The control terminals of the fifth transistor T5 and the sixth transistor T6 are both electrically connected to the stage transmission signal input terminal Cout[n-1] of the (n-1)th stage. The first end of the fifth transistor T5 is electrically connected to the first scan signal input terminal WR1[n-1] of the (n-1)th stage. The second end of the fifth transistor T5 is electrically connected to the first end of the sixth transistor T6. The second end of the sixth transistor T6 is electrically connected to the third node T. The control terminal of the seventh transistor T7 is electrically connected to the third node T. The first end of the seventh transistor T7 is electrically connected to the first reference high level signal input terminal VGH1. The second end of the seventh transistor T7 is electrically connected to the second end of the fifth transistor T5. The control terminal of the eighth transistor T8 is electrically connected to the third node T. The first end of the eighth transistor T8 is electrically connected to the first reference high level signal input terminal VGH1. The second end of the eighth transistor T8 is electrically connected to the second node QB.

[0042] When the shift register is operating, high levels are input to both the first scan signal input terminal WR1[n-1] and the stage transmission signal input terminal Cout[n-1] of the (n-1)th stage. As a result, the fifth transistor T5 and the sixth transistor T6 are turned on, and the potential of the third node T is pulled up to a high level by the stage transmission signal input terminal Cout[n-1] of the (n-1)th stage. Thus, the eighth transistor T8 is turned on, and the first reference high level signal input terminal VGH1 pulls up the potential of the second node QB to a high level. As a result, the third transistor T3 is turned on, and the second reference low level signal input terminal VGL2 pulls down the potential of the second scan signal output terminal WR2[n] of the nth stage to a low level.

[0043] In this embodiment, the first pull-up control circuit 100 includes a ninth transistor T9 and a tenth transistor T10. The control terminals of the ninth transistor T9 and the tenth transistor T10 are both electrically connected to the first drive signal input terminal RD[n] of the nth stage. The first end of the ninth transistor T9 is electrically connected to the first reference high level signal input terminal VGH1. The second end of the ninth transistor T9 is electrically connected to the first end of the tenth transistor T10. The second end of the tenth transistor T10 is electrically connected to the first node Q.

[0044] When the shift register is operating, a high level is input to the first drive signal input terminal RD[n] of the nth stage, the ninth transistor T9 and the tenth transistor T10 are turned on, and the potential of the first node Q is pulled up to a high level by the first reference high level signal input terminal VGH1.

[0045] Reference Figure 2 In this embodiment, the nth-stage shift register further includes an anti-leakage circuit 600. The anti-leakage circuit 600 includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is electrically connected to the first node Q. The first terminal of the eleventh transistor T11 is electrically connected to the first reference high-level signal input terminal VGH1. The second terminal of the eleventh transistor T11 is electrically connected to the fourth node N[n].

[0046] The pull-down circuit 400 further includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminal of the twelfth transistor T12 is electrically connected to the (n-1)th-stage first scan signal input terminal WR1[n-1]. The first terminal of the twelfth transistor T12 is electrically connected to the first node Q. The second terminal of the twelfth transistor T12 is electrically connected to the second terminal of the fourth transistor T4, and the second terminal of the twelfth transistor T12 is also electrically connected to the fourth node N[n]. The control terminals of the thirteenth transistor T13 and the fourteenth transistor T14 are both electrically connected to the second node QB. The first terminal of the thirteenth transistor T13 is electrically connected to the first node Q. The second terminal of the thirteenth transistor T13 is electrically connected to the first terminal of the fourteenth transistor T14, and the second terminal of the thirteenth transistor T13 is also electrically connected to the fourth node N[n]. The second terminal of the fourteenth transistor T14 is electrically connected to the first reference low-level signal input terminal VGL1.

[0047] When the shift register is operating, the first node Q is pulled to a high level, the eleventh transistor T11 is turned on, and the fourth node N[n] is pulled to a high level. Since the second terminals of the twelfth transistor T12 and the thirteenth transistor T13 are electrically connected to the fourth node N[n] at this time, the second terminals of the twelfth transistor T12 and the thirteenth transistor T13 are pulled to a high level, thereby preventing leakage of the first node Q.

[0048] In this embodiment, the pull-down circuit 400 further includes a fifteenth transistor T15 and a sixteenth transistor T16. The control terminal of the fifteenth transistor T15 is electrically connected to the nth-stage first drive signal input terminal RD[n]. The first terminal of the fifteenth transistor T15 is electrically connected to the first reference low-level signal input terminal VGL1. The second terminal of the fifteenth transistor T15 is electrically connected to the second node QB. The control terminal of the sixteenth transistor T16 is electrically connected to the first node Q. The first terminal of the sixteenth transistor T16 is electrically connected to the first reference low-level signal input terminal VGL1. The second terminal of the sixteenth transistor T16 is electrically connected to the second node QB.

[0049] When the shift register is operating, a high level is input to the first driving signal input terminal RD[n] of the nth stage, and the fifteenth transistor T15 is turned on. As a result, the second node QB is pulled low by the first reference low-level signal input terminal VGL1, that is, the second node QB maintains a level continuously during the wide pulse stage. At the same time, since the first node Q is at a high level, the sixteenth transistor T16 is turned on, and the second node QB can also be pulled low by the first reference low-level signal input terminal VGL1 under the action of the sixteenth transistor T16. At the same time, when a high level is input to the first driving signal input terminal RD[n] of the nth stage and the first scanning signal input terminal WR1[n - m] of the (n - m)th stage, the high level input to the first driving signal input terminal RD[n] of the nth stage stops before the first scanning signal input terminal WR1[n - m] of the (n - m)th stage. Therefore, setting the sixteenth transistor T16 can also ensure that when a high level is input to the first scanning signal input terminal WR1[n - m] of the (n - m)th stage, the second node QB can be pulled low by the first reference low-level signal input terminal VGL1.

[0050] In this embodiment, the nth-stage shift register further includes a first capacitor C1. The first end of the first capacitor C1 is electrically connected to the control terminal of the second transistor T2, and the second end of the first capacitor C1 is electrically connected to the second scanning signal output terminal WR2[n] of the nth stage. By setting the first end of the first capacitor C1 to be electrically connected to the control terminal of the second transistor T2 and the second end of the first capacitor C1 to be electrically connected to the second scanning signal output terminal WR2[n] of the nth stage, the signal transmitted by the pull-up circuit 300 to the second scanning signal output terminal WR2[n] of the nth stage can be made more stable.

[0051] In this embodiment, the pull-down control circuit 500 further includes a second capacitor C2. The first end of the second capacitor C2 is electrically connected to the control terminal of the eighth transistor T8, and the second end of the second capacitor C2 is electrically connected to the first end of the eighth transistor T8. By setting the second capacitor C2, during the process of the fifth transistor T5 and the sixth transistor T6 turning from on to off, the first reference high-level signal input terminal VGH1 enables the eighth transistor T8 to still remain on for a certain period of time, and then the control terminal of the eighth transistor T8 can still maintain a high level for a certain period of time, so that the second node QB still remains at a high potential. At the same time, under the coupling action of the second capacitor C2, the second node QB can be made to maintain a high potential. Thus, the second node QB can maintain a high level, and further the second scanning signal output terminal WR2[n] of the nth stage can be maintained at a low level, avoiding the shift register from failing due to instability.

[0052] The specific working process of the shift register includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4, where:

[0053] In the first stage t1, the first driving signal input terminal RD[n] of the nth stage is at a high level, the ninth transistor T9 and the tenth transistor T10 are turned on, causing the first node Q to rise to a high level. At this time, the potential of the first node Q is VGH1. At this time, the voltage of the second scanning signal output terminal WR2[n] of the nth stage is VGH1 - Vth, where Vth is the threshold voltage of the second transistor T2. At the same time, the fifteenth transistor T15 is turned on, and the first reference low-level signal input terminal VGL1 pulls down the potential of the second node QB to a low level. At the same time, since the first scanning signal input terminal WR1[n - 1] of the (n - 1)th stage inputs a low-level signal, the fourth transistor T4 and the twelfth transistor T12 are not conducting, so the pull-down circuit does not work; and because the first scanning signal input terminal WR1[n - 1] of the (n - 1)th stage inputs a low-level signal, the fourth node N[n] is at a low level, so the pull-down maintenance circuit does not work either. The first reference low-level signal input terminal VGL1 pulls down the potential of the second node QB to a low level, and the third transistor T3 is not conducting.

[0054] In the second stage t2, the second transistor T2 is turned on, and the pull-up circuit 300 controls the second scanning signal output terminal WR2[n] of the nth stage to output a signal, so that the scanning line corresponding to the nth stage shift register is charged, turning on a row of pixels corresponding to the scanning line of the nth stage, and the pixels of this row are lit.

[0055] In the third stage t3, the first scanning signal input terminal WR1[n - m] of the (n - m)th stage is at a high level, the first transistor T1 is turned on, and the first node Q drops to VGH2. At this time, the voltage of the second scanning signal output terminal WR2[n] of the nth stage is VGH2 - Vth, where Vth is the threshold voltage of the second transistor T2. At the same time, the sixteenth transistor T16 is turned on, and the first reference low-level signal input terminal VGL1 pulls down the potential of the second node QB to a low level, and the third transistor T3 is not conducting.

[0056] In the fourth stage t4, both the first scanning signal input terminal WR1[n - 1] and the stage transmission signal input terminal Cout[n - 1] of the (n - 1)th stage input high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, the potential of the third node T is pulled up, the eighth transistor T8 is turned on, causing the second node QB to be pulled up, and the third transistor T3 is turned on, so that the second scanning signal output terminal WR2[n] of the nth stage is pulled to a low level by the second reference low-level signal input terminal VGL2.

[0057] The above describes the embodiments of the present application. The above description is only used to help understand the method and its core idea of the present application. The content of this specification should not be construed as a limitation on the protection scope of the present application.

Claims

1. A gate driver, characterized in that, It includes a shift register with multiple levels of cascading. The nth-level shift register includes a first pull-up control circuit (100), a second pull-up control circuit (200), a pull-up circuit (300), a pull-down circuit (400), and a pull-down control circuit (500); The first pull-up control circuit (100) is electrically connected to the nth-level first driving signal input terminal (RD[n]), the first reference high-level signal input terminal (VGH1), and the first node (Q); The second pull-up control circuit (200) is electrically connected to the (n - m)th-level first scanning signal input terminal (WR1[n - m]), the second reference high-level signal input terminal (VGH2), and the first node (Q); The pull-up circuit (300) is electrically connected to the first node (Q), the first reference high-level signal input terminal (VGH1), and the nth-level second scanning signal output terminal (WR2[n]); The pull-down circuit (400) is electrically connected to the (n - 1)th-level first scanning signal input terminal (WR1[n - 1]), the first reference low-level signal input terminal (VGL1), the first node (Q), the second node (QB), the second reference low-level signal input terminal (VGL2), and the nth-level second scanning signal output terminal (WR2[n]); The pull-down control circuit (500) is electrically connected to the (n - 1)th-level cascading signal input terminal (Cout[n - 1]), the (n - 1)th-level first scanning signal input terminal (WR1[n - 1]), the first reference high-level signal input terminal (VGH1), and the second node (QB); Wherein, the voltage of the second reference high-level signal input terminal (VGH2) is less than the voltage of the first reference high-level signal input terminal (VGH1).

2. The gate driver according to claim 1, characterized in that, The second pull-up control circuit (200) includes a first transistor (T1). The control end of the first transistor (T1) is electrically connected to the (n - m)th-level first scanning signal input terminal (WR1[n - m]). The first end of the first transistor (T1) is electrically connected to the second reference high-level signal input terminal (VGH2). The second end of the first transistor (T1) is electrically connected to the first node (Q); The pull-up circuit (300) includes a second transistor (T2). The control end of the second transistor (T2) is electrically connected to the first node (Q). The first end of the second transistor (T2) is electrically connected to the first reference high-level signal input terminal (VGH1). The second end of the second transistor (T2) is electrically connected to the nth-level second scanning signal output terminal (WR2[n]); The pull-down circuit (400) includes a third transistor (T3). The control end of the third transistor (T3) is electrically connected to the second node (QB). The first end of the third transistor (T3) is electrically connected to the second reference low-level signal input terminal (VGL2). The second end of the third transistor (T3) is electrically connected to the nth-level second scanning signal output terminal (WR2[n]).

3. The gate driver according to claim 2, characterized in that, The pull-down circuit (400) further includes a fourth transistor (T4). The control terminal of the fourth transistor (T4) is electrically connected to the (n-1)th stage first scan signal input terminal (WR1[n-1]). The first terminal of the fourth transistor (T4) is electrically connected to the first reference low-level signal input terminal (VGL1). The second terminal of the fourth transistor (T4) is electrically connected to the first node (Q).

4. The gate driver according to claim 3, characterized in that, The pull-down control circuit (500) includes a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8). The control terminals of the fifth transistor (T5) and the sixth transistor (T6) are both electrically connected to the (n-1)th stage stage transfer signal input terminal (Cout[n-1]). The first terminal of the fifth transistor (T5) is electrically connected to the (n-1)th stage first scan signal input terminal (WR1[n-1]). The second terminal of the fifth transistor (T5) is electrically connected to the first terminal of the sixth transistor (T6). The second terminal of the sixth transistor (T6) is electrically connected to the third node (T). The control terminal of the seventh transistor (T7) is electrically connected to the third node (T). The first terminal of the seventh transistor (T7) is electrically connected to the first reference high-level signal input terminal (VGH1). The second terminal of the seventh transistor (T7) is electrically connected to the second terminal of the fifth transistor (T5). The control terminal of the eighth transistor (T8) is electrically connected to the third node (T). The first terminal of the eighth transistor (T8) is electrically connected to the first reference high-level signal input terminal (VGH1). The second terminal of the eighth transistor (T8) is electrically connected to the second node (QB).

5. The gate driver according to claim 1, characterized in that, The first pull-up control circuit (100) includes a ninth transistor (T9) and a tenth transistor (T10). The control terminals of the ninth transistor (T9) and the tenth transistor (T10) are both electrically connected to the nth stage first drive signal input terminal (RD[n]). The first terminal of the ninth transistor (T9) is electrically connected to the first reference high-level signal input terminal (VGH1). The second terminal of the ninth transistor (T9) is electrically connected to the first terminal of the tenth transistor (T10). The second terminal of the tenth transistor (T10) is electrically connected to the first node (Q).

6. The gate driver according to claim 3, characterized in that, The nth stage shift register further includes an anti-leakage circuit (600). The anti-leakage circuit (600) includes an eleventh transistor (T11). The control terminal of the eleventh transistor (T11) is electrically connected to the first node (Q). The first terminal of the eleventh transistor (T11) is electrically connected to the first reference high-level signal input terminal (VGH1). The second terminal of the eleventh transistor (T11) is electrically connected to the fourth node (N[n]); The pull-down circuit (400) further includes a twelfth transistor (T12), a thirteenth transistor (T13), and a fourteenth transistor (T14). The control terminal of the twelfth transistor (T12) is electrically connected to the (n-1)-th stage first scan signal input terminal (WR1[n-1]). The first terminal of the twelfth transistor (T12) is electrically connected to the first node (Q). The second terminal of the twelfth transistor (T12) is electrically connected to the second terminal of the fourth transistor (T4), and the second terminal of the twelfth transistor (T12) is electrically connected to the fourth node (N[n]). The control terminals of the thirteenth transistor (T13) and the fourteenth transistor (T14) are both electrically connected to the second node (QB). The first terminal of the thirteenth transistor (T13) is electrically connected to the first node (Q). The second terminal of the thirteenth transistor (T13) is electrically connected to the first terminal of the fourteenth transistor (T14), and the second terminal of the thirteenth transistor (T13) is electrically connected to the fourth node (N[n]). The second terminal of the fourteenth transistor (T14) is electrically connected to the first reference low-level signal input terminal (VGL1).

7. The gate driver according to claim 3, characterized in that, The pull-down circuit (400) further includes a fifteenth transistor (T15) and a sixteenth transistor (T16). The control terminal of the fifteenth transistor (T15) is electrically connected to the n-th stage first drive signal input terminal (RD[n]). The first terminal of the fifteenth transistor (T15) is electrically connected to the first reference low-level signal input terminal (VGL1). The second terminal of the fifteenth transistor (T15) is electrically connected to the second node (QB). The control terminal of the sixteenth transistor (T16) is electrically connected to the first node (Q). The first terminal of the sixteenth transistor (T16) is electrically connected to the first reference low-level signal input terminal (VGL1). The second terminal of the sixteenth transistor (T16) is electrically connected to the second node (QB).

8. The gate driver according to claim 2, characterized in that, The n-th stage shift register further includes a first capacitor (C1). The first terminal of the first capacitor (C1) is electrically connected to the control terminal of the second transistor (T2). The second terminal of the first capacitor (C1) is electrically connected to the n-th stage second scan signal output terminal (WR2[n]).

9. The gate driver according to claim 4, characterized in that, The pull-down control circuit (500) further includes a second capacitor (C2). The first terminal of the second capacitor (C2) is electrically connected to the control terminal of the eighth transistor (T8). The second terminal of the second capacitor (C2) is electrically connected to the first terminal of the eighth transistor (T8).

10. A display panel, characterized in that, The display panel includes the gate driver according to any one of claims 1-9.

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