PWM controller of high-speed low-power-consumption current mode

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a circuit of a PWM controller of a high-speed low-power-consumption current mode. The PWM controller circuit comprises a reference circuit, an error amplifier, a current mode comparator, a clock circuit, a protection circuit and a digital logic circuit module. And the control on the duty ratio is realized by detecting the external current, so that the control on the output power is realized, and the control on the output voltage is finally realized. According to the invention, the voltage in an application input range can be controlled to be 4-20V, the quiescent current is 30uA, and the working frequency is 1.5 MHz.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, especially the power management chip circuit. Background Art

[0002] Power supply, as a core component of electronic devices, its performance plays a decisive role in the overall device performance. Currently, the development trend of power management chips is towards high integration, high efficiency and enhanced portability. In this context, significant progress has been made in reducing the volume, power consumption and improving the integration level of power management chips. DCDC power management chips occupy an important position in the market due to their excellent power conversion efficiency. Compared with traditional LDO management chips, the efficiency of DCDC power management chips can be as high as over 90%, which benefits from the internal switching power supply operating in a high-frequency switching state, resulting in extremely low self-power consumption. Therefore, DCDC power management chips are widely used in various electronic devices, such as portable devices like smartphones, tablets, laptops, as well as large devices like data centers and servers. With the rapid development of the electronics industry and the continuous expansion of the market scale, the demand for power management chips is also increasing year by year. This provides a broad market space and development opportunities for the research and development and production of power management chips. In addition, as the core part of DCDC power management chips, DCDC converters can be divided into different types according to the number of active power devices. Among them, single-switch converters include active forward, flyback and Cuk converters; dual-switch converters cover dual-switch forward, dual-switch flyback, push-pull and half-bridge. These different types of converters provide diverse choices for the design of DCDC power management chips, enabling them to meet the requirements of different application scenarios. Summary of the Invention

[0003] In order to overcome the deficiencies of the prior art, the present invention provides a high-speed and low-power current-mode PWM controller amplifier circuit.

[0004] The present invention is achieved through the following solutions:

[0005] 1. A circuit of a high-speed and low-power current-mode PWM controller, characterized in that the circuit includes a reference circuit, a bandgap reference circuit, a soft-start circuit, an error amplifier circuit, a comparison circuit, a clock circuit, a pre-regulator circuit, a linear regulator circuit, an under-voltage protection circuit, an over-current protection circuit, a protection circuit, and a drive circuit.

[0006] 2. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the bandgap reference circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PNP transistor Q1, a second PNP transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a first amplifier M1, a second amplifier M2, a first comparator T1, a first inverter I1, and a second inverter I2.

[0007] The source of the first NMOS transistor N1 in the bandgap reference module is grounded and connected to the source of the second NMOS transistor N2, the collector and base of the first PNP transistor Q1, the base and collector of the second PNP transistor Q2, one end of the sixth resistor, and the source of the third NMOS transistor N3. The drain is connected to the drain, gate of the fourth PMOS transistor P4, and the gate of the second NMOS transistor N2. The source of the fourth NMOS transistor N4 is connected to the drain and gate of the third PMOS transistor P3. The source of the third PMOS transistor is connected to the drain and gate of the second PMOS transistor. The source of the second PMOS transistor P2 is connected to the gate and drain of the first PMOS transistor P1. The source of the first PMOS transistor P1 is connected to the sources of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9. The gate of the fifth PMOS transistor P5 is connected to the gates of the sixth PMOS transistor, the drain of the second NMOS transistor N2, the output of the first amplifier M1, and the gate of the seventh PMOS transistor. The drain of the fifth PMOS transistor P5 is connected to one end of the first resistor R1, and the other end is connected to the collector of the first PNP transistor P1 and the positive terminal of the amplifier. The drain of the sixth PMOS transistor P6 is connected to the second resistor R2, the positive terminal of the first comparator T1, and the negative terminal of the second amplifier M2. The other end of the second resistor R2 is connected in series with the third resistor R3 and the fourth resistor R4. The end of the fourth resistor R4 is connected to the collector of the second PNP transistor Q2. The drain of the eighth PMOS transistor P8 is connected in series with the fifth resistor R5 and the sixth resistor R6. One end of the sixth resistor is connected to the drain of the third NMOS transistor. The output of the first comparator T1 is connected to the input of the first inverter I1. The output of the first inverter I1 is connected to the input of the second inverter and the gate of the third NMOS transistor N3. The output of the second amplifier M2, the positive segment of the second amplifier M2, and the first capacitor C1 are connected. The other end of the first capacitor C1 is connected to ground.

[0008] 3. The high-speed and low-power current-mode PWM controller as claimed in claim 1, wherein the soft-start circuit comprises: a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second capacitor C2, a second comparator T2, and a first converter A1.

[0009] The source terminal of the fourth NMOS transistor N4, the drain terminal of the fifth NMOS transistor N5, one end of the second capacitor C2, the ground terminal of the second comparator T2, and the ground terminal of the first selector are connected. The gate and drain of the fourth NMOS transistor N4 are connected to the gate of the fifth NMOS transistor N5. The drain terminal of the fifth NMOS transistor N5 is connected to the drain terminal, gate terminal of the tenth PMOS transistor P10, the gate terminal of the eleventh PMOS transistor P11, the gate terminal of the twelfth PMOS transistor P12, and the gate terminal of the thirteenth PMOS transistor P13. The source of the eleventh PMOS transistor is connected to the source of the tenth PMOS transistor P10, the power supply terminal of the second comparator, and the power supply terminal of the first selector A1. One end of the second capacitor C2 is connected to the positive terminal of the second comparator T2 and the 0 terminal of the first selector A1, and the negative terminal of the second comparator T2 is connected to the 1 terminal of the first selector A1.

[0010] 4. The high-speed and low-power current-mode PWM controller as claimed in claim 1, wherein the error amplifier circuit comprises: a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, and a thirteenth NMOS transistor N13.

[0011] The source of the sixth NMOS transistor N6 of the error amplifier circuit described above is connected to the sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, and the thirteenth NMOS transistor N13, and is connected to ground. The gate and drain of the sixth NMOS transistor N6 are connected to the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor N7 is connected to the drain of the fourteenth PMOS transistor P14, the gate of the fourteenth PMOS transistor P14, and the gate of the sixteenth PMOS transistor. The source of the fourteenth PMOS transistor P14 is connected to the sources of the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, and the nineteenth PMOS transistor P19. The drain of the sixteenth PMOS transistor P16 is connected to the sources of the seventeenth PMOS transistor P17 and the eighteenth PMOS transistor P18. The drain of the seventeenth NMOS transistor N17 is connected to the gate of the eighth NMOS transistor N8, the drain and gate of the ninth NMOS transistor N9, the gate of the tenth NMOS transistor N10, and the drain of the eleventh NMOS transistor. The drain of the eighteenth PMOS transistor P18 is connected to the drain of the tenth NMOS transistor N10, the drain and gate of the twelfth NMOS transistor N12, the gate of the eleventh NMOS transistor N11, and the gate of the thirteenth NMOS transistor N13. The gate of the fifteenth PMOS transistor P15 is connected to the gate of the nineteenth PMOS transistor P19. The drain of the fifteenth PMOS transistor P15 is connected to the drain of the eighth PMOS transistor P8. The drain of the nineteenth PMOS transistor P19 is connected to the drain of the thirteenth NMOS transistor N13.

[0012] 5. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the comparison circuit includes a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, a twenty-third PMOS transistor P23, a twenty-fourth PMOS transistor P24, and a twenty-fifth PMOS transistor P25. A fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, and a twenty-second NMOS transistor N22. A third inverter I3 and a fourth inverter I4.

[0013] The source of the fourteenth NMOS transistor N14 in the error amplifier circuit is connected to the sources of the fifteenth NMOS transistor N15, the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N17, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, and the twenty-first NMOS transistor N21, and is grounded. The gate and drain of the fourteenth NMOS transistor N14 are connected to the gate of the fifteenth NMOS transistor N15. The drain of the fifteenth NMOS transistor N15 is connected to the drains and gates of the twentieth PMOS transistor P20 and the twenty-second PMOS transistor P22. The source of the twentieth PMOS transistor P20 is connected to the sources of the twenty-first PMOS transistor P21, the twenty-second PMOS transistor P22, and the twenty-fifth PMOS transistor P25. The drain of the twenty-second PMOS transistor P22 is connected to the sources of the twenty-third PMOS transistor P23 and the twenty-fourth PMOS transistor P24. The drain of the twenty-third PMOS transistor P23 is connected to the gates of the sixteenth NMOS transistor N16, the drains and gates of the seventeenth NMOS transistor N17, the gate of the eighteenth NMOS transistor N18, and the drain of the nineteenth PMOS transistor P19. The drain of the twenty-fourth PMOS transistor P24 is connected to the drains of the eighteenth NMOS transistor N18, the drains and gates of the twentieth NMOS transistor N20, the gate of the nineteenth NMOS transistor N19, and the gate of the twenty-first NMOS transistor N21. The gate of the twenty-first PMOS transistor P21 is connected to the gate of the twenty-fifth PMOS transistor P25. The drain of the twenty-first PMOS transistor P21 is connected to the drain of the fifteenth PMOS transistor P15. The drain of the twenty-fifth PMOS transistor P25 is connected to the drain of the twenty-first NMOS transistor N21 and the input terminal of the third inverter I3. The output terminal of the third inverter I3 is connected to the input terminal of the fourth inverter I4.

[0014] 6. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the clock circuit comprises a twenty-sixth PMOS transistor P26, a twenty-seventh PMOS transistor P27, a twenty-third NMOS transistor N23, a twenty-fourth NMOS transistor N24, a seventh resistor R7, a third comparator T3, a fourth comparator T4, a first NAND gate Y1, a second NAND gate Y2, a fifth inverter I5, a sixth inverter I6, a third capacitor C3, and an OSC_OK module.

[0015] The seventh resistor R7 of the clock circuit is connected to the positive terminals of the third comparator T3 and the fourth comparator T4. The source of the twenty-seventh PMOS transistor is connected to the source of the twenty-sixth PMOS transistor. The gate of the twenty-seventh PMOS transistor P27 is connected to the gate of the twenty-fourth NMOS transistor P24, the output terminal of the fifth inverter I5, and the input terminal of the sixth inverter I6. The drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor and the negative terminal of the fourth comparator T4. The gate of the twenty-sixth PMOS transistor P26 is connected to the gate of the twenty-seventh PMOS transistor P27 and the input terminal of the fifth inverter I5. The drain of the twenty-sixth PMOS transistor P26 is connected to the drain of the twenty-third NMOS transistor N23, one end of the third capacitor C3, and the negative terminal of the third comparator T3. One end of the third capacitor C3 is connected to the ground. The output terminal of the third comparator is connected to the A terminal of the first NAND gate Y1. The D terminal of the first NAND gate Y1 is connected to the output terminal of the second NAND gate Y2. The A terminal of the second NAND gate Y2 is connected to the output terminal of the first NAND gate Y1. The D terminal of the second NAND gate is connected to the output terminal of the fourth comparator T4. The output terminal of the sixth inverter I6 is connected to the OSC_OK module.

[0016] 7. The OSC module according to claim 6, wherein the OSC_OK module includes a first NOR gate H1, a second NOR gate H2, a third NOR gate H3, a fourth NOR gate H4, a fifth NOR gate H5, a sixth NOR gate H6, a third NAND gate Y3, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth inverter W5, a seventh inverter I7, an eighth inverter I8, and a ninth inverter I9.

[0017] The A terminal of the first NOR gate H1 of the OSC_OK module, the Q terminal of the first D flip-flop D1, and the A terminal of the sixth NOR gate H6 are connected. The B terminal of the first NOR gate H1 is connected to the A terminal of the third NOR gate H3, and the output terminal is connected to the A terminal of the fourth NOR gate H4. The B terminal of the fourth NOR gate H4 is connected to the output terminal of the second NOR gate H2. The output terminal of the fourth NOR gate H4 is connected to the input terminal of the seventh inverter I7. The output terminal of the seventh inverter I7 is connected to the D port of the first D flip-flop D1. The QN terminal of the first flip-flop D1, the A terminal of the second NOR gate H2, and the B terminal of the third NOR gate H3 are connected. The B terminal of the first NOR gate H1 is connected to the B terminal of the second NOR gate H2, the A terminal of the third NOR gate H3, the A terminal of the fifth NOR gate H5, and the Q terminal of the second D flip-flop. The output terminal of the second NOR gate H2 is connected to the B terminal of the fifth NOR gate H5. The output terminal of the fifth NOR gate H5 is connected to the input terminal of the eighth inverter I8. The output terminal of the eighth inverter I8 is connected to the D terminal of the second D flip-flop. The QN terminal of the second D flip-flop is connected to the B terminal of the sixth NOR gate H6. The output terminal of the sixth NOR gate H6 is connected to the B terminal of the third NAND gate Y3. The output terminal of the third NAND gate Y3 is connected to the input terminal of the ninth inverter I9.

[0018] 8. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the pre-regulator circuit includes an eighth resistor R8, a ninth resistor R9, a third capacitor C3, and a first high-voltage NMOS transistor NA1, a first voltage regulator G1, and a second voltage regulator G2.

[0019] One end of the eighth resistor R8 of the pre-regulator circuit is connected to the drain terminal of the first high-voltage NMOS transistor NA1 and is connected to the power supply. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and the output terminal of the first voltage regulator G1. The input terminal of the first voltage regulator is connected to one end of the third capacitor C3 and the input terminal of the second voltage regulator G2. The output terminal of the second voltage regulator G2 is connected to the other end of the first high-voltage NMOS transistor NA1. The gate of the first high-voltage regulator NA1 is connected to the ninth resistor R9.

[0020] 9. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the linear voltage regulator circuit includes: the twenty-eighth PMOS transistor P28, the twenty-ninth PMOS transistor P29, the thirtieth PMOS transistor P30, the thirty-first PMOS transistor P31, the thirty-second PMOS transistor P32, the thirty-third PMOS transistor P33, the twenty-fifth NMOS transistor N25, the twenty-sixth NMOS transistor N26, the twenty-seventh NMOS transistor N27, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29, the thirtieth NMOS transistor N30, the thirty-first NMOS transistor N31, the thirty-second NMOS transistor N32, the thirty-third NMOS transistor N33, the thirty-fourth NMOS transistor N34, the thirty-fifth NMOS transistor N35, the first high-voltage PMOS transistor PA1, the second high-voltage PMOS transistor PA2, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the third voltage regulator tube G3, the fourth voltage regulator tube G4, and the fifth voltage regulator tube G5.

[0021] The source electrodes of the twenty-fifth NMOS transistor N25, the twenty-sixth NMOS transistor N26, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29, the thirtieth NMOS transistor N30, the thirty-second NMOS transistor N32, the fourth capacitor C4, the eleventh resistor R11, the fifth capacitor C5, the input terminal of the fifth voltage regulator diode G5, the thirteenth resistor R13, and the fifteenth resistor R15 are connected together and connected to the ground wire. The drain electrode and the gate electrode of the twenty-fifth NMOS transistor N25 are connected to the gate electrode of the twenty-sixth NMOS transistor N26. The drain electrode of the twenty-sixth NMOS transistor N26 is connected to the drain electrode of the thirtieth PMOS transistor P30. The source electrodes of the thirtieth PMOS transistor P30 and the thirty-first PMOS transistor P31 are connected together. The gate electrode of the thirtieth PMOS transistor P30 is connected to the gate electrode of the thirty-first PMOS transistor P31. The drain electrode of the thirty-first PMOS transistor P31 is connected to the source electrodes of the thirty-second PMOS transistor P32 and the thirty-third PMOS transistor P33. The gate electrode of the thirty-second PMOS transistor P32 is connected to the tenth resistor R10 and the eleventh resistor R11. The drain electrode of the thirty-second PMOS transistor is connected to the drain electrode of the twenty-ninth NMOS transistor N29. The gate electrode of the twenty-ninth NMOS transistor is connected to the gate electrode of the twenty-eighth NMOS transistor N28. The gate-drain electrode of the twenty-eighth NMOS transistor is connected to the source electrode of the twenty-seventh NMOS transistor. The drain electrode of the twenty-seventh NMOS transistor is connected to the drain electrode and the gate electrode of the first high-voltage PMOS transistor PA1, the gate electrode of the second high-voltage PMOS transistor PA2, and the input terminal of the third voltage regulator diode G3. The source electrodes of the twenty-eighth PMOS transistor P28 and the twenty-ninth PMOS transistor P29, the output terminal of the third voltage regulator diode G3, the drain electrode of the thirty-third NMOS transistor, and the drain electrode of the thirty-fifth NMOS transistor are connected together and connected to the power supply terminal. The drain electrode of the twenty-ninth PMOS transistor P29 is connected to the source electrode of the second high-voltage transistor PA2. The drain electrode of the second high-voltage transistor PA2 is connected to the drain electrode of the thirty-first NMOS transistor N31, the fourth capacitor C4, the output terminal of the fourth voltage regulator diode G4, the gate electrode of the thirty-third NMOS transistor N33, the second resistor R2, the fourteenth resistor R14, the gate electrode of the thirty-fifth NMOS transistor N35, the gate electrode of the thirty-fourth NMOS transistor N34, and the sixth capacitor C6. The sixth capacitor C6 is connected to the ground. The source electrode of the thirty-third NMOS transistor N33 is connected to the input terminal of the fourth voltage regulator diode G4, the tenth resistor R10, the fifth capacitor C5, and the output terminal of the fifth voltage regulator diode G5. The source electrode of the thirty-fourth NMOS transistor N34 is connected to the thirteenth resistor. The source electrode of the thirty-fifth NMOS transistor N35 is connected to the fifteenth resistor R15.

[0022] 10. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the undervoltage protection circuit includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fifth comparator T5, a tenth inverter I10, an eleventh inverter I11, and a thirty-third NMOS transistor N33.

[0023] The sixteenth resistor R16 of the undervoltage protection circuit is connected to the negative terminals of the seventeenth resistor R17 and the seventh comparator T7. The other end of the sixteenth resistor R16 is connected to the power supply terminals of the fifth comparator T5, the tenth inverter I10, and the eleventh inverter I11. One end of the seventeenth resistor R17 is connected to the drain of the thirty-sixth NMOS transistor N36. The source of the thirty-sixth NMOS transistor N36 is connected to the eighteenth resistor R18. The output terminal of the fifth comparator T5 is connected to the input terminal of the tenth inverter I10. The output terminal of the tenth inverter I10 is connected to the input terminal of the eleventh inverter I11.

[0024] 11. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the overcurrent protection circuit includes: a thirty-seventh PMOS transistor P37, a thirty-eighth PMOS transistor P38, a thirty-fourth NMOS transistor N34, a thirty-fifth NMOS transistor N35, a sixth comparator T7, an eighth inverter I8, a ninth inverter I9, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a sixth capacitor C6, a third amplifier M3, a twelfth inverter I12, and a thirteenth inverter I13.

[0025] The power supply terminal of the third amplifier M3 is connected to the sources of the thirty-fourth PMOS transistor P34 and the thirty-fifth PMOS transistor P35 and is connected to the power supply. The output terminal of the third amplifier M3 is connected to the gate of the thirty-seventh NMOS transistor N37 and the sixth capacitor C6. The source of the thirty-seventh NMOS transistor is connected to the nineteenth capacitor R19 and the positive terminal of the third amplifier M3. The ground terminal of the third amplifier M3 is connected to the sixth capacitor C6, the nineteenth resistor R19, the twenty-second resistor R22, and the source of the thirty-eighth NMOS transistor. The gate of the thirty-eighth NMOS transistor is connected to the output terminal of the twelfth inverter I12 and the input terminal of the thirteenth inverter I13. The output terminal of the seventh comparator T7 is connected to the input terminal of the twelfth inverter I12.

[0026] The advantages and positive effects of the present invention are as follows: The present invention designs a high-speed and low-power PWM controller. The overall input is controlled within a voltage range of 4 - 20V, the static current is 30 μA, the operating frequency is 1.5 MHz, the operating current is 500 μA, the output current is above 1 A, and the efficiency reaches more than 90%, meeting most of the requirements of the market for power management chips. Description of the Drawings

[0027] Figure 1 This is the bandgap reference module circuit in the present invention

[0028] Figure 2 This is the soft start module circuit in the present invention

[0029] Figure 3 This is the error amplifier circuit module in the present invention

[0030] Figure 4 This is the comparator module in the present invention

[0031] Figure 5 This is the clock module in the present invention

[0032] Figure 6 This is OSC_OK in the present invention

[0033] Figure 7 This is the pre - voltage - regulation circuit in the present invention

[0034] Figure 8 This is the linear voltage - regulation circuit in the present invention

[0035] Figure 9 This is the under - voltage protection circuit in the present invention Figure 10 This is the over - current protection circuit in the present invention Figure 11 This is the overall system diagram of the present invention Detailed Description of the Invention

[0036] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] 1. The high - speed and low - power current - mode PWM controller as described in claim 1, wherein the bandgap reference circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PNP transistor Q1, a second PNP transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a first amplifier M1, a second amplifier M2, a first comparator T1, a first inverter I1, and a second inverter I2.

[0038] The source terminal of the first NMOS transistor N1 of the bandgap reference module is grounded and connected to the source terminals of the second NMOS transistor N2, the collector and base of the first PNP transistor Q1, the base and collector of the second PNP transistor Q2, one segment of the sixth resistor, and the source of the third NMOS transistor N3. The drain is connected to the drain, gate of the fourth PMOS transistor P4, and the gate of the second NMOS transistor N2. The source of the fourth NMOS transistor N4 is connected to the drain and gate of the third PMOS transistor P3. The source of the third PMOS transistor is connected to the drain and gate of the second PMOS transistor. The source of the second PMOS transistor P2 is connected to the gate and drain of the first PMOS transistor P1. The source of the first PMOS transistor P1 is connected to the sources of the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9. The gate of the fifth PMOS transistor P5 is connected to the gates of the sixth PMOS transistor, the drain of the second NMOS transistor N2, the output of the first amplifier M1, and the gate of the seventh PMOS transistor. The drain of the fifth PMOS transistor P5 is connected to one end of the first resistor R1, and the other end is connected to the collector of the first PNP transistor P1 and the positive terminal of the amplifier. The drain of the sixth PMOS transistor P6 is connected to the second resistor R2, the positive terminal of the first comparator T1, and the negative terminal of the second amplifier M2. The other end of the second resistor R2 is connected in series with the third resistor R3 and the fourth resistor R4, and the end of the fourth resistor R4 is connected to the collector of the second PNP transistor Q2. The drain of the eighth PMOS transistor P8 is connected in series with the fifth resistor R5 and the sixth resistor R6. One segment of the sixth resistor is connected to the drain terminal of the third NMOS transistor. The output terminal of the first comparator T1 is connected to the input terminal of the first inverter I1, and the output terminal of the first inverter I1 is connected to the input terminal of the second inverter and the gate of the third NMOS transistor N3. The output terminal of the second amplifier M2, the positive segment of the second amplifier M2, and the first capacitor C1 are connected, and the other end of the first capacitor C1 is grounded.

[0039] In this embodiment, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, and the first NMOS transistor N1 form a bias structure to control the second NMOS transistor N2. The fifth PMOS transistor P5 and the sixth PMOS transistor P6 together form a current mirror structure, and then together with the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first PNP transistor Q1, and the second PNP transistor Q2, they form the core part of the bandgap reference module. The first PNP transistor Q1 and the second PNP transistor Q2 are set to 1:8, and at the same time, the parameters of the resistors are configured to achieve an output voltage of 1.2V. The 1.2V reference voltage and the error amplifier are configured to improve the load-carrying capacity of the error amplifier. The seventh PMOS transistor P7, the eighth PMOS transistor P8, and the ninth PMOS transistor P9 output current. Subsequently, the first comparator T1, the first inverter I1, the second inverter I2, the third NMOS transistor N3, the sixth resistor R6, and the fifth resistor R5 together form the temperature protection circuit part of this PWM controller. It can achieve hysteresis temperature protection between 150° and 155°. The composition of the first inverter I1 and the second inverter I2 enhances the driving ability.

[0040] 2. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the soft-start circuit comprises: a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a second capacitor C2, a second comparator T2, and a first converter A1.

[0041] The source terminal of the fourth NMOS transistor N4, the drain terminal of the fifth NMOS transistor N5, one end of the second capacitor C2, the ground terminal of the second comparator T2, and the ground terminal of the first selector are connected. The gate and drain of the fourth NMOS transistor N4 are connected to the gate of the fifth NMOS transistor N5. The drain terminal of the fifth NMOS transistor N5 is connected to the drain terminal, gate terminal of the tenth PMOS transistor P10, the gate terminal of the eleventh PMOS transistor P11, the gate terminal of the twelfth PMOS transistor P12, and the gate terminal of the thirteenth PMOS transistor P13. The source of the eleventh PMOS transistor is connected to the source of the tenth PMOS transistor P10, the power supply terminal of the second comparator, and the power supply terminal of the first selector A1. One end of the second capacitor C2 and the positive segment of the second comparator T2 are connected to the 0 terminal of the first selector A1, and the negative segment of the second comparator T2 is connected to the 1 terminal of the first selector A1.

[0042] In this embodiment, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are combined into a current mirror structure, which realizes the biasing problem of the overall circuit. The combination of the tenth PMOS transistor P10 and the eleventh PMOS transistor P11 forms a current mirror structure, and then the biased current is introduced into the circuit. Subsequently, the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, and the thirteenth PMOS transistor P13 are combined together to bias the branch. The internal resistances of the three PMOS transistors are used for biasing to adjust the magnitude of the current, and the on and off times of the circuit are controlled together by controlling the magnitude of the second capacitor C2. The soft start control time is realized at about 800 μs, which can better meet the requirements of the vast majority of products in the market.

[0043] 3. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the error amplifier circuit comprises: a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19; a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13.

[0044] The source of the sixth NMOS transistor N6 in the error amplifier circuit described is connected to the sources of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, and the thirteenth NMOS transistor N13, and is connected to ground. The gate and drain of the sixth NMOS transistor N6 are connected to the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor N7 is connected to the drain of the fourteenth PMOS transistor P14, the gate of the fourteenth PMOS transistor P14, and the gate of the sixteenth PMOS transistor. The source of the fourteenth PMOS transistor P14 is connected to the sources of the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, and the nineteenth PMOS transistor P19. The drain of the sixteenth PMOS transistor P16 is connected to the sources of the seventeenth PMOS transistor P17 and the eighteenth PMOS transistor P18. The drain of the seventeenth NMOS transistor N17 is connected to the gate of the eighth NMOS transistor N8, the drain and gate of the ninth NMOS transistor N9, the gate of the tenth NMOS transistor N10, and the drain of the eleventh NMOS transistor. The drain of the eighteenth PMOS transistor P18 is connected to the drain of the tenth NMOS transistor N10, the drain and gate of the twelfth NMOS transistor N12, the gate of the eleventh NMOS transistor N11, and the gate of the thirteenth NMOS transistor N13. The gate of the fifteenth PMOS transistor P15 is connected to the gate of the nineteenth PMOS transistor P19. The drain of the fifteenth PMOS transistor P15 is connected to the drain of the eighth PMOS transistor P8. The drain of the nineteenth PMOS transistor P19 is connected to the drain of the thirteenth NMOS transistor N13.

[0045] In this example, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are combined into a current mirror structure to introduce a bias current. The fourteenth PMOS transistor P14 and the sixteenth PMOS transistor P16 are combined into a current mirror structure to introduce the introduced bias current into the core amplification module of this error amplifier. The sixteenth PMOS transistor P16 serves as the tail current source of the cross-coupled amplifiers of the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, and the twelfth NMOS transistor N12. The error amplifier in this part has a large gain, which can reach 90 dB. In addition, in order to achieve the overall high-speed characteristic, using this structure can also provide a high frequency characteristic and has low power consumption. The fifteenth PMOS transistor P15 and the nineteenth PMOS transistor P19 are combined into a current mirror.

[0046] 4. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the comparison circuit includes a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, a twenty-third PMOS transistor P23, a twenty-fourth PMOS transistor P24, and a twenty-fifth PMOS transistor P25. A fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, and a twenty-second NMOS transistor N22. A third inverter I3 and a fourth inverter I4.

[0047] For the error amplifier circuit described above, the source of the fourteenth NMOS transistor N14 is connected to the sources of the fifteenth NMOS transistor N15, the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N17, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, the twenty-first NMOS transistor N21, and the twenty-second NMOS transistor N22, and is grounded. The gate and drain of the fourteenth NMOS transistor N14 are connected to the gate of the fifteenth NMOS transistor N15. The drain of the fifteenth NMOS transistor N15 is connected to the drain and gate of the twentieth PMOS transistor P20 and the gate of the twenty-second PMOS transistor P22. The source of the twentieth PMOS transistor P20 is connected to the sources of the twenty-first PMOS transistor P21, the twenty-second PMOS transistor P22, and the twenty-fifth PMOS transistor P25. The drain of the twenty-second PMOS transistor P22 is connected to the sources of the twenty-third PMOS transistor P23 and the twenty-fourth PMOS transistor P24. The drain of the twenty-third PMOS transistor P23 is connected to the gate of the sixteenth NMOS transistor N16, the drain and gate of the seventeenth NMOS transistor N17, the gate of the eighteenth NMOS transistor N18, and the drain of the nineteenth PMOS transistor P19. The drain of the twenty-fourth PMOS transistor P24 is connected to the drain of the eighteenth NMOS transistor N18, the drain and gate of the twentieth NMOS transistor N20, the gate of the nineteenth NMOS transistor N19, and the gate of the twenty-first NMOS transistor N21. The gate of the twenty-first PMOS transistor P21 is connected to the gate of the twenty-fifth PMOS transistor P25. The drain of the twenty-first PMOS transistor P21 is connected to the drain of the fifteenth PMOS transistor P15. The drain of the twenty-fifth PMOS transistor P25 is connected to the drain of the twenty-first NMOS transistor N21 and the input terminal of the third inverter I3. The output terminal of the third inverter I3 is connected to the input terminal of the fourth inverter I4.

[0048] In this embodiment, the fourteenth NMOS transistor P14 and the fifteenth NMOS transistor P15 are combined to form a current mirror, and then the twentieth PMOS transistor P20 and the twenty-second PMOS transistor P22 are combined to form a current mirror to mirror the current of the previous current mirror into the cross-coupled amplifier. The twenty-third PMOS transistor P23, the twenty-fourth PMOS transistor P24, the seventeenth NMOS transistor N17, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, and the twentieth NMOS transistor N20 together form a cross-coupled amplifier, which can provide a large gain of 68 dB to achieve the amplification function. The third amplifier I3 and the fourth amplifier I4 are used for driving to improve the driving ability.

[0049] 5. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the clock circuit includes a twenty-sixth PMOS transistor P26, a twenty-seventh PMOS transistor P27, a twenty-third NMOS transistor N23, a twenty-fourth NMOS transistor N24, a seventh resistor R7, a third comparator T3, a fourth comparator T4, a first NAND gate Y1, a second NAND gate Y2, a fifth inverter I5, a sixth inverter I6, a third capacitor C3, and an OSC_OK module.

[0050] The seventh resistor R7 of the clock circuit is connected to the positive terminals of the third comparator T3 and the fourth comparator T4. The source electrodes of the twenty-seventh PMOS transistor and the twenty-sixth PMOS transistor are connected. The gate electrode of the twenty-seventh PMOS transistor P27 is connected to the gate electrode of the twenty-fourth NMOS transistor P24, the output terminal of the fifth inverter I5, and the input terminal of the sixth inverter I6. The drain electrode of the twenty-seventh PMOS transistor is connected to the drain electrode of the twenty-fourth NMOS transistor and the negative terminal of the fourth comparator T4. The gate electrode of the twenty-sixth PMOS transistor P26 is connected to the gate electrode of the twenty-seventh PMOS transistor P27 and the input terminal of the fifth inverter I5. The drain electrode of the twenty-sixth PMOS transistor P26 is connected to the drain electrode of the twenty-third NMOS transistor N23, one end of the third capacitor C3, and the negative terminal of the third comparator T3, and one end of the third capacitor C3 is connected to the ground. The output terminal of the third comparator is connected to the A terminal of the first NAND gate Y1, and the D terminal of the first NAND gate Y1 is connected to the output terminal of the second NAND gate Y2. The A terminal of the second NAND gate Y2 is connected to the output terminal of the first NAND gate Y1, and the D terminal of the second NAND gate is connected to the output terminal of the fourth comparator T4. The output terminal of the sixth inverter I6 is connected to the OSC_OK module.

[0051] 6. The OSC module as described in claim 6, wherein the OSC_OK module includes a first NOR gate H1, a second NOR gate H2, a third NOR gate H3, a fourth NOR gate H4, a fifth NOR gate H5, a sixth NOR gate H6, a third NAND gate Y3, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth inverter W5, a seventh inverter I7, an eighth inverter I8, and a ninth inverter I9.

[0052] The A terminal of the first NOR gate H1 of the OSC_OK module is connected to the Q terminal of the first D flip-flop D1 and the A terminal of the sixth NOR gate H6. The B terminal of the first NOR gate H1 is connected to the A terminal of the third NOR gate H3, and the output terminal is connected to the A terminal of the fourth NOR gate H4. The B terminal of the fourth NOR gate H4 is connected to the output terminal of the second NOR gate H2. The output terminal of the fourth NOR gate H4 is connected to the input terminal of the seventh inverter I7. The output terminal of the seventh inverter I7 is connected to the D port of the first D flip-flop D1. The QN terminal of the first flip-flop D1 is connected to the A terminal of the second NOR gate H2 and the B terminal of the third NOR gate H3. The B terminal of the first NOR gate H1 is connected to the B terminal of the second NOR gate H2, the A terminal of the third NOR gate H3, the A terminal of the fifth NOR gate H5, and the Q terminal of the second D flip-flop. The output terminal of the second NOR gate H2 is connected to the B terminal of the fifth NOR gate H5. The output terminal of the fifth NOR gate H5 is connected to the input terminal of the eighth inverter I8. The output terminal of the eighth inverter I8 is connected to the D terminal of the second D flip-flop. The QN terminal of the second D flip-flop is connected to the B terminal of the sixth NOR gate H6. The output terminal of the sixth NOR gate H6 is connected to the B terminal of the third NAND gate Y3. The output terminal of the third NAND gate Y3 is connected to the input terminal of the ninth inverter I9.

[0053] In this embodiment, the twenty-sixth PMOS transistor P26 and the twenty-third NMOS transistor N23 together form an inverter, and the twenty-seventh PMOS transistor P27 and the twenty-fourth NMOS transistor N24 together form an inverter. Then, the signals are compared by a comparator and then subjected to logic selection processing by a NAND gate, thereby realizing the amplification of the analog signal. Through the inverter and the OSC_OK module, the oscillation of the module is realized. It can achieve a frequency oscillation of 1.5 MHz. It meets the high-speed design requirements of this design.

[0054] 7. The high-speed and low-power current-mode PWM controller as described in claim 1, wherein the pre-regulator circuit includes an eighth resistor R8, a ninth resistor R9, a third capacitor C3, a first high-voltage NMOS transistor NA1, a first voltage regulator diode G1, and a second voltage regulator diode G2.

[0055] One end of the eighth resistor R8 of the pre-regulator circuit is connected to the drain of the first high-voltage NMOS transistor NA1 and is connected to the power supply. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and the output end of the first voltage regulator diode G1. The input end of the first voltage regulator diode is connected to one end of the third capacitor C3 and the input end of the second voltage regulator diode G2. The output end of the second voltage regulator diode G2 is connected to the other end of the first high-voltage NMOS transistor NA1. The gate of the first high-voltage voltage regulator transistor NA1 is connected to the ninth resistor R9.

[0056] In this example, the pre-regulator circuit uses the first voltage regulator diode G1, the second voltage regulator diode G2, and the first high-voltage NMOS transistor NA1 to step down a relatively high voltage. In this way, a voltage of 5 - 20V can be stepped down, and a voltage of 10 - 20V is basically stabilized at 4.6V - 5V. Thus, a relatively high voltage is pre-regulated.

[0057] 8. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the linear voltage regulator circuit includes: the twenty-eighth PMOS transistor P28, the twenty-ninth PMOS transistor P29, the thirtieth PMOS transistor P30, the thirty-first PMOS transistor P31, the thirty-second PMOS transistor P32, the thirty-third PMOS transistor P33, the twenty-fifth NMOS transistor N25, the twenty-sixth NMOS transistor N26, the twenty-seventh NMOS transistor N27, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29, the thirtieth NMOS transistor N30, the thirty-first NMOS transistor N31, the thirty-second NMOS transistor N32, the thirty-third NMOS transistor N33, the thirty-fourth NMOS transistor N34, the thirty-fifth NMOS transistor N35, the first high-voltage PMOS transistor PA1, the second high-voltage PMOS transistor PA2, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the third voltage regulator diode G3, the fourth voltage regulator diode G4, and the fifth voltage regulator diode G5.

[0058] The source electrodes of the twenty-fifth NMOS transistor N25, the twenty-sixth NMOS transistor N26, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29, the thirtieth NMOS transistor N30, the thirty-second NMOS transistor N32, the fourth capacitor C4, the eleventh resistor R11, the fifth capacitor C5, the input terminal of the fifth voltage regulator diode G5, the thirteenth resistor R13, and the fifteenth resistor R15 are connected together and connected to the ground wire. The drain electrode and the gate electrode of the twenty-fifth NMOS transistor N25 are connected to the gate electrode of the twenty-sixth NMOS transistor N26. The drain electrode of the twenty-sixth NMOS transistor N26 is connected to the drain electrode of the thirtieth PMOS transistor P30. The source electrodes of the thirtieth PMOS transistor P30 and the thirty-first PMOS transistor P31 are connected together. The gate electrode of the thirtieth PMOS transistor P30 is connected to the gate electrode of the thirty-first PMOS transistor P31. The drain electrode of the thirty-first PMOS transistor P31 is connected to the source electrodes of the thirty-second PMOS transistor P32 and the thirty-third PMOS transistor P33. The gate electrode of the thirty-second PMOS transistor P32 is connected to the tenth resistor R10 and the eleventh resistor R11. The drain electrode of the thirty-second PMOS transistor is connected to the drain electrode of the twenty-ninth NMOS transistor N29. The gate electrode of the twenty-ninth NMOS transistor is connected to the gate electrode of the twenty-eighth NMOS transistor N28. The drain and gate electrodes of the twenty-eighth NMOS transistor are connected to the source electrode of the twenty-seventh NMOS transistor. The drain electrode of the twenty-seventh NMOS transistor is connected to the drain and gate electrodes of the first high-voltage PMOS transistor PA1, the gate electrode of the second high-voltage PMOS transistor PA2, and the input electrode of the third voltage regulator diode G3. The source electrodes of the twenty-eighth PMOS transistor P28, the twenty-ninth PMOS transistor P29, the output terminal of the third voltage regulator diode G3, the drain electrode of the thirty-third NMOS transistor, and the drain electrode of the thirty-fifth NMOS transistor are connected together and connected to the power supply terminal. The drain electrode of the twenty-ninth PMOS transistor P29 is connected to the source electrode of the second high-voltage transistor PA2. The drain electrode of the second high-voltage transistor PA2 is connected to the drain electrode of the thirty-first NMOS transistor N31, the fourth capacitor C4, the output terminal of the fourth voltage regulator diode G4, the gate electrode of the thirty-third NMOS transistor N33, the second resistor R2, the fourteenth resistor R14, the gate electrode of the thirty-fifth NMOS transistor N35, the gate electrode of the thirty-fourth NMOS transistor N34, and the sixth capacitor C6. The sixth capacitor C6 is connected to the ground. The source electrode of the thirty-third NMOS transistor N33 is connected to the input terminal of the fourth voltage regulator diode G4, the tenth resistor R10, the fifth capacitor C5, and the output terminal of the fifth voltage regulator diode G5. The source electrode of the thirty-fourth NMOS transistor N34 is connected to the thirteenth resistor. The source electrode of the thirty-fifth NMOS transistor N35 is connected to the fifteenth resistor R15.

[0059] In the linear voltage regulator circuit of this embodiment, the twenty-fifth NMOS transistor N25 and the twenty-sixth NMOS transistor N26 are used to construct a current mirror structure, and the current mirror structure of this part is used to realize the biasing of this part of the circuit. Then, the thirtieth PMOS transistor P30 and the thirty-first PMOS transistor P31 form a current mirror structure to introduce the bias current into the amplifier module. The twenty-eighth PMOS transistor P28, the twenty-ninth PMOS transistor P29, the first high-voltage PMOS transistor PA1, and the second high-voltage PMOS transistor PA2 jointly reduce the voltage of the high-voltage part of the circuit. The third voltage regulator diode G3 is used to stabilize the voltage of the high-voltage transistor to prevent damage to the high-voltage transistor. The fourth voltage regulator diode G4 and the fifth voltage regulator diode G5 are respectively used to protect the thirty-third NMOS transistor N33 and the fifth capacitor C5, and then a voltage division is formed through the tenth resistor R10 and the eleventh resistor R11 to realize the output of a 5V voltage.

[0060] 9. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the under-voltage protection circuit includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fifth comparator T5, a tenth inverter I10, an eleventh inverter I11, and a thirty-third NMOS transistor N33.

[0061] The sixteenth resistor R16 and the seventeenth resistor R17 in the under-voltage protection circuit are connected to the negative terminal of the seventh comparator T7. The other end of the sixteenth resistor R16 is connected to the power supply terminal of the fifth comparator T5, the power supply terminal of the tenth inverter I10, and the power supply terminal of the eleventh inverter I11. One end of the seventeenth resistor R17 is connected to the drain of the thirty-sixth NMOS transistor N36. The source of the thirty-sixth NMOS transistor N36 is connected to the eighteenth resistor R18. The output terminal of the fifth comparator T5 is connected to the input terminal of the tenth inverter I10. The output terminal of the tenth inverter I10 is connected to the input terminal of the eleventh inverter I11.

[0062] In the under-voltage protection circuit of this embodiment, the sixteenth resistor R16, the seventeenth resistor R17, and the eighteenth resistor R18 control the negative terminal of the fifth comparator T5 through voltage division. The fifth comparator T5 is connected to the tenth inverter I10 and the eleventh inverter I11 behind it for driving. There needs to be a certain voltage interval between the drop and rise of the under-voltage protection circuit, thus realizing a voltage hysteresis of 1.4 - 1.6V.

[0063] 10. The high-speed and low-power current-mode PWM controller according to claim 1, wherein the overcurrent protection circuit comprises: the thirty-seventh PMOS transistor P37, the thirty-eighth PMOS transistor P38, the thirty-fourth NMOS transistor N34, the thirty-fifth NMOS transistor N35, the sixth comparator T7, the eighth inverter I8, the ninth inverter I9, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the sixth capacitor C6, the third amplifier M3, the twelfth inverter I12, and the thirteenth inverter I13.

[0064] The power supply terminal of the third amplifier M3, the source electrodes of the thirty-fourth PMOS transistor P34 and the thirty-fifth PMOS transistor P35 are connected to the power supply. The output terminal of the third amplifier M3 is connected to the gate of the thirty-seventh NMOS transistor N37 and the sixth capacitor C6. The source electrode of the thirty-seventh NMOS transistor is connected to the nineteenth capacitor R19 and the positive terminal of the third amplifier M3. The ground terminal of the third amplifier M3 is connected to the sixth capacitor C6, the nineteenth resistor R19, the twenty-second resistor R22, and the source electrode of the thirty-eighth NMOS transistor. The gate of the thirty-eighth NMOS transistor is connected to the output terminal of the twelfth inverter I12 and the input terminal of the thirteenth inverter I13. The output terminal of the seventh comparator T7 is connected to the input terminal of the twelfth inverter I12.

[0065] As mentioned above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention shall be covered by the protection scope of the present invention.

Claims

1. A high-speed, low-power current-mode PWM controller circuit, characterized in that The circuit includes a reference circuit, a bandgap reference circuit, a soft start circuit, an error amplifier circuit, a comparison circuit, a clock circuit, a pre-voltage regulator circuit, a linear voltage regulator circuit, an undervoltage protection circuit, an overcurrent protection circuit, a protection circuit, and a drive circuit.

2. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that: The bandgap reference circuit includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first PNP tube Q1, a second PNP tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a first amplifier M1, a second amplifier M2, a first comparator T1, a first inverter I1, and a second inverter I2. The source end of the first NMOS tube N1 of the bandgap reference module is grounded, and is connected to the source end of the second NMOS tube N2, the collector and base of the first PNP tube Q1, the base and collector of the second PNP tube Q2, a section of the sixth resistor, and the source of the third NMOS tube N3. The drain is connected to the drain, the gate, and the gate of the fourth PMOS tube P4 and the gate of the second NMOS tube N2. The source of the fourth NMOS tube N4 is connected to the drain and the gate of the third PMOS tube P3. The source of the third PMOS tube is connected to the drain and the gate of the second PMOS tube. The source of the second PMOS tube P2 is connected to the gate and the drain of the first PMOS tube P1. The source of the first PMOS tube P1 is connected to the source of the fifth PMOS tube P5, the source of the sixth PMOS tube P6, the source of the seventh PMOS tube P7, the source of the eighth PMOS tube P8, and the source of the ninth PMOS tube P9. The gate of the fifth PMOS tube P5 is connected to the gate of the sixth PMOS tube, the drain of the second NMOS tube N2, the output end of the first amplifier M1, and the gate of the seventh PMOS tube. The drain of the fifth PMOS tube P5 is connected to one end of the first resistor R1, and the other end is connected to the collector of the first PNP tube P1 and the positive end of the amplifier. The drain of the sixth PMOS tube P6 is connected to the second resistor R2, the positive end of the first comparator T1, and the negative end of the second amplifier M2. The other end of the second resistor R2 is connected in series with the third resistor R3 and the fourth resistor R4, and the end of the fourth resistor R4 is connected to the collector of the second PNP tube Q2. The drain of the eighth PMOS tube P8 is connected in series with the fifth resistor R5 and the sixth resistor R6. A section of the sixth resistor is connected to the drain end of the third NMOS tube. The output end of the first comparator T1 is connected to the input end of the first inverter I1, and the output end of the first inverter I1 is connected to the input end of the second inverter and the gate of the third NMOS tube N3. The output end of the second amplifier M2 and the positive section of the second amplifier M2 are connected to the first capacitor C1, and the other end of the first capacitor C1 is connected to the ground.

3. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The soft start circuit includes: a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourth NMOS tube N4, a fifth NMOS tube N5, a second capacitor C2, a second comparator T2, and a first converter A1. The source end of the fourth NMOS tube N4 of the soft start module, the far end of the fifth NMOS tube N5, a section of the second capacitor C2, the ground end of the second comparator T2, and the ground end of the first selector are connected. The gate and drain of the fourth NMOS tube N4 and the gate of the fifth NMOS tube N5 are connected. The drain end of the fifth NMOS tube N5 is connected to the drain end and gate end of the tenth PMOS tube P10, the gate end of the eleventh PMOS tube P11, the gate end of the twelfth PMOS tube P12, and the gate end of the thirteenth PMOS tube P13. The source of the eleventh PMOS tube is connected to the source of the tenth PMOS tube P10 and the power supply end of the second comparator and the power supply end of the first selector A1. One end of the second capacitor C2 is connected to the 0 end of the first selector A1 of the positive section of the second comparator T2, and the negative end of the second comparator T2 is connected to the 1 end of the first selector A1.

4. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The error amplifier circuit includes: a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17, an eighteenth PMOS tube P18, and a nineteenth PMOS tube P19. A sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, and a thirteenth NMOS tube N13. The source of the sixth NMOS tube N6 of the error amplifier circuit is connected to the source of the seventh NMOS tube N7, the source of the eighth NMOS tube N8, the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10, the source of the eleventh NMOS tube N11, the source of the twelfth NMOS tube N12, and the source of the thirteenth NMOS tube N13, and is connected to the ground. The gate and drain of the sixth NMOS tube N6 are connected to the gate of the seventh NMOS tube. The drain of the seventh NMOS tube N7 is connected to the drain of the fourteenth PMOS tube P14, the gate of the fourteenth PMOS tube P14, and the gate of the sixteenth PMOS tube. The source of the fourteenth PMOS tube P14 is connected to the source of the fifteenth PMOS tube P15, the source of the sixteenth PMOS tube P16, and the source of the nineteenth PMOS tube P19. The drain of the sixteenth PMOS tube P16 is connected to the source of the seventeenth PMOS tube P17 and the source of the eighteenth PMOS tube P18. The drain of the seventeenth NMOS tube N17 is connected to the gate of the eighth NMOS tube N8, the drain and gate of the ninth NMOS tube N9, the gate of the tenth NMOS tube N10, and the drain of the eleventh NMOS tube. The drain of the eighteenth PMOS tube P18 is connected to the drain of the tenth NMOS tube N10, the drain and gate of the twelfth NMOS tube N12, the gate of the eleventh NMOS tube N11, and the gate of the thirteenth NMOS tube N13. The gate of the fifteenth PMOS tube P15 is connected to the gate of the nineteenth PMOS tube P19. The drain of the fifteenth PMOS tube P15 is connected to the drain of the eighth PMOS tube P8. The drain of the nineteenth PMOS tube P19 is connected to the drain of the thirteenth NMOS tube N13.

5. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The comparison circuit includes a 20th PMOS tube P20, a 21st PMOS tube P21, a 22nd PMOS tube P22, a 23rd PMOS tube P23, a 24th PMOS tube P24, and a 25th PMOS tube P25. A 14th NMOS tube N14, a 15th NMOS tube N15, a 16th NMOS tube N16, a 17th NMOS tube N17, an 18th NMOS tube N18, a 19th NMOS tube N19, a 20th NMOS tube N20, a 21st NMOS tube N21, and a 22nd NMOS tube N22. A third inverter I3 and a fourth inverter I4. The source of the fourteenth NMOS tube N14 of the error amplifier circuit is connected to the source of the fifteenth NMOS tube N15, the source of the sixteenth NMOS tube N16, the source of the seventeenth NMOS tube N17, the source of the eighteenth NMOS tube N18, the source of the nineteenth NMOS tube N19, the source of the twentieth NMOS tube N20, and the source of the twenty-first NMOS tube N21, and is connected to the ground. The gate and drain of the fourteenth NMOS tube N14 and the gate of the fifteenth NMOS tube N15 are connected. The drain of the fifteenth NMOS tube N15 is connected to the drain of the twentieth PMOS tube P20, the gate of the twentieth PMOS tube P20, and the gate of the twenty-second PMOS tube P22. The source of the twentieth PMOS tube P20 is connected to the source of the twenty-first PMOS tube P21, the source of the twenty-second PMOS tube P22, and the source of the twenty-fifth PMOS tube P25. The drain of the twenty-second PMOS tube P22 is connected to the source of the twenty-third PMOS tube P23 and the source of the twenty-fourth PMOS tube P24. The drain of the twenty-third PMOS tube P23 is connected to the gate of the sixteenth NMOS tube N16, the drain and gate of the seventeenth NMOS tube N17, the gate of the eighteenth NMOS tube N18, and the drain of the nineteenth NMOS tube P19. The drain of the twenty-fourth PMOS tube P24 is connected to the drain of the eighteenth NMOS tube N18, the drain and gate of the twentieth NMOS tube N20, the gate of the nineteenth NMOS tube N19, and the gate of the twenty-first NMOS tube N21. The gate of the twenty-first PMOS tube P21 is connected to the gate of the twenty-fifth PMOS tube P25. The drain of the twenty-first PMOS tube P21 is connected to the drain of the fifteenth PMOS tube P15. The drain of the twenty-fifth PMOS tube P25 is connected to the drain of the twenty-first NMOS tube N21 and the input end of the third inverter I3. An output terminal of the third inverter I3 is connected to an input terminal of the fourth inverter I4.

6. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The clock circuit includes a twenty-sixth PMOS tube P26, a twenty-seventh PMOS tube P27, a twenty-third NMOS tube N23, a twenty-fourth NMOS tube N24, a seventh resistor R7, a third comparator T3, a fourth comparator T4, a first NAND gate Y1, a second NAND gate Y2, a fifth inverter I5, a sixth inverter I6, a third capacitor C3, and an OSC_OK module. The seventh resistor R7 of the clock circuit is connected to the positive end of the third comparator T3 and the positive end of the fourth comparator T4. The source of the twenty-seventh PMOS tube is connected to the source of the twenty-sixth PMOS tube, and the gate of the twenty-seventh PMOS tube P27 is connected to the gate of the twenty-fourth NMOS tube P24, the output end of the fifth inverter I5, and the input end of the sixth inverter I6. The drain of the twenty-seventh PMOS tube is connected to the drain of the twenty-fourth NMOS tube and the negative end of the fourth comparator T4. The gate of the twenty-sixth PMOS tube P26 is connected to the gate of the twenty-seventh PMOS tube P27 and the input end of the fifth inverter I5. The drain of the twenty-sixth PMOS tube P26 is connected to the drain of the twenty-third NMOS tube N23, one end of the third capacitor C3, and the negative end of the third comparator T3, and one end of the third capacitor C3 is connected to the ground. The output end of the third comparator is connected to the A end of the first NAND gate Y1, and the D end of the first NAND gate Y1 is connected to the output end of the second NAND gate Y2. The A terminal of the second NAND gate Y2 is connected to the output terminal of the first NAND gate Y1, the D terminal of the second NAND gate is connected to the output terminal of the fourth comparator T4, and the output terminal of the sixth inverter I6 is connected to the OSC_OK module.

7. The OSC module according to claim 6, characterized in that The OSC_OK module includes a first NOR gate H1, a second NOR gate H2, a third NOR gate H3, a fourth NOR gate H4, a fifth NOR gate H5, a sixth NOR gate H6, a third NAND gate Y3, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth inverter W5, a seventh inverter I7, an eighth inverter I8, and a ninth inverter I9. The A end of the first NOR gate H1 of the OSC_OK module is connected to the Q end of the first D flip-flop D1 and the A end of the sixth NOR gate H6. The B end of the first NOR gate H1 is connected to the A end of the third NOR gate H3, and the output end is connected to the A end of the fourth NOR gate H4. The B end of the fourth NOR gate H4 is connected to the output end of the second NOR gate H2. The output end of the fourth NOR gate H4 is connected to the input end of the seventh inverter I7. The output end of the seventh inverter I7 is connected to the D port of the first D flip-flop D1. The QN end of the first flip-flop D1 is connected to the A end of the second NOR gate H2 and the B end of the third NOR gate H3. The B end of the first NOR gate H1 is connected to the B end of the second NOR gate H2, the A end of the third NOR gate H3, the A end of the fifth NOR gate H5, and the Q end of the second D flip-flop. The output end of the second NOR gate H2 is connected to the B end of the fifth NOR gate H5. The output end of the fifth NOR gate H5 is connected to the input end of the eighth inverter I8. The output end of the eighth inverter I8 is connected to the D end of the second D flip-flop. The QN end of the second D flip-flop is connected to the B end of the sixth NOR gate H6. The output end of the sixth NOR gate H6 is connected to the B end of the third NAND gate Y3. The output end of the third NAND gate Y3 is connected to the input end of the ninth inverter I9.

8. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The pre-voltage stabilization circuit includes an eighth resistor R8, a ninth resistor R9, a third capacitor C3, a first high-voltage NMOS tube NA1, a first voltage stabilization tube G1, and a second voltage stabilization tube G2. One end of the eighth resistor R8 of the pre-voltage stabilization circuit is connected to the drain end of the first high-voltage NMOS tube NA1 and is connected to a power supply. The other end of the eighth resistor R8 is connected to one end of the ninth resistor R9 and the output end of the first voltage regulator tube G1. The input end of the first voltage regulator tube is connected to one end of the third capacitor C3 and the input end of the second voltage regulator tube G2. The output end of the second voltage regulator tube G2 is connected to the other end of the first high-voltage NMOS tube NA1. The gate of the first high-voltage voltage regulator tube NA1 is connected to the ninth resistor R9.

9. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The linear voltage stabilizing circuit includes: a twenty-eighth PMOS tube P28, a twenty-ninth PMOS tube P29, a thirtieth PMOS tube P30, a thirty-first PMOS tube P31, a thirty-second PMOS tube P32, a thirty-third PMOS tube P33, a twenty-fifth NMOS tube N25, a twenty-sixth NMOS tube N26, a twenty-seventh NMOS tube N27, a twenty-eighth NMOS tube N28, a twenty-ninth NMOS tube N29, a thirtieth NMOS tube N30, a thirty-first NMOS tube N31, The thirty-second NMOS tube N32, the thirty-third NMOS tube N33, the thirty-fourth NMOS tube N34, the thirty-fifth NMOS tube N35, the first high-voltage PMOS tube PA1, the second high-voltage PMOS tube PA2, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the third voltage regulator tube G3, the fourth voltage regulator tube G4, and the fifth voltage regulator tube G5. The source of the 25th NMOS tube N25 is connected to the source of the 26th NMOS tube N26, the source of the 28th NMOS tube N28, the source of the 29th NMOS tube N29, the source of the 30th NMOS tube N30, the source of the 32nd NMOS tube N32, the fourth capacitor C4, the 11th resistor R11, the fifth capacitor C5, the input end of the fifth voltage regulator tube G5, the 13th resistor R13, and the 15th resistor R15, and is connected to the ground line. The drain of the 25th NMOS tube N25 is connected to the gate and the gate of the 26th NMOS tube N26. The drain of the 26th NMOS tube N26 is connected to the drain of the 30th PMOS tube P30. The source of the 30th PMOS tube P30 is connected to the source of the 31st PMOS tube P31. The gate of the 30th PMOS tube P30 is connected to the gate of the 31st PMOS tube P31. The drain of the thirty-first PMOS tube P31 is connected to the source of the thirty-second PMOS tube P32 and the source of the thirty-third PMOS tube P33. The gate of the thirty-second PMOS tube P32 is connected to the tenth resistor R10 and the eleventh resistor R11. The drain of the thirty-second PMOS tube is connected to the drain of the twenty-ninth NMOS tube N29. The gate of the twenty-ninth NMOS tube is connected to the gate of the twenty-eighth NMOS tube N28. The gate-drain of the twenty-eighth NMOS tube is connected to the source of the twenty-seventh NMOS tube. The drain of the twenty-seventh NMOS tube is connected to the drain and gate of the first high-voltage PMOS tube PA1, the gate of the second high-voltage PMOS tube PA2, and the input electrode of the third voltage regulator tube G3. The source of the twenty-eighth PMOS tube P28 is connected to the source of the twenty-ninth PMOS tube P29, the output electrode of the third voltage regulator tube G3, the drain of the thirty-third NMOS tube, and the drain of the thirty-fifth NMOS tube and connected to the power supply electrode. The drain of the twenty-ninth PMOS tube P29 is connected to the source of the second high-voltage tube PA2. The drain of the second high-voltage tube PA2 is connected to the drain of the thirty-first NMOS tube N31, the fourth capacitor C4, the output end of the fourth voltage-stabilizing tube G4, the gate of the thirty-third NMOS tube N33, the second resistor R2, the fourteenth resistor R14, the thirty-fifth NMOS tube N35, the gate of the thirty-fourth NMOS tube N34, and the sixth capacitor C6. The sixth capacitor C6 is connected to the ground. The source of the thirty-third NMOS tube N33 is connected to the input end of the fourth voltage-stabilizing tube G4, the tenth resistor R10, the fifth capacitor C5, and the output end of the fifth voltage-stabilizing tube G5. The source of the thirty-fourth NMOS tube N34 is connected to the thirteenth resistor. The source of the thirty-fifth NMOS tube N35 is connected to the fifteenth resistor R15.

10. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The undervoltage protection circuit includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fifth comparator T5, a tenth inverter I10, an eleventh inverter I11, and a thirty-third NMOS tube N33. The undervoltage protection circuit comprises a sixteenth resistor R16, a seventeenth resistor R17 and a negative terminal of the seventh comparator T7. The other end of the sixteenth resistor R16 is connected to the power supply terminal of the fifth comparator T5, the power supply terminal of the tenth inverter I10 and the power supply terminal of the eleventh inverter I11. One end of the seventeenth resistor R17 is connected to the drain of the thirty-sixth NMOS tube N36. The source end of the thirty-sixth NMOS tube N36 is connected to the eighteenth resistor R18. The output end of the fifth comparator T5 is connected to the input end of the tenth inverter I10. The output end of the tenth inverter I10 is connected to the input end of the eleventh inverter I11.

11. The high-speed, low-power current-mode PWM controller according to claim 1, characterized in that The overcurrent protection circuit includes: a thirty-seventh PMOS tube P37, a thirty-eighth PMOS tube P38, a thirty-fourth NMOS tube N34, a thirty-fifth NMOS tube N35, a sixth comparator T7, an eighth inverter I8, a ninth inverter I9, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a sixth capacitor C6, a third amplifier M3, a twelfth inverter I12, and a thirteenth inverter I13. The power supply terminal of the third amplifier M3 is connected to the source of the 34th PMOS tube P34 and the source of the 35th PMOS tube P35, and is also connected to the power supply. The output terminal of the third amplifier M3 is connected to the gate of the 37th NMOS tube N37 and the sixth capacitor C6. The source of the 37th NMOS tube is connected to the 19th capacitor R19 and the positive end of the third amplifier M3. The ground terminal of the third amplifier M3 is connected to the sixth capacitor C6, the 19th resistor R19, the 22nd resistor R22, and the source of the 38th NMOS tube. The gate of the 38th NMOS tube is connected to the output terminal of the 12th inverter I12 and the input terminal of the 13th inverter I13. The output terminal of the seventh comparator T7 is connected to the input terminal of the 12th inverter I12.

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