Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes three types of cells as a plurality of logic gates. The first cell includes a p-type MOSFET having a first threshold voltage and an n-type MOSFET having a second threshold voltage. The second cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a fourth threshold voltage. The third cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a second threshold voltage. An absolute value of the first threshold voltage is higher than an absolute value of the third threshold voltage, and an absolute value of the second threshold voltage is higher than an absolute value of the fourth threshold voltage.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-212398, including the specification, drawings, and abstract, filed on December 15, 2023, is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2008-305950

[0006] A semiconductor device having a logic gate including a p-channel MOSFET and an n-channel MOSFET is known. Patent Document 1 discloses a semiconductor device having a logic gate including a p-channel MOSFET and an n-channel MOSFET. Summary of the Invention

[0007] There has been a continuous demand for semiconductor devices having logic gates to further increase the operating speed of the logic gates and further reduce power consumption.

[0008] Generally, in a semiconductor device having a logic gate including a p-channel MOSFET and an n-channel MOSFET, in order to increase the operating (i.e., switching) speed, it is necessary to lower the gate threshold voltage of the FET. On the other hand, in an FET having a low gate threshold voltage, when the FET is turned off, the leakage current is relatively large, thereby increasing power consumption.

[0009] As described above, in a logic gate including a p-channel MOSFET and an n-channel MOSFET, there is usually a trade-off relationship between the operating speed and power consumption. For example, in order to further improve the operating speed and power consumption, developing new devices incurs financial and time costs.

[0010] A semiconductor device including a logic gate is necessary to improve the balance between the operating speed and power consumption while suppressing costs.

[0011] In a representative embodiment, a semiconductor device includes three types of cells as multiple logic gates. The first cell includes a p-channel MOSFET having a first threshold voltage and an n-channel MOSFET having a second threshold voltage. The second cell includes a p-channel MOSFET having a third threshold voltage and an n-channel MOSFET having a fourth threshold voltage. The third cell includes a p-channel MOSFET having a third threshold voltage and an n-channel MOSFET having a second threshold voltage. The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, and the absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage.

[0012] According to an embodiment, in a semiconductor device including logic gates, a balance between operation speed and power consumption can be improved while suppressing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a configuration example of a representative logic gate as a cell.

[0014] Figure 2 is a diagram illustrating a state in which leakage current flows in a cell.

[0015] Figure 3 is a diagram illustrating examples of rise time and fall time of an output in a cell.

[0016] Figure 4 is a graph illustrating an example of a relationship between cell drive power ratio and cell leakage with respect to LVT cells and HVT cells.

[0017] Figure 5 is a graph illustrating an example of a relationship between cell drive power ratio and cell leakage with respect to MVT cells.

[0018] Figure 6 is a diagram illustrating a configuration example of a semiconductor device according to a first embodiment.

[0019] Figure 7 is a diagram illustrating a configuration example of a third cell according to a first embodiment.

[0020] Figure 8 is a graph illustrating a relationship between drive power of three types of cells and cell leakage according to a first embodiment.

[0021] Figure 9 is a diagram illustrating an estimation of an effect of reducing cell leakage by cell replacement according to a first embodiment.

[0022] Figure 10 is a graph illustrating an example of a relationship between drive power of a cell and cell leakage according to a first embodiment.

[0023] Figure 11 It is a graph showing an example of the relationship between the operation speed of a cell and the cell leakage according to the first embodiment.

[0024] Figure 12 It is a flowchart showing an example of a method for manufacturing a cell according to the first embodiment.

[0025] Figure 13 It is a flowchart showing an example of a well formation process according to the first embodiment.

[0026] Figure 14 It is a flowchart showing an example of a gate formation process according to the first embodiment.

[0027] Figure 15 It is a diagram showing an example of three types of cells arranged on a semiconductor substrate according to the first embodiment.

[0028] Figure 16 It is a diagram showing an example of four types of masks according to the first embodiment.

[0029] Figure 17 It is a flowchart showing an example of an impurity implantation process for adjusting the threshold voltage according to the first embodiment.

[0030] Figure 18 It is a diagram showing an example of the configuration of a NOT (INV) type cell according to the second embodiment.

[0031] Figure 19 It is a graph showing an example of the relationship between the operation speed of a cell and the cell leakage according to the second embodiment.

[0032] Figure 20 It is a diagram showing an example of the configuration of a combinational circuit according to the related art.

[0033] Figure 21 It is a diagram showing an example of the configuration of a combinational circuit according to the third embodiment.

[0034] Figure 22 It is a diagram showing an example of the configuration of a NAND circuit type cell according to the fourth embodiment.

[0035] Figure 23 It is a graph showing an example of the relationship between the number of stages of vertically stacked n-type MOSFETs in a NAND circuit type cell according to the fourth embodiment and the on-current.

[0036] Figure 24FIG. illustrates an example in which HVT(p) cells and LVT(n) cells are applied to a NAND circuit type cell according to the fourth embodiment. DETAILED DESCRIPTION

[0037] (Background Reviewed by Inventor)

[0038] A semiconductor device including a digital logic circuit is known. The digital logic circuit includes a plurality of logic gates. Each logic gate includes a p-channel MOSFET connected to a line on the high potential side of a power supply and an n-channel MOSFET connected to a line on the low potential side of the same power supply. Such a semiconductor device is, for example, an integrated circuit, and as a specific example, there is a semiconductor chip obtained by cutting a semiconductor wafer.

[0039] Generally, mask and layout design of a digital logic circuit (e.g., a CMOS digital logic circuit) is performed by combining pre-standardized and provided basic circuits. The basic circuit is generally called a cell. The cell is a logic gate or a circuit in which logic gates are combined. Examples of cells include logic gates such as NOT (INV), NAND, NOR, AND-OR-INV (AOI), and OR-AND-INV (OAI). In addition, examples of cells also include basic logic circuits (such as flip-flops and multiplexers) and auxiliary circuits (such as gated clocks, buffers, and delay circuits).

[0040] The set of cells provided in advance as described above is called a "cell library". In the design of a digital logic circuit, a desired digital logic circuit is designed by laying out cells selected from the cell library on a semiconductor substrate and connecting these cells by wiring.

[0041] Figure 1 Configuration examples of a NOT (INV) type cell 21, a NAND type cell 22, and a NOR type cell 23 are illustrated. In Figure 1 Vdd indicates a line on the high potential side of the power supply. Vss or GND indicates a line on the low potential side of the same power supply. In addition, A and B indicate input terminals, and Y indicates an output terminal. As Figure 1 illustrated, each logic gate includes a p-channel MOSFET connected to the line Vdd on the high potential side of the power supply and an n-channel MOSFET connected to the line Vss or GND on the low potential side of the same power supply.

[0042] Note that in this specification and the drawings, a p-channel MOSFET may be referred to as a p-type MOSFET or a pFET. In addition, an n-channel MOSFET may be referred to as an n-type MOSFET or an nFET.

[0043] Logic gates are the basic building blocks of cells. Depending on differences in purpose (function), size, operating speed, drive power, etc., multiple types of cells (e.g., cells with 1000 or more patterns) are provided as logic gates.

[0044] In recent years, semiconductor devices including digital logic circuits (including such logic gates) have been required to achieve increased operating speed and reduced power consumption.

[0045] Generally, in order to increase the operating speed of a semiconductor device including cells, it is necessary to configure a logic gate by combining a p-type MOSFET with a low absolute value of the gate threshold voltage Vt and an n-type MOSFET with a low absolute value of the gate threshold voltage Vt. However, when the absolute value of the gate threshold voltage Vt is reduced, the leakage current when the MOSFET is turned off increases, and the power consumption increases. In other words, in a semiconductor device including MOSFETs, there is a trade-off relationship between the operating speed and the power consumption. Hereinafter, the relationship between the leakage current and the operating speed in MOSFETs will be described.

[0046] Here, the leakage current flowing through the cell is also referred to as cell leakage. In addition, the current flowing through the MOSFET when it is turned on (ON) is also referred to as the on-current, and the leakage current flowing through the MOSFET when it is turned off (OFF) is also referred to as the off-leakage.

[0047] Figure 2 An example of a NOT (INV) type cell 21, which is a representative cell in a CMOS circuit, is illustrated. As Figure 2 illustrated, when an on-signal is input to the input terminal A of the NOT type cell 21, the off-leakage 21L of the NOT type cell 21 is determined by the off-leakage value IoffP of the p-type MOSFET. On the contrary, when an off-signal is input to the input terminal A, the off-leakage 21L of the NOT type cell 21 is determined by the off-leakage value IoffN of the n-type MOSFET. In the operation of the NOT type cell 21, when it is assumed that the time when the on-signal is input to the input terminal A and the time when the off-signal is input to the input terminal A are approximately the same, the average leakage current Ileak_ave per unit time can be expressed by Expression (1) described below.

[0048]

Expression 1

[0049] I leak_ave=(I offN+I offP) / 2 (1)

[0050] Figure 3The example of the rise time Traise when a turn-on signal is output to the output terminal Y of the NOT-type cell and the example of the fall time Tfall when a turn-off signal is output to the output terminal Y of the NOT-type cell are illustrated. When the rise time Traine is short, the rise slope becomes steep, and when the rise time Traise is long, the rise slope becomes gentle. When the fall time Tfall is short, the fall slope becomes steep, and when the fall time Tfall is long, the fall slope becomes gentle.

[0051] As Figure 3 Illustrated, considering the operation speed in the NOT-type cell, the rise time Traise is determined by the on-current value IonP of the p-type MOSFET and is proportional to the load capacitance Cload / IonP, where the circuit load is Cload. On the other hand, the fall time Tfall is determined by the on-current value IonN of the n-type MOSFET and is proportional to the load capacitance Cload / IonN. The load capacitance is a value, that is, the time obtained by dividing the circuit load Cload by the on-current. Here, the average circuit operation speed (i.e., the average switching time Tpd) can be expressed by the following expression (2).

[0052]

Expression 2

[0053]

[0054] Generally, many semiconductor device manufacturers have four types of design models for the gate threshold voltage Vt of MOSFETs. Specifically, as the gate threshold voltage Vt designed for the p-type MOSFET, there are a threshold voltage HVTP and a threshold voltage LVTP. The absolute value of the threshold voltage LVTP is lower than the absolute value of the threshold voltage HVTP. In addition, as the gate threshold voltage Vt designed for the n-type MOSFET, there are a threshold voltage HVTN and a threshold voltage LVTN. The absolute value of the threshold voltage LVTN is lower than the absolute value of the threshold voltage HVTN.

[0055] Semiconductor device manufacturers design two types of logic gates with different balances between operation speed and leakage current by using four types of gate threshold voltage design models. The first type of logic gate is a high-speed operation / high-leakage current type logic gate. The second type of logic gate is a low-speed operation / low-leakage current type logic gate.

[0056] The high-speed operation / high leakage current type logic gate includes a p-type MOSFET having a threshold voltage LVTP and an n-type MOSFET having a threshold voltage LVTN. In this specification, the unit of the high-speed operation / high leakage current type logic gate is also referred to as an LVT unit. In addition, the low-speed operation / low leakage current type logic gate includes a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HVTN. In this specification, the unit of the low-speed operation / low leakage current type logic gate is also referred to as an HVT unit.

[0057] As can be understood from Figure 3 Generally, as the absolute value of the gate threshold voltage Vt of the MOSFETs constituting the unit increases, that is, as the on-current of the unit decreases, the rise time and fall time of the signal output Y of the unit become longer, and the rise and fall become slower. On the contrary, as the gate threshold voltage Vt of the FETs constituting the unit decreases, that is, as the on-current of the unit increases, the rise time and fall time of the signal output Y of the unit become shorter, and the rise and fall become faster. That is, as Figure 3 indicated by the arrows SH31 and SH32 in

[0058] As Figure 4 illustrated, when comparing the LVT unit and the HVT unit having the same drive power, it can be seen that the unit leakage of the LVT unit is approximately 16 times that of the unit leakage of the HVT unit.

[0059] Semiconductor device manufacturers use LVT units in parts that require high-speed operation, and use HVT units in parts that do not require high-speed operation as fast as the LVT units. Therefore, semiconductor devices are designed to minimize unit leakage while ensuring the required operating speed.

[0060] However, in reality, the digital circuit part using the high-speed operation / high leakage current type LVT unit includes parts whose operation speed is sufficient to be an intermediate speed between the operation speed of the LVT unit and the operation speed of the HVT unit.

[0061] Therefore, as one of the methods to further suppress power consumption while ensuring the operation speed, it can be imagined that semiconductor devices are designed to include newly added MVT units, which have the characteristic that the balance between the operation speed and the leakage current is in the middle of the LVT unit and the HVT unit.

[0062] As Figure 5As shown, when comparing LVT cells, HVT cells, and MVT cells with the same drive power, it can be seen that the cell leakage of the MVT cells is approximately in the middle of the cell leakage of the LVT cells and the cell leakage of the HVT cells.

[0063] To design MVT cells, an intermediate threshold voltage MVTP is added as a design model for the gate threshold voltage of p-type MOSFETs, and an intermediate threshold voltage MVTN is added as a design model for the gate threshold voltage of n-type MOSFETs. The absolute value of the threshold voltage MVTP is higher than the absolute value of the threshold voltage LVTP and lower than the absolute value of the threshold voltage HVTP. In addition, the absolute value of the threshold voltage MVTN is higher than the absolute value of the threshold voltage LVTN and lower than the absolute value of the threshold voltage HVTN. Then, a new MVT cell is provided, which is a combination of a p-type MOSFET with the threshold voltage MVTP and an n-type MOSFET with the threshold voltage MVTN.

[0064] Semiconductor device manufacturers selectively use three types of cells, including LVT cells, HVT cells, and MVT cells, for each logic gate in the digital circuit section of semiconductor devices according to the required operating speed. Here, this method is called the standard method.

[0065] According to this standard method, in the digital circuit section of a semiconductor device, among the parts where LVT cells must be used, parts that allow the operating speed of MVT cells can be replaced with MVT cells having a leakage current smaller than that of LVT cells. Therefore, in a semiconductor device including a digital circuit, compared with semiconductor devices in the related art, power consumption can be suppressed while ensuring the required operating speed.

[0066] However, the standard method also has problems. The process of manufacturing a semiconductor device includes a process of injecting impurities into the channel directly under the gate in a well of a semiconductor substrate. This process is also called channel doping. The content of the channel doping process varies according to the difference in the channel type (p-type / n-type) of the MOSFET and the difference in the gate threshold voltage to be designed. In the process of channel doping, the gate threshold voltage of the MOSFET can be adjusted by adjusting the type, amount, or diffusion state of the impurities to be injected.

[0067] A mask is used in the process of channel doping. The mask has an opening corresponding to the region where impurities are injected. Therefore, to add MVT cells as cells to be used in a digital circuit, a mask for a p-type MOSFET with the threshold voltage MVTP and a mask for an n-type MOSFET with the threshold voltage MVTN are newly required. That is, when adding MVT cells as cells to be used in a digital circuit, the number of masks for manufacturing increases, the number of manufacturing steps also increases, and the financial and time costs increase.

[0068] The present inventor has designed a method capable of further reducing power consumption, while suppressing costs and ensuring the required operating speed in a semiconductor device including a digital circuit.

[0069] (First Embodiment)

[0070] The first embodiment is a semiconductor device including a digital circuit and a method for designing and manufacturing the semiconductor device. In the first embodiment, in the semiconductor device, in addition to HVT cells and LVT cells, a cell having characteristics between the HVT cell and the LVT cell and a configuration different from that of the MVT cell is used. Note that the HVT cell is an example of the "first cell" in the present application, and the LVT cell is an example of the "second cell" in the present application. In addition, the cell having characteristics between the HVT cell and the LVT cell and a configuration different from that of the MVT cell is an example of the "third cell" in the present application. Further, in each of the following embodiments, it is assumed that the thickness of the gate layer of the MOSFET constituting the cell is constant, and the size of the cell is proportional to the size of the well or the like occupying the substrate surface of the semiconductor substrate.

[0071] The semiconductor device 100 according to the first embodiment is, for example, an integrated circuit and is a so-called semiconductor chip. As Figure 6 illustrated, the semiconductor device 100 includes a digital circuit portion 101 and non-digital circuit portions 102 and 103. The non-digital circuit portion 102 is, for example, an analog circuit portion. The non-digital circuit portion 103 is, for example, an input / output (I / O) circuit portion.

[0072] Three types of cells are used in the digital circuit portion 101. That is, in addition to the HVT cell as the first cell and the LVT cell as the second cell used in the related art, a third cell is provided. Then, the digital circuit portion 101 is designed by combining the three types of cells.

[0073] The third cell includes a p-type MOSFET connected to a first potential and an n-type MOSFET connected to a second potential. The second potential is lower than the first potential. The threshold voltage Vt of the p-type MOSFET constituting the third cell is the threshold voltage LVTP, which is the same as the threshold voltage of the p-type MOSFET constituting the LVT cell. The threshold voltage Vt of the n-type MOSFET constituting the third cell is the threshold voltage HVTN, which is the same as the threshold voltage of the n-type MOSFET constituting the HVT cell. That is, the third cell is characterized in that the threshold voltage of the p-type MOSFET is set to the relatively low threshold voltage LVTP for the p-type, and the threshold voltage of the n-type MOSFET is set to the relatively high threshold voltage HVTN for the n-type.

[0074] Here, the threshold voltage HVTP is an example of the "first threshold voltage" in the present application, and the threshold voltage HVTN is an example of the "second threshold voltage" in the present application. Further, the threshold voltage LVTP is an example of the "third threshold voltage" in the present application, and the threshold voltage LVTN is an example of the "fourth threshold voltage" in the present application.

[0075] Generally, the leakage current of an LVT cell composed of MOSFETs having a threshold voltage Vt with a low absolute value corresponds to ten times and several to several tens of times the leakage current of an HVT cell composed of MOSFETs having a threshold voltage Vt with a high absolute value. Further, due to the physical properties of silicon, the on-current of an n-type MOSFET corresponds to approximately several times the on-current of a p-type MOSFET. Here, consider comparing the rise time of the output of a p-type MOSFET with the fall time of the output of an n-type MOSFET at the same on-current (load). Here, the rise time of the p-type MOSFET is longer than the fall time of the n-type MOSFET. The operating speed of a cell can be approximately considered as the reciprocal of the time required for switching composed of the rise and fall of the output of the cell.

[0076] Therefore, the threshold voltage Vt of the n-type MOSFET is set to the threshold voltage HVTN with a relatively high absolute value for the n-type, and the threshold voltage Vt of the p-type MOSFET is set to the threshold voltage LVTP with a relatively low absolute value for the p-type. Accordingly, the on-current of the p-type MOSFET increases and the rise time is shortened. With this design, the leakage current can be reduced and the operating speed in the cell can be increased.

[0077] Figure 7 A configuration example of a NOT (INV) type cell 31 as an example of a logic gate is illustrated. In the NOT type cell 31, a p-type MOSFET 311 connected to the line Vdd and an n-type MOSFET 312 connected to the line Vss (GND) are connected in series. The potential of the line Vdd is a first potential on the high potential side of the power supply, and the potential of the line Vss is a second potential on the low potential side of the same power supply. The gate of the p-type MOSFET 311 and the gate of the n-type MOSFET 312 are connected, and the connection point of the gates is the input terminal A. Further, the source of the p-type MOSFET 311 and the drain of the n-type MOSFET 312 are connected, and the connection point of the source and the drain is the output terminal Y.

[0078] In the NOT type cell 31, the p-type MOSFET 311 is a p-type MOSFET having a threshold voltage LVTP (hereinafter also referred to as LVT(p)), and the n-type MOSFET 312 is an n-type MOSFET having a threshold voltage HVTN (hereinafter also referred to as HVT(n)). In this specification, a cell including a p-type MOSFET having a threshold voltage LVTP (i.e., LVT(p)) and an n-type MOSFET having a threshold voltage HVTN (i.e., HVT(n)) is referred to as an LVT(p)&HVT(n) cell.

[0079] Figure 8 is a graph showing the relationship between the drive power and the cell leakage of each cell size of an LVT cell, an HVT cell, an LVT(p)&HVT(n) cell, and an MVT cell according to a standard method for comparison.

[0080] The drive power of a cell is related to the operating speed of the cell. In addition, the cell leakage is related to the power consumption of the cell. That is, the higher the drive power, the higher the operating speed, and the smaller the cell leakage, the smaller the power consumption. As Figure 8 shown, in the relationship between the drive power and the cell leakage of a cell, the newly added LVT(p)&HVT(n) cell in the first embodiment has characteristics between the existing LVT cell and the HVT cell, that is, characteristics close to those of the MVT cell according to the standard method. That is, the LVT(p)&HVT(n) cell can be used instead of the MVT cell.

[0081] That is, in the method of designing a digital circuit according to the first embodiment, among the parts where the operating speed or drive power of the LVT cell is too high but the operating speed or drive power of the HVT cell is insufficient, the LVT(p)&HVT(n) cell is used in the part where the operating speed or drive power between the LVT cell and the HVT cell is sufficient. Therefore, according to the first embodiment, a digital circuit can be provided that reduces the power consumption caused by leakage current while ensuring the required operating speed.

[0082] In addition, in the method of designing a digital circuit according to the first embodiment, as a cell having characteristics between LVT cells and HVT cells, LVT(p)&HVT(n) cells are used instead of MVT cells. Therefore, in the first embodiment, the design models of LVTP and HVTN, which are the existing design models of the gate threshold voltage, can be completely used to form cells, and thus there is no need to newly develop a new design model of the gate threshold voltage. In addition, in the first embodiment, there is no need to newly develop a new design model of the gate threshold voltage. Therefore, during the process of manufacturing a digital circuit, no new mask is required, and for the process of injecting impurities into the channels or wells of a semiconductor substrate for gate threshold voltage control, using the existing mask is sufficient.

[0083] In addition, according to the first embodiment, there is no need to newly develop a design model of the gate threshold voltage. In addition, there is no need to fabricate a new mask as the mask used in the process of injecting impurities for gate threshold voltage control. Moreover, the process of using a new mask is also unnecessary. That is, according to the first embodiment, a semiconductor device can be realized that improves the balance between the operation speed and power consumption while suppressing the financial and time costs.

[0084] <Estimation of the effect of reducing cell leakage by cell replacement>

[0085] Figure 9 A table is illustrated that shows the relationship between the usage rate of cell types in a digital circuit and cell leakage. Figure 9 The left table shows the relationship between the usage rates of HVT cells and LVT cells and cell leakage (related art example). Figure 9 The right table shows the relationship between the usage rates of HVT cells, LVT(p)&HVT(n) cells, and LVT cells in a digital circuit and cell leakage. Here, it is assumed that the cell sizes are all the same. In addition, in the table, cell leakage is indicated as the cell leakage rate, which is the ratio when the cell leakage when all cells are HVT cells is set to 1.

[0086] For example, as Figure 9As shown, in the related art example, when the usage rates of the HVT cells and the LVT cells are 0.5:0.5, the cell leakage rate is 12.4. On the other hand, in the example of the first embodiment, when the usage rates of the HVT cells, the LVT(p)&HVT(n) cells, and the LVT cells are 0.5:0.5:0.0, the cell leakage rate is 4.4. Further, in the example of the first embodiment, when the usage rates of the HVT cells, the LVT(p)&HVT(n) cells, and the LVT cells are 0.5:0.4:0.1, the cell leakage rate is 6.0. Therefore, in the case of a digital circuit where the usage rates of the HVT cells and the LVT cells are 0.5:0.5, by replacing all or approximately 80% of the LVT cells with LVT(p)&HVT(n) cells, the cell leakage can be reduced to approximately 1 / 2 times to approximately 1 / 3 times.

[0087] <Relationship between driving power and leakage current of cells>

[0088] Figure 10 is a graph showing the relationship between the driving power of the LVT cells, the HVT cells, the MVT cells, and the LVT(p)&HVT(n) cells and the cell leakage. Further, in Figure 10 the graph shown, for each cell size, a curve (close to a straight line) is drawn with a dashed line, where the curve represents the characteristics when the threshold voltages Vt of the p-type MOSFET and the n-type MOSFET are simultaneously adjusted in the same positive or negative direction in cells of the same size. Note that in Figure 10 the graph shown, "X160", "X240", and "X320" represent the cell sizes, and the larger the number, the larger the cell size. The physical heights of the MOSFETs constituting the cells are the same, and the occupied areas of the cells are different.

[0089] As Figure 10 shown, the ratio of cell leakage to driving power in the HVT cells is relatively small. The ratio of cell leakage to driving power in the LVT cells is relatively large. The ratio of cell leakage to driving power in the MVT cells is characterized by being between the HVT cells and the LVT cells. The ratio of cell leakage to driving power in the LVT(p)&HVT(n) cells is slightly larger than that of the MVT cells and has the characteristic of being close to the ratio of the MVT cells.

[0090] Here, in Figure 10In the illustrated graph, the curve corresponding to the LVT(p)&HVT(n) cell is compared with each of the curves corresponding to the HVT cell, LVT cell, and MVT cell. Then, it can be seen that the curve corresponding to the LVT(p)&HVT(n) cell is generally shifted to the right from the other curves. This means that the cell leakage in the LVT(p)&HVT(n) cell is less than the drive power compared to the other cells. That is, when cells of the same size and the same drive power are compared with each other, it can be seen that the cell leakage of the LVT(p)&HVT(n) cell is less than the cell leakage of the other cells, and the performance of the LVT(p)&HVT(n) cell is higher than that of the MVT cell.

[0091] <Relationship between the operating speed and leakage current of the cell>

[0092] Figure 11 is a graph showing the relationship between the operating speed of each cell and the cell leakage. In Figure 11 In the illustrated graph, graph P1 indicates the relationship between the operating speed and the cell leakage in the HVT cell. Graph P2 indicates the relationship between the operating speed and the cell leakage in the LVT cell. In addition, graph P3 indicates the relationship between the operating speed and the cell leakage in the LVT(p)&HVT(n) cell. In addition, in Figure 11 In the illustrated graph, for a cell formed by simultaneously changing the threshold voltages Vt of the n-type FET and p-type FET, a curve (close to a straight line) L1 indicating the relationship between the operating speed and the cell leakage is drawn with a dashed line. In Figure 11 In the illustrated graph, the area (diagonal lower right) below the dashed line L1 indicates the area for further improving the balance between the operating speed and the cell leakage.

[0093] In Figure 11 In the illustrated graph, graph P3 corresponding to the LVT(p)&HVT(n) cell is located below the dashed line L1. Therefore, compared with the LVT cell and the HVT cell, the LVT(p)&HVT(n) cell not only has characteristics between the LVT cell and the HVT cell, but also has an improved balance between the operating speed and the cell leakage. This is also a characteristic of the LVT cell and the HVT cell different from the characteristics of the MVT cell.

[0094] <Method for manufacturing a cell>

[0095] As Figure 12As illustrated, in step (process) S0, a process of preparing a semiconductor substrate is performed. In step S1, a process of forming a well is performed. Note that details of the process of forming a well in step S1 will be described later. In step S2, a process of forming a trench is performed. In step S3, a process of filling the trench is performed. In step S4, a process of forming a gate is performed. Note that details of the process of forming a gate in step S4 will be described later.

[0096] In step S5, a process of forming a lightly doped drain (LDD) is performed. In step S6, a process of forming sidewall spacers is performed. In step S7, a process of forming source and drain is performed. In step S8, a process of forming an interlayer film and contacts is performed. In step S9, a process of forming metal wirings is performed. In step S10, a process of wiring multi-layer metals and a process of forming a passivation film are performed.

[0097] Note that, as Figure 12 illustrated, performing the processes of steps S1 to S7 above is substantially equivalent to performing the processes of steps T1 to T6 below. Step T1 is a process of forming the first p-type MOSFET of the HVT cell. Step T2 is a process of forming the first n-type MOSFET of the HVT cell. Step T3 is a process of forming the second p-type MOSFET of the HVT cell. Step T4 is a process of forming the second n-type MOSFET of the HVT cell. Step T5 is a process of forming the third p-type MOSFET of the LVT(p)&HVT(n) cell. Step T6 is a process of forming the third n-type MOSFET of the LVT(p)&HVT(n) cell.

[0098] As Figure 13 illustrated, in step S11, a first p-type well, a second p-type well, and a third p-type well are formed by implanting p-type impurities into the semiconductor substrate 10. In addition, in step S12, a first n-type well, a second n-type well, and a third n-type well are formed by implanting n-type impurities into the semiconductor substrate 10.

[0099] Here, the first p-type well is the well of the n-type MOSFET that constitutes the HVT cell. The second p-type well is the well of the n-type MOSFET that constitutes the HVT cell. The third p-type well is the well of the n-type MOSFET that constitutes the LVT(p)&HVT(n) cell. In addition, the first n-type well is the well of the p-type MOSFET that constitutes the HVT cell. The second n-type well is the well of the p-type MOSFET that constitutes the HVT cell. The third n-type well is the well of the p-type MOSFET that constitutes the LVT(p)&HVT(n) cell.

[0100] Next, as Figure 14As shown, in step S41, an element isolation structure is formed. First, a trench is formed in the semiconductor substrate, and an oxide film is formed on the semiconductor substrate to fill the trench. Thereafter, the oxide film formed outside the trench is removed to form the element isolation structure.

[0101] In step S42, a process of forming a gate insulating film is performed. For example, a gate insulating film (oxide film) is formed by oxidizing the semiconductor substrate. Thus, the first p-type MOSFET and the first n-type MOSFET constituting the HVT unit 11 as the first unit have a first gate insulating film. In addition, the second p-type MOSFET and the second n-type MOSFET constituting the LVT unit 12 as the second unit have a second gate insulating film. In addition, the third p-type MOSFET and the third n-type MOSFET constituting the LVT(p)&HVT(n) unit 13 as the third unit have a third gate insulating film. Additionally, the thickness of the first gate insulating film, the thickness of the second gate insulating film, and the thickness of the third gate insulating film are the same. However, stating that the thicknesses of the gate insulating films are the same does not mean that the thicknesses are exactly the same, but rather that they are the same in design, thus allowing for manufacturing errors, etc.

[0102] In step S43, a process of injecting impurities for threshold voltage adjustment is performed. Specifically, three types of units are laid out on the semiconductor substrate. For each individual type of unit, impurities are injected into the channel directly under the gate located in the well to adjust the threshold voltage of each of the p-type MOSFET and the n-type MOSFET constituting the unit. The threshold voltage is adjusted by changing the amount of impurities to be injected, the concentration of impurities in the channel, the degree of diffusion, etc. p-type impurities are injected into the channel in the p-type well of the n-type MOSFET. n-type impurities are injected into the channel in the n-type well of the p-type MOSFET. Examples of n-type impurities include phosphorus (P), arsenic (As), antimony (Sb), etc. Examples of p-type impurities include boron (B), indium (In), aluminum (Al), etc.

[0103] In this example, by performing the process of injecting impurities for threshold voltage adjustment, each MOSFET of each unit has a channel with an impurity concentration as described below.

[0104] The first p-type MOSFET constituting the HVT unit 11 as the first unit has a channel with a first impurity concentration corresponding to the threshold voltage HVTP. In addition, the first n-type MOSFET constituting the HVT unit 11 as the first unit has a channel with a second impurity concentration corresponding to the threshold voltage HVTN.

[0105] The second p-type MOSFET forming the LVT cell 12 as the second unit has a channel having a third impurity concentration corresponding to the threshold voltage LVTP. Further, the second n-type MOSFET forming the LVT cell 12 as the second unit has a channel having a fourth impurity concentration corresponding to the threshold voltage LVTN.

[0106] The third p-type MOSFET forming the LVT(p)&HVT(n) cell 13 as the third unit has a channel having a third impurity concentration corresponding to the threshold voltage LVTP. Further, the third n-type MOSFET forming the LVT(p)&HVT(n) cell 13 as the third unit has a channel having a second impurity concentration corresponding to the threshold voltage HVTN.

[0107] Note that when the impurity concentration in the channel of a MOSFET increases, the absolute value of the threshold voltage of the MOSFET increases. Conversely, when the impurity concentration in the channel of a MOSFET decreases, the absolute value of the threshold voltage of the MOSFET decreases.

[0108] Therefore, in a p-type MOSFET, the impurity concentration in the channel of the first n-type well corresponding to the threshold voltage HVTP is higher than the impurity concentration in the channel of the second n-type well corresponding to the threshold voltage LVTP and the impurity concentration in the channel of the third n-type well. Further, in an n-type MOSFET, the impurity concentration in the channel of the first p-type well corresponding to the threshold voltage HVTN and the impurity concentration in the channel of the third p-type well are higher than the impurity concentration in the channel of the second p-type well corresponding to the threshold voltage LVTN.

[0109] In an n-type MOSFET, the impurity concentration in the channel of the first p-type well corresponding to the threshold voltage HVTN is the same as the impurity concentration in the channel of the third p-type well corresponding to the threshold voltage HVTN. Further, in a p-type MOSFET, the impurity concentration in the channel of the second n-type well corresponding to the threshold voltage LVTP is the same as the impurity concentration in the channel of the third n-type well corresponding to the threshold voltage LVTP. Note that the fact that the impurity concentrations are the same means that the designed concentrations are the same, and an error is allowed in actual manufacturing.

[0110] Here, for example, as Figure 15As shown, consider a design in which HVT cells 11, LVT cells 12, and LVT(p)&HVT(n) cells 13 are arranged on a semiconductor substrate 10. The HVT cell 11 includes a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HVTN. The LVT cell 12 includes a p-type MOSFET having a threshold voltage LVTP and an n-type MOSFET having a threshold voltage LVTN. In addition, the LVT(p)&HVT(n) cell 13 includes a p-type MOSFET having a threshold voltage LVTP and an n-type MOSFET having a threshold voltage HVTN.

[0111] The type of impurity to be implanted into the p-type MOSFET is different from the type of impurity to be implanted into the n-type MOSFET. That is, the implantation conditions of the impurities corresponding to the threshold voltages HVTP and LVTP are different from the implantation conditions of the impurities corresponding to the threshold voltages HVTN and LVTN. In addition, even when the same p-type MOSFET or the same n-type MOSFET is compared with each other, the magnitude of the absolute value of the threshold voltage to be adjusted may be different, and thus the implantation amount or diffusion state of the impurities is different, and the implantation conditions of the impurities are different. Therefore, in step S43, four types of masks are used.

[0112] Specifically, as Figure 16 shown, the above four types of masks include a mask 111 for the threshold voltage HVTP, a mask 112 for the threshold voltage HVTN, a mask 113 for the threshold voltage LVTP, and a mask 114 for the threshold voltage LVTN.

[0113] As Figure 16 shown, the mask 111 for the threshold voltage HVTP covers the wells of the MOSFETs having the threshold voltages HVTN, LVTP, and LVTN, and has an opening 111h to expose the channel of the p-type MOSFET having the threshold voltage HVTP. Specifically, the mask 111 for the threshold voltage HVTP covers the wells of the n-type MOSFET of the HVT cell 11, the p-type MOSFET and n-type MOSFET of the LVT cell 12, and the p-type MOSFET and n-type MOSFET of the LVT(p)&HVT(n) cell 13, and is formed to expose the channel of the p-type MOSFET of the HVT cell 11.

[0114] As Figure 16As illustrated, mask 112 for threshold voltage HVTN covers the wells of MOSFETs with threshold voltages HVTP, LVTP, and LVTN, and has an opening 112h to expose the channels of n-type MOSFETs with threshold voltage HVTN. Specifically, mask 112 for threshold voltage HVTN covers the wells of the p-type MOSFETs of HVT cell 11, the p-type MOSFETs and n-type MOSFETs of LVT cell 12, and the p-type MOSFETs of LVT(p&HVT(n) cell 13, and is formed to expose the channels of the n-type MOSFETs of HVT cell 11 and LVT(p)&HVT(n) cell 13.

[0115] As Figure 16 As illustrated, mask 113 for threshold voltage LVTP covers the wells of MOSFETs with threshold voltages HVTP, HVTN, and LVTN, and has an opening 113h to expose the channels of p-type MOSFETs with threshold voltage LVTP. Specifically, mask 113 for threshold voltage LVTP covers the wells of the p-type MOSFETs and n-type MOSFETs of HVT cell 11, the n-type MOSFETs of LVT cell 12, and the n-type MOSFETs of LVT(p&HVT(n) cell 13, and is formed to expose the channels of the p-type MOSFETs of LVT cell 12 and LVT(p)&HVT(n) cell 13.

[0116] As Figure 16 As illustrated, mask 114 for threshold voltage LVTN covers the wells of MOSFETs with threshold voltages HVTP, HVTN, and LVTP, and has an opening 114h to expose the channels of n-type MOSFETs with threshold voltage LVTN. Specifically, mask 114 for threshold voltage LVTN covers the wells of the p-type MOSFETs and n-type MOSFETs of HVT cell 11, the p-type MOSFETs of LVT cell 12, and the p-type MOSFETs and n-type MOSFETs of LVT(p&HVT(n) cell 13, and is formed to expose the channels of the n-type MOSFETs of LVT cell 12.

[0117] As Figure 17As shown in the figure, first, in step S431, a mask 111 for the threshold voltage HVTP is formed (set) on the semiconductor substrate 10. Thereafter, in step S432, a process of implanting n-type impurities for the threshold voltage HVTP into the channel of the n-type well corresponding to the threshold voltage HVTP in the semiconductor substrate 10 is performed using the mask 111 for the threshold voltage HVTP. Here, the "mask for the threshold voltage HVTP" is an example of the "first mask film" in the present application. In addition, the "n-type well corresponding to the threshold voltage HVTP" is an example of the "first n-type well" in the present application.

[0118] Next, in step S433, a mask 112 for the threshold voltage HVTN is formed (set) on the semiconductor substrate 10. Thereafter, in step S434, a process of implanting p-type impurities for the threshold voltage HVTN into the channel of the p-type well corresponding to the threshold voltage HVTN in the semiconductor substrate 10 is performed using the mask 112 for the threshold voltage HVTN. Here, the "mask for the threshold voltage HVTN" is an example of the "second mask film" in the present application. In addition, the "p-type well corresponding to the threshold voltage HVTN" is an example of the "first p-type well" and an example of the "third p-type well" in the present application.

[0119] Next, in step S435, a mask 113 for the threshold voltage LVTP is formed (set) on the semiconductor substrate 10. Thereafter, in step S436, a process of implanting n-type impurities for the threshold voltage LVTP into the channel of the n-type well corresponding to the threshold voltage LVTP in the semiconductor substrate 10 is performed using the mask 113 for the threshold voltage LVTP. Here, the "mask for the threshold voltage LVTP" is an example of the "third mask film" in the present application. In addition, the "n-type well corresponding to the threshold voltage LVTP" is an example of the "second n-type well" and an example of the "third n-type well" in the present application.

[0120] Next, in step S437, a mask 114 for the threshold voltage LVTN is formed (set) on the semiconductor substrate 10. Thereafter, in step S438, a process of implanting p-type impurities for the threshold voltage LVTN into the channel of the p-type well corresponding to the threshold voltage LVTN in the semiconductor substrate 10 is performed using the mask 114 for the threshold voltage LVTN. Here, the "mask for the threshold voltage LVTN" is an example of the "fourth mask film" in the present application. In addition, the "p-type well corresponding to the threshold voltage LVTN" is an example of the "second p-type well" in the present application.

[0121] Here, step S431 and step S432 executed after step S431 are defined as process A. Step S433 and step S434 executed after step S433 are defined as process B. Step S435 and step S436 executed after step S435 are defined as process C. In addition, step S437 and step S438 executed after step S437 are defined as process D. As described above, an example of executing process A, process B, process C, and process D in this order has been described, but the order of executing processes A to D is not limited to this. For example, process A, process C, process B, and process D can be executed in this order, or process D, process C, process B, and process A can be executed in this order.

[0122] In addition, when a digital circuit using the HVT cell 11, LVT cell 12, and LVT(p)&HVT(n) cell 13 is formed by the method according to the first embodiment, as described above, in order to implant impurities for threshold voltage adjustment, four masks are sufficient as in the related art. On the other hand, when a digital circuit using the HVT cell 11, LVT cell 12, and MVT cell is formed by a standard method, in order to implant impurities for threshold voltage adjustment, two additional masks are required, including a mask for threshold voltage MVTP and a mask for threshold voltage MVTN, and a total of six masks are required.

[0123] <Effect of the First Embodiment>

[0124] According to the first embodiment, by replacing at least a part of the LVT cells with LVT(p)&HVT(n) cells in the digital circuit portion of the semiconductor device, unit leakage, that is, power consumption, can be reduced while ensuring the required operating speed in the digital circuit portion. In addition, according to the first embodiment, the operating speed of the unit can be improved under the condition of the same unit leakage compared with the unit according to the standard method.

[0125] In addition, according to the first embodiment, when forming a semiconductor device including a digital circuit portion, there is no need to add a mask for implanting impurities compared with the standard method. Therefore, the manufacturing cost of the added mask and the process of implanting impurities do not increase, and costs can be suppressed.

[0126] In addition, according to the first embodiment, by only reducing the absolute value of the gate threshold voltage Vt of the p-type MOSFET, the drive power of the unit is improved under the condition of the same off leakage. In addition, as understood from Figure 10 it can be understood that the LVT(p)&HVT(n) cell becomes a cell with lower leakage and higher drive power than the MVT cell. Moreover, as understood from Figure 3 it can be understood that the LVT(p)&HVT(n) cell has the highest drive power ratio to unit leakage in any cell size.

[0127] In addition, according to the first embodiment, three types of cells according to the first embodiment can be selectively used in the digital circuit portion of a semiconductor device including a digital circuit portion and a non-digital circuit portion, depending on the required operating speed or drive power. Therefore, a semiconductor device can be provided that suppresses power consumption while ensuring the required operating speed. Thus, according to the first embodiment, in a semiconductor device including a digital circuit, the balance between the operating speed and power consumption can be improved.

[0128] (Second Embodiment)

[0129] The second embodiment is a modification of the LVT(p)&HVT(n) cell according to the first embodiment. In the second embodiment, the threshold voltage Vt is changed without changing the relative magnitude relationship of the absolute values of the threshold voltages Vt of the p-type MOSFET and the n-type MOSFET that make up the cell.

[0130] Figure 18 The illustrated NOT (INV) type cell 31a represents an HVT(p)&HHVT(n) cell formed by a combination of a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HHVTN. The absolute value of the threshold voltage HHVTN is greater than the absolute value of the threshold voltage HVTN. Compared with the LVT(p)&HVT(n) cell, this HVT(p)&HHVT(n) cell has lower off-leakage and higher operating speed. For example, the HVT(p)&HHVT(n) cell is suitable as a cell to be used in a circuit portion for which the required operating speed is not as high as that of the LVT cell but is insufficient compared with the operating speed of the LVT(p)&HVT(n) cell. "Threshold voltage HHVTN" is an example of "the fifth threshold voltage" in the present application.

[0131] Figure 18 The illustrated NOT (INV) type cell 31b represents an LLVT(p)&LVT(n) cell formed by combining a p-type MOSFET having a threshold voltage LLVTP and an n-type MOSFET having a threshold voltage LVTN. The absolute value of the threshold voltage LVTN is greater than the absolute value of the threshold voltage LLVTN. Compared with the LVT(p)&HVT(n) cell, this LLVT(p)&LVT(n) cell has lower off-leakage and higher operating speed. For example, the LLVT(p)&LVT(n) cell is suitable as a cell to be used in a circuit portion for which the required operating speed is not as high as that of the LVT cell but is insufficient compared with the operating speed of the LVT(p)&HVT(n) cell.

[0132] Figure 19The figure shows a graph in which graph P1 and graph P2 are plotted. Graph P1 shows the relationship between the operating speed and the cell leakage corresponding to the HVT cell, and graph P2 shows the relationship between the operating speed and the cell leakage corresponding to the LVT cell. In addition, in Figure 19 the shown graph, graph P3 is plotted, which shows the relationship between the operating speed and the cell leakage corresponding to the LVT(p)&HVT(n) cell. In addition, in Figure 19 the shown graph, graph P4 and graph P5 are plotted. Graph P4 shows the relationship between the operating speed and the cell leakage corresponding to the HVT(p)&HHVT(n) cell, and graph P5 shows the relationship between the operating speed and the cell leakage corresponding to the LLVT(p)&LVT(n) cell. Additionally, in Figure 19 the shown graph, the curve (close to a straight line) L1 is drawn as a dashed line, which indicates the relationship between the operating speed and the cell leakage in the cell formed by simultaneously changing the threshold voltages Vt of the n-type MOSFET and the p-type MOSFET. In Figure 19 the shown graph, the area (diagonal lower right) below the dashed line L1 indicates the area for further improving the balance between the operating speed and the cell leakage.

[0133] As understood from Figure 19 the shown graph, the HVT(p)&HHVT(n) cell and the LLVT(p)&LVT(n) cell are located below the dashed line L1. Therefore, similar to the LVT(p)&HVT(n) cell, compared with the LVT cell and the HVT cell, the HVT(p)&HHVT(n) cell and the LLVT(p)&LVT(n) cell have an improved balance between the operating speed and the cell leakage. For example, compared with the HVT cell, the HVT(p)&HHVT(n) cell is suitable as a cell to be used in a part where reducing the cell leakage is more important than the cell operating speed. On the other hand, compared with the LVT cell, the LLVT(p)&LVT(n) cell is suitable, for example, as a cell to be used in a part where the cell operating speed is more important than reducing the cell leakage. "Threshold voltage LLVTN" is an example of the "sixth threshold voltage" in this application.

[0134] Note that when manufacturing HVT(p)&HHVT(n) cells in addition to the two types of cells according to the related art or the three types of cells according to the first embodiment, a new mask for HHVT is required (a total of five masks are required). In addition, when newly manufacturing LLVT(p)&LVT(n) cells in addition to the two types of cells according to the related art or the three types of cells according to the first embodiment, a new mask for LLVT is required (a total of five masks are required). However, in either case of HVT(p)&HHVT(n) cells and LLVT(p)&LVT(n) cells, the number of masks increases by one. That is, it is not necessary to add two new masks as in the case of MVT cells (a total of six masks are required).

[0135] (Third Embodiment)

[0136] The third embodiment is the following example, in which among the combinational circuits connected between flip-flop circuits, not only LVT cells but also LVT(p)&HVT(n) cells are used in the combinational circuits that require relatively high-speed operation.

[0137] Generally, various types of time delays occur in combinational circuits. In the related art, it is necessary for the combinational circuits with relatively large delays or those that require short delays among the combinational circuits to use cells with high-speed operation. Therefore, in the related art, in the combinational circuits that require such short delays, it is necessary to use cells with high operating speed but large leakage current. That is, in such circuits, it is necessary to use cells with high drive power. Specifically, among the HVT cell 11 and the LVT cell 12, it is necessary to use the LVT cell 12 with high-speed operation and high drive power.

[0138] On the other hand, in the third embodiment, among the combinational circuits that require such short delays, the LVT(p)&HVT(n) cell 13 with medium-speed operation and medium drive power is used in the combinational circuits where the operation speed and drive power in the LVT(p)&HVT(n) cell 13 are sufficient. Therefore, in the combinational circuit, the leakage current can be suppressed while ensuring the required operation speed. Hereinafter, the third embodiment will be described with reference to the drawings.

[0139] Figure 20 An example of the configuration of a combinational circuit according to the related art is illustrated, and Figure 21 An example of the configuration of a combinational circuit according to the third embodiment is illustrated. Note that in Figure 20 and Figure 21 the flip-flop circuit is represented by "FF".

[0140] As Figure 20 and Figure 21As shown in the figure, each of some circuits 51 included in the digital circuit section 101 includes a first flip-flop circuit FF1, a second flip-flop circuit FF2, a third flip-flop circuit FF3, a first combinational circuit KC1, and a second combinational circuit KC2. The first flip-flop circuit FF1, the second flip-flop circuit FF2, and the third flip-flop circuit FF3 operate in synchronization with the same clock signal CLK. The first combinational circuit KC1 is connected between the first flip-flop circuit FF1 and the second flip-flop circuit FF2. The second combinational circuit KC2 is connected between the second flip-flop circuit FF2 and the third flip-flop circuit FF3.

[0141] Here, for simplicity of description, the time delays caused by the operations of the combinational circuits are represented in three levels: large, medium, and small, and the required operating speeds are represented in three levels: high, medium, and low. The delay caused in the first combinational circuit KC1 is small, and the required operating speed is low. The delay caused in the second combinational circuit KC2 is medium, and the required operating speed is medium. In addition, the operating speeds of the units are represented in three levels: high, medium, and low. Here, the operating speed of the HVT unit 11 is low, the operating speed of the LVT unit 12 is low, and the operating speed of the LVT(p)&HVT(n) unit 13 is medium.

[0142] Figure 20 An example of using the HVT unit 11 and the LVT unit 12 according to the related art in a combinational circuit is shown. In addition, Figure 21 An example of using the HVT unit 11 and the LVT(p)&HVT(n) unit 13 in a combinational circuit is shown.

[0143] In the related art, as Figure 20 shown, the HVT unit 11 with a low operating speed is used in the first combinational circuit KC1 having a small delay and a low required operating speed. In addition, the LVT unit 12 with a high operating speed must be used in the second combinational circuit KC2 having a medium delay and a medium required operating speed.

[0144] On the other hand, in the third embodiment, as Figure 21 shown, the HVT unit 11 with a low operating speed is used in the first combinational circuit KC1 having a small delay and a low required operating speed. At the same time, the LVT(p)&HVT(n) unit 13 with a medium operating speed is used in the second combinational circuit KC2 having a medium delay and a medium required operating speed.

[0145] That is, in the combinational circuit connected between the trigger circuits, the high-speed operating LVT cells 12 are used for the combinational circuit with a relatively large induced time delay (for example, the wiring is physically long or the number of circuits is large). The LVT(p)&HVT(n) cells 13 are used for the combinational circuit with a medium induced delay and a sufficient operating speed of the LVT(p)&HVT(n) cells 13. The low-speed HVT cells 11 are used for the combinational circuit with a small induced delay and an excessive operating speed of the LVT(p)&HVT(n) cells 13.

[0146] As described above, in the third embodiment, in the second combinational circuit KC2 that requires a medium operating speed, the medium-speed and medium-leakage LVT(p)&HVT(n) cells 13 are used instead of the high-speed and large-leakage LVT cells. Therefore, according to the third embodiment, in a digital circuit including trigger circuits and combinational circuits, unit leakage can be reduced while ensuring the required operating speed.

[0147] In the above specific example, the cells are selectively used based on the required operating speed, but the cells can also be selectively used based on the required drive power. For example, the LVT cells 12 with high drive power can be used for the part with high required drive power, the HVT cells 11 with small drive power can be used for the part with small required drive power, and the LVT(p)&HVT(n) cells 13 with medium drive power can be used for the part with medium required drive power.

[0148] (Fourth Embodiment)

[0149] The fourth embodiment is an example of a NAND circuit type cell to be used for a digital circuit part included in a semiconductor device.

[0150] As Figure 22 illustrated, the NAND circuit type cell 41 according to the fourth embodiment includes a plurality of p-type MOSFETs and a plurality of n-type MOSFETs. The plurality of p-type MOSFETs are connected to a line Vdd on the high-potential side of a power supply at a first potential and are connected in parallel. The plurality of n-type MOSFETs are connected to a line Vss(GND) on the low-potential side of a power supply at a second potential and are connected in series. In Figure 22 the example, the NAND circuit type cell 41 has a configuration in which three p-type MOSFETs connected in parallel and three n-type MOSFETs connected in series are connected. That is, the NAND circuit type cell 41 has three input terminals A, B, and C and one output terminal Y.

[0151] The p-type MOSFET forming the NAND circuit type cell 41 has a threshold voltage LVTP. The n-type MOSFET forming the NAND circuit type cell 41 has a threshold voltage HVTN. That is, the NAND circuit type cell 41 is an example of an LVT(p)&HVT(n) cell.

[0152] Here, characteristics related to the on-current in the NAND circuit type cell 41 will be considered. In a NAND circuit, when the number of input terminals increases, both the number of p-type MOSFETs connected in parallel and the number of n-type MOSFETs connected in series increase. Even if the number of p-type MOSFETs connected in parallel increases, the on-current of the entire p-type MOSFETs connected in parallel does not become lower than the on-current of a single-stage p-type MOSFET. On the other hand, when the number of n-type MOSFETs connected in series (i.e., the number of stages of n-type MOSFETs stacked vertically) increases, the internal resistance of the entire n-type MOSFETs connected in series increases, and the on-current of the entire n-type MOSFETs connected in series (i.e., stacked vertically) decreases.

[0153] Therefore, when the number of input terminals of the NAND circuit type cell (i.e., the number of stages of n-type MOSFETs stacked vertically) is less than a certain number, the on-current of the n-type MOSFETs stacked vertically becomes greater than the on-current of a single-stage p-type MOSFET. However, when the number of input terminals (i.e., the number of stages of n-type MOSFETs stacked vertically) becomes a certain number or more, the on-current of the n-type MOSFETs stacked vertically becomes equal to or less than the on-current of a single-stage p-type MOSFET.

[0154] Figure 23 is a graph showing an example of the relationship between the number of stages of n-type MOSFETs stacked vertically in a NAND circuit type cell and the on-current. In Figure 23 the example shown, when the number of stages GateN of the n-type MOSFETs stacked vertically becomes three or more, the on-current Ids of the n-type MOSFETs stacked vertically becomes less than the on-current of a single-stage p-type MOSFET. Then, the operation speed of the NAND circuit type cell 41 is limited by the n-type MOSFETs stacked vertically. Therefore, there is an advantage in terms of the effect of reducing leakage current by applying an HVT(p)&LVT(n) cell instead of an LVT(p)&HVT(n) cell to the NAND circuit type cell 41.

[0155] Figure 24 shows an example of applying an HVT(p)&LVT(n) cell to a NAND circuit type cell. As Figure 24As illustrated, the p-type MOSFET constituting the NAND-type cell 42 has a threshold voltage HVTP. In addition, the n-type MOSFET constituting the NAND-type cell 42 has a threshold voltage LVTN. That is, the NAND-type cell 42 is an example of an HVT(p)&LVT(n) cell.

[0156] As described above, in the NAND circuit-type cell, it is possible to determine whether to apply an LVT(p)&HVT(n) cell or an HVT(p)&LVT(n) cell according to the number of stages of the vertically stacked n-type MOSFETs, which has an advantage in terms of the effect of reducing leakage current.

[0157] In the foregoing, the present invention made by the inventors of the present application has been specifically described based on embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and various modifications and changes can be made within the scope of the present invention. In addition, the semiconductor device according to each embodiment can be applied to any product as long as the product uses a digital circuit. Some of the content described in the above embodiments will be described below.

[0158] [Appendix 1]

[0159] A semiconductor device, comprising:

[0160] A first cell as a logic gate, the first cell comprising:

[0161] A first p-channel MOSFET; and

[0162] A first n-channel MOSFET;

[0163] A second cell as a logic gate, the second cell comprising:

[0164] A second p-channel MOSFET; and

[0165] A second n-channel MOSFET; and

[0166] A third cell as a logic gate, the third cell comprising:

[0167] A third p-channel MOSFET; and

[0168] A third n-channel MOSFET,

[0169] wherein the p-channel MOSFET of the first cell has a first threshold voltage,

[0170] the n-channel MOSFET of the first cell has a second threshold voltage,

[0171] the p-channel MOSFET of the second cell has a third threshold voltage,

[0172] The n-channel MOSFET of the second unit has a fourth threshold voltage,

[0173] The p-channel MOSFET of the third unit has a first threshold voltage,

[0174] The n-channel MOSFET of the third unit has a sixth threshold voltage,

[0175] The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage,

[0176] The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, and

[0177] The absolute value of the sixth threshold voltage is higher than the absolute value of the first threshold voltage.

[0178] [Appendix 2]

[0179] A semiconductor device, comprising:

[0180] A first unit as a logic gate, the first unit including a first p-channel MOSFET and a first n-channel MOSFET;

[0181] A second unit as a logic gate, the second unit including a second p-channel MOSFET and a second n-channel MOSFET; and

[0182] A third unit as a logic gate, the third unit including a third p-channel MOSFET and a third n-channel MOSFET,

[0183] wherein the p-channel MOSFET of the first unit has a first threshold voltage,

[0184] the n-channel MOSFET of the first unit has a second threshold voltage,

[0185] the p-channel MOSFET of the second unit has a third threshold voltage,

[0186] the n-channel MOSFET of the second unit has a fourth threshold voltage,

[0187] the p-channel MOSFET of the third unit has a first threshold voltage, the n-channel MOSFET of the third unit has a fourth threshold voltage, the absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, the absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, and the third unit is a NAND gate having three or more input terminals.

Claims

1. A semiconductor device, comprising: As a first unit of a logic gate, the first unit comprises: A first p-channel MOSFET connected to a first potential; and a first n-channel MOSFET connected to a second potential lower than the first potential; As a second unit of the logic gate, the second unit includes: a second p-channel MOSFET connected to the first potential; and a second n-channel MOSFET connected to the second potential; and a third unit as a logic gate, the third unit comprising: a third p-channel MOSFET connected to the first potential; and A third n-channel MOSFET, connected to the second potential, wherein the first p-channel MOSFET has a first threshold voltage, wherein the first n-channel MOSFET has a second threshold voltage, wherein the second p-channel MOSFET has a third threshold voltage, wherein the second n-channel MOSFET has a fourth threshold voltage, wherein the third p-channel MOSFET has the third threshold voltage, wherein the third n-channel MOSFET has the second threshold voltage, wherein the absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, and The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage.

2. The semiconductor device according to claim 1, wherein the first p-channel MOSFET and the first n-channel MOSFET each have a first gate insulating film, wherein the second p-channel MOSFET and the second n-channel MOSFET each have a second gate insulating film, wherein the third p-channel MOSFET and the third n-channel MOSFET each have a third gate insulating film, and The thickness of the first gate insulating film, the thickness of the second gate insulating film, and the thickness of the third gate insulating film are equal to each other.

3. The semiconductor device according to claim 2, wherein the first p-channel MOSFET has a channel having a first impurity concentration, wherein the first n-channel MOSFET has a channel having a second impurity concentration, wherein the second p-channel MOSFET has a channel having a third impurity concentration, wherein the second n-channel MOSFET has a channel having a fourth impurity concentration, wherein the third p-channel MOSFET has a channel having the third impurity concentration, and The third n-channel MOSFET has a channel having the second impurity concentration.

4. The semiconductor device according to claim 2, wherein the first p-channel MOSFET has a well having a first impurity concentration, wherein the first n-channel MOSFET has a well, the well having a second impurity concentration, wherein the second p-channel MOSFET has a well having a third impurity concentration, wherein the second n-channel MOSFET has a well having a fourth impurity concentration, wherein the third p-channel MOSFET has a well having the third impurity concentration, and The third n-channel MOSFET has a well having the second impurity concentration.

5. The semiconductor device according to claim 1, further comprising: The first flip-flop circuit and the second flip-flop circuit operate in synchronization with a same clock signal; as well as a combinational circuit connected between the first flip-flop circuit and the second flip-flop circuit, Wherein the third unit is included in the combinational circuit.

6. A semiconductor device comprising: A first unit as a logic gate, wherein the first unit includes a first p-channel MOSFET and a first n-channel MOSFET; a second unit as a logic gate, the second unit comprising a second p-channel MOSFET and a second n-channel MOSFET; and As a third unit of the logic gate, the third unit includes a third p-channel MOSFET and a third n-channel MOSFET, wherein the p-channel MOSFET of the first cell has a first threshold voltage, wherein the n-channel MOSFET of the first cell has a second threshold voltage, wherein the p-channel MOSFET of the second cell has a third threshold voltage, wherein the n-channel MOSFET of the second cell has a fourth threshold voltage, wherein the p-channel MOSFET of the third cell has a fifth threshold voltage, wherein the n-channel MOSFET of the third cell has the fourth threshold voltage, wherein the absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, wherein the absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, and The absolute value of the fifth threshold voltage is lower than the absolute value of the third threshold voltage.

7. The semiconductor device according to claim 1, further comprising: Digital circuit part and non-digital circuit part, The digital circuit portion includes the first unit, the second unit and the third unit.

8. A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor substrate; as well as (b) forming a first p-channel MOSFET, a first n-channel MOSFET, a second p-channel MOSFET, a second n-channel MOSFET, a third p-channel MOSFET and a third n-channel MOSFET on the semiconductor substrate, wherein the first p-channel MOSFET and the first n-channel MOSFET configure a first unit, wherein the second p-channel MOSFET and the second n-channel MOSFET configure a second unit, wherein the third p-channel MOSFET and the third n-channel MOSFET configure a third unit, wherein the first p-channel MOSFET has a first threshold voltage and is connected to a first potential, wherein the first n-channel MOSFET has a second threshold voltage and is connected to a second potential lower than the first potential, wherein the second p-channel MOSFET has a third threshold voltage and is connected to the first potential, wherein the second n-channel MOSFET has a fourth threshold voltage and is connected to the second potential, wherein the third p-channel MOSFET has the third threshold voltage and is connected to the first potential, wherein the third n-channel MOSFET has the second threshold voltage and is connected to the second potential, wherein the absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, and The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage.

9. The method according to claim 8, wherein the first p-channel MOSFET and the first n-channel MOSFET each have a first gate insulating film, wherein the second p-channel MOSFET and the second n-channel MOSFET each have a second gate insulating film, wherein the third p-channel MOSFET and the third n-channel MOSFET each have a third gate insulating film, and The method further comprises: (c) after (a), forming an insulating film on the semiconductor substrate; as well as (d) The insulating film is processed to form the first gate insulating film, the second gate insulating film, and the third gate insulating film.

10. The method according to claim 9, further comprising: (e) after (a), forming a first p-type well, a second p-type well, and a third p-type well by implanting p-type impurities into the semiconductor substrate; (f) forming a first n-type well, a second n-type well, and a third n-type well by implanting n-type impurities into the semiconductor substrate; (g) forming a first mask film on the semiconductor substrate, the first mask film covering the second n-type well, the third n-type well, the first p-type well, the second p-type well and the third p-type well, and exposing a channel of the first n-type well; (h) after (g), implanting n-type impurities into the channel of the first n-type well by using the first mask film; (i) forming a second mask film on the semiconductor substrate, the second mask film covering the first n-type well, the second n-type well, the third n-type well and the second p-type well, and exposing a channel of the first p-type well and a channel of the third p-type well; (j) after (i), implanting p-type impurities into the channel of the first p-type well and the channel of the third p-type well by using the second mask film; (k) forming a third mask film on the semiconductor substrate, the third mask film covering the first n-type well, the first p-type well, the second p-type well, and the third p-type well, and exposing a channel of the second n-type well and a channel of the third n-type well; (l) after (k), implanting n-type impurities into the channel of the second n-type well and the channel of the third n-type well by using the third mask film; (m) forming a fourth mask film on the semiconductor substrate, the fourth mask film covering the first n-type well, the second n-type well, the third n-type well, the first p-type well and the third p-type well, and exposing a channel of the second p-type well; as well as (n) after (m), implanting p-type impurities into the channel of the second p-type well using the fourth mask film, wherein the first p-channel MOSFET has the first n-type well, wherein the first n-channel MOSFET has the first p-type well, wherein the second p-channel MOSFET has the second n-type well, wherein the second n-channel MOSFET has the second p-type well, wherein the third p-channel MOSFET has the third n-type well, and The third n-channel MOSFET has the third p-type well.

11. The method according to claim 10, wherein the impurity concentration in the channel of the first n-type well is higher than the impurity concentration in the channel of the second n-type well and the impurity concentration in the channel of the third n-type well, and The impurity concentration in the channel of the first p-type well and the impurity concentration in the channel of the third p-type well are higher than the impurity concentration in the channel of the second p-type well.

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