Current enhancement type multi-channel isolation AlGaN / GaN CAVET device

Abstract

The invention relates to a current enhancement type multi-channel isolation AlGaN / GaN CAVET device, and belongs to the technical field of microelectronics. The device comprises a drain electrode, a substrate, a GaN buffer layer, a current blocking layer, a current isolation layer, barrier layers and channel layers, the barrier layers and the channel layers are alternately stacked above the current blocking layer and the current isolation layer, and the channel isolation layer is embedded between the adjacent barrier layer and channel layer and used for isolating current. According to the invention, the design of taking an aperture as a current channel is abandoned, and the hole concentration at the current blocking layer and the side wall of the gate is regulated and controlled by adopting the gate voltage, so that the opening and closing of the device are realized. In the multi-channel design, the problem that electron gas among multiple channels in a vertical structure is mutually exhausted is solved by introducing the isolation layer, and meanwhile, the isolation layer is also embedded in the current blocking layer, so that the exhaustion effect of P-GaN on the channels is effectively prevented, and the output capability of the device is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and relates to a current-enhanced multi-channel isolated AlGaN / GaN CAVET device. Background Art

[0002] Gallium nitride (GaN), as a representative of the third-generation semiconductor materials, has become an ideal choice for high-voltage and high-frequency power devices due to its wide bandgap (3.4 eV), high critical breakdown field strength (3.3 MV / cm), high electron saturation drift velocity (2.5×10 7 cm / s), and excellent radiation resistance. Most of the existing literature research objects are lateral structure GaN HEMT devices, and the related technologies have developed relatively maturely. Although the lateral devices have made great progress, most of the lateral HEMTs are applied in the range of 1KW to 3KW, and in the field of high voltage and high current, they are mainly vertical structure devices. Compared with the vertical structure, the lateral devices have several relatively serious defects. For example, in the lateral devices, the high electric field region is located at the gate edge near the drain side. Since the high electric field injects electrons into the traps existing on the surface, current collapse occurs, which further limits the application of the lateral devices in the high-voltage field. At the same time, the lateral GaN HEMT devices mainly rely on the active region between the gate and the drain to withstand the breakdown voltage. To obtain a large breakdown voltage, a large gate-drain spacing needs to be designed, which increases the area required for the chip, does not meet the demand for miniaturization, and is not conducive to reducing the manufacturing cost. While the breakdown voltage region of the vertical devices is distributed in the longitudinal drift region, and the breakdown voltage of the device can be significantly improved without increasing the lateral size of the device.

[0003] Vertical structure devices (such as CAVET, MOSFET) withstand high voltage through the longitudinal drift region and can achieve kilovolt-level breakdown voltage at a relatively small lateral size. However, when the existing vertical GaN devices achieve high breakdown voltage, it is often difficult to achieve high current density at the same time. Among them, the thickness and doping concentration of the P-GaN layer directly affect the blocking ability and on-resistance (R on ). Research shows that when the thickness of the P-GaN increases from 1μm to 3μm, the breakdown voltage (V br ) can be increased from 800V to 1.2kV, but R on increases by about 40% at the same time. To increase the current density, researchers have tried to introduce a multi-channel structure. However, the vertically stacked AlGaN / GaN heterojunctions will form two-dimensional hole gas (2DHG), which will recombine and deplete with the channel electron gas (2DEG), resulting in a decrease in the effective carrier concentration. Simulations show that the electron concentration of the double-channel structure decreases by about 25% compared with that of the single-channel structure, seriously weakening the advantages of the multi-channel design.

[0004] According to the above, it is urgent to develop an innovative structure that can significantly enhance the output current capacity of the device while maintaining high breakdown voltage performance, so as to expand the application scope of GaN vertical devices in high-power application fields. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a current-enhanced multi-channel isolated AlGaN / GaN CAVET device. By designing an isolated multi-channel structure, the recombination and depletion of the electron-hole gas generated by the AlGaN / GaN heterojunction and the channel electrons are avoided, so as to improve the output current capacity of the device while maintaining the high breakdown voltage performance of the device.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A current-enhanced multi-channel isolated AlGaN / GaN CAVET device, the device comprising:

[0008] A substrate;

[0009] A GaN buffer layer located on the surface of the substrate;

[0010] A current blocking layer located on the surface of the GaN buffer layer;

[0011] A current isolation structure located on the surface of the GaN buffer layer, the current isolation structure separating the current blocking layer into two parts;

[0012] At least three stacked barrier / channel structures located on the surfaces of the current blocking layer and the current isolation structure;

[0013] A channel isolation layer located between each barrier / channel structure;

[0014] A first source electrode located on the surface of the uppermost barrier / channel structure;

[0015] A second source electrode perpendicular to the stacking direction of the barrier / channel structures and used to connect the channel layers in each barrier / channel structure, the upper surface of the second source electrode is connected to the first source electrode, and the lower surface is in contact with the surface of the channel layer in the lowermost barrier / channel structure;

[0016] A passivation layer located on the surface of the uppermost barrier / channel structure and distributed on both sides of the first source electrode;

[0017] Gate electrodes located on both sides of the device; and

[0018] Located on the surface of the substrate on the side away from the GaN buffer layer.

[0019] Further, the current isolation structure includes a first current isolation layer and second current isolation layers distributed on both sides of the first current isolation layer.

[0020] Furthermore, the barrier / channel structure includes a channel layer and a barrier layer, where the barrier layer is located on the upper surface of the channel layer.

[0021] Furthermore, the gates located on both sides of the device are insulated from other parts of the device by an HfO2 insulating gate.

[0022] Furthermore, there is a spacing between the second current isolation layer and the HfO2 insulating gate, and the spacing is 100 - 500 nm.

[0023] Furthermore, there is a spacing between the channel isolation layer located between the barrier / channel structures and the HfO2 insulating gate, and the spacing is 100 - 500 nm.

[0024] Furthermore, the channel layers in each barrier / channel structure have the same thickness, and the barrier layers in each barrier / channel structure have the same thickness.

[0025] The beneficial effects of the present invention are as follows: The present invention breaks through the design of using the aperture as the current channel in the traditional structure, and uses the gate voltage to regulate the hole concentration at the current blocking layer and the gate sidewall, thereby realizing the opening and closing of the device and effectively reducing the leakage current. In the multi-channel design, the present invention uses an SiO2-based isolation layer to isolate the AlGaN barrier layer and the GaN channel layer, avoiding the recombination and depletion of the electron-hole gas generated by the AlGaN / GaN heterojunction and the channel electrons, so that the multi-channel structure can fully play its role. At the same time, an SiO2 current isolation layer is embedded in the P-GaN current blocking layer to prevent the depletion of the P-GaN on the channel electrons. Based on this, the CAVET device proposed by the present invention can maintain high breakdown voltage performance while significantly improving the device's output current capacity.

[0026] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the following specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0028] Figure 1 is a schematic cross-sectional view of the structure of a current-enhanced multi-channel isolated AlGaN / GaN CAVET device provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic cross-sectional view of the basic structure;

[0030] Figure 3 This is a comparison graph of the transfer characteristic curve and transconductance characteristic curve of the device of the present invention and the basic structure;

[0031] Figure 4 is V G = 10V, V D = 6V, a comparison graph of the cross-sectional distribution of channel electron concentration of two structures with and without inserting a SiO2 current isolation layer in the P-GaN current blocking layer of a traditional CAVET device, Figure 4 (a) Without inserting a SiO2 current isolation layer, Figure 4 (b) With inserting a SiO2 current isolation layer;

[0032] Figure 5 is V G = 10V, V D = 6V, a comparison graph of the cross-sectional distribution of electron concentration of three structures: a double-channel structure without a channel isolation layer, a double-channel structure with a channel isolation layer, and a triple-channel structure with a channel isolation layer (i.e., the exemplary structure of the present invention), Figure 5 (a) A double-channel structure without a channel isolation layer, Figure 5 (b) A double-channel structure with a channel isolation layer, Figure 5 (c) A triple-channel structure with a channel isolation layer;

[0033] Figure 6 This is a comparison graph of the output characteristic curves of the present invention and the basic structure.

[0034] Reference numerals: 101 - drain, 102 - substrate, 103 - GaN buffer layer, 104 - HfO2 insulating gate, 105 - gate, 106 - first source, 107 - passivation layer, 108 - first barrier layer, 109 - first channel layer, 110 - current blocking layer, 111 - first current isolation layer, 112 - second barrier layer, 113 - second channel layer, 114 - third barrier layer, 115 - third channel layer, 116 - second source, 117 - second current isolation layer, 118 - first channel isolation layer, 119 - second channel isolation layer. Detailed implementation manners

[0035] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] Among them, the accompanying drawings are only for illustrative purposes, showing only schematic diagrams rather than actual physical diagrams, and should not be construed as a limitation on the present invention; in order to better illustrate the embodiments of the present invention, some components in the accompanying drawings will be omitted, enlarged or reduced, which does not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0037] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as a limitation on the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0038] As Figure 1 Shown is a current-enhanced multi-channel isolated AlGaN / GaN CAVET device provided by an embodiment of the present invention, which includes a drain 101, a substrate 102, a GaN buffer layer 103, an HfO2 insulating gate 104, a gate 105, a first source 106, a passivation layer 107, a first barrier layer 108, a first channel layer 109, a current blocking layer 110, a first current isolation layer 111, a second barrier layer 112, a second channel layer 113, a third barrier layer 114, a third channel layer 115, a second source 116, a second current isolation layer 117, a first channel isolation layer 118, and a second channel isolation layer 119.

[0039] In this CAVET device, it has an isolated multi-channel structure, including a first channel layer 109, a second channel layer 113, and a third channel layer 115. Each channel is connected by a vertical second source 116, and the first channel layer 109 is isolated from the second barrier layer 112 below it, and the second channel layer 113 is isolated from the third barrier layer 114 below it by using the first channel isolation layer 118 and the second channel isolation layer 119. In addition, a second current isolation layer 117 is added to the current blocking layer 110 to isolate the current while separating the P-GaN current blocking layer 110 from the third channel layer 115.

[0040] The described first channel layer 109, second channel layer 113, and third channel layer 115 are stacked in sequence between the first source electrode 106 and the first current isolation layer 111, with consistent thickness and the thickness value range being 100 - 400 nm. The second source electrode 116 connects each channel layer in the direction perpendicular to the three channel layers. The upper surface of the second source electrode 116 is in contact with the first source electrode 106 located at the top of the device, and the lower surface is in contact with the third channel layer 115. The lateral length value range of the second source electrode 116 is 100 - 1000 nm.

[0041] The described first channel isolation layer 118 is embedded in the second barrier layer 112. The upper surface of the first channel isolation layer 118 is in contact with the lower surface of the first channel layer 109, isolating the direct contact between the first channel layer 109 and the second barrier layer 112. The described second channel isolation layer 119 is embedded in the third barrier layer 114. The upper surface of the second channel isolation layer 119 is in contact with the lower surface of the second channel layer 113, isolating the direct contact between the second channel layer 113 and the third barrier layer 114. The thicknesses of the first channel isolation layer 118 and the second channel isolation layer 119 are consistent, and the value ranges are both 1 - 25 nm, and the length is 1 - 5 μm. Neither the first channel isolation layer 118 nor the second channel isolation layer 119 is in contact with the HfO2 insulating gate 104, and the spacing is 100 - 500 nm.

[0042] The described first current isolation layer 111 is located in the current blocking layer 110 and divides the current blocking layer 110 into two parts. The upper surface of the first current isolation layer 111 is in contact with the third channel layer 115, and the lower surface is in contact with the GaN buffer layer 103. The thickness is 1 - 3 μm, and the length is 1 - 6 μm.

[0043] The described second current isolation layer 117 is embedded in the current blocking layer 110 and is distributed on both sides of the first current isolation layer 111. The upper surface of the second current isolation layer 117 is in contact with the lower surface of the third channel layer 115. The thickness is 0.1 - 1 μm. The second current isolation layer 117 is not in contact with the HfO2 insulating gate 104, and the spacing is 100 - 500 nm.

[0044] The thicknesses of the first barrier layer 108, second barrier layer 112, and third barrier layer 114 are equal before inserting the current isolation layer, and the thickness value ranges are all 15 - 50 nm.

[0045] The gate 105 is located on both sides of the device and is insulated from other areas of the device through the HfO2 insulating gate 104. The thickness of the gate 108 is 1 - 3 μm, and the length is 1 - 2 μm. The thickness of the HfO2 insulating gate 104 is 10 - 100 nm.

[0046] The thickness of the first source electrode 106 is 100 - 200 nm, and the length is 1 - 6 μm; the passivation layer 107 is located on both sides of the first source electrode 106, the thickness of the passivation layer 107 is 200 - 225 nm, and the length is 1 - 6 μm.

[0047] The thickness of the GaN buffer layer 103 is 3 - 10 μm.

[0048] The present invention breaks through the design of using the aperture as the current channel in the traditional structure, and uses the gate voltage to regulate the hole concentration at the current blocking layer and the gate sidewall, so as to realize the opening and closing of the device. In the multi-channel design, by introducing a current isolation layer, the problem of mutual depletion of the electron gas between the multi-channels in the vertical structure is solved. At the same time, an isolation layer is ingeniously embedded in the current blocking layer, effectively preventing the depletion effect of P-GaN on the channel, thereby greatly improving the output ability of the device.

[0049] Figure 3 For the comparison of the transfer characteristic curves of the present invention and the basic structure, wherein the basic structure is as Figure 2 shown. It can be found that the threshold voltages of both the present invention and the basic structure reach 2.81 V. When V d = 6 V, the saturation current densities of the two are 2398.6 mA / mm and 2075.6 mA / mm respectively. Compared with the basic structure, the current density of the present invention is increased by 323 mA / mm, and the maximum transconductance is increased by 70%. The increase in current density is because the device changes from a single-channel structure to a three-channel structure on the basis of the single-channel, and the output ability is improved. At the same time, a SiO2-based current isolation layer is embedded in the P-GaN current blocking layer to isolate the depletion effect of P-GaN on the electrons in the upper channel. As can be seen from Figure 4 , Figure 4 (a) The electron concentration in the channel is significantly less than Figure 4 (b) The electron concentration in the channel, which is because Figure 4 (a) The GaN channel layer is in direct contact with the underlying P-GaN, and the high-concentration holes in the heavily doped P-GaN will inevitably have a certain depletion effect on the electrons in the upper channel, while Figure 4 (b) A layer of SiO2 is inserted between the P-GaN and the upper channel layer, which can not only isolate the downward movement of electrons, but also prevent the depletion effect of the P-GaN layer on electrons. Therefore, Figure 4 (b) There is a high-concentration electron distribution almost throughout the GaN channel layer.

[0050] From Figure 5 it can be seen that Figure 5 (a) The electron concentration distribution region of the double-channel structure without a channel isolation layer is significantly smaller than Figure 5 (b) The double-channel structure with a channel isolation layer and Figure 5(c) The electron concentration distribution region of the triple-channel with a channel isolation layer structure, and the electron concentration value is also smaller. This is because in the case of multiple channels, the GaN channel layer will form a GaN / AlGaN heterojunction with the underlying AlGaN barrier layer, generating two-dimensional hole gas (2DHG). And since the source of the vertical device is above and the drain is below, when an external stress is applied, a vertical electric field is generated. Therefore, the generated hole gas will move vertically and undergo mutual recombination depletion with the two-dimensional electron gas in the channel, resulting in a decrease in the electron concentration in the channel and an increase in the resistance. By inserting a channel isolation layer based on SiO2 with a certain thickness between the AlGaN / GaN heterojunction to isolate the direct contact between AlGaN and GaN, this problem can be effectively avoided, enabling the multi-channel structure to give full play to its advantages and functions without being affected by the hole gas.

[0051] Figure 6 Figure for comparing the output characteristic curves of the present invention and the basic structure, V g = 5V, the saturation output current of the exemplary structure of the present invention compared to the basic structure increases from the original 2012 mA / mm to 3459 mA / mm, an increase of 71.9%; the on-resistance is reduced by 0.38 Ω·mm compared to the basic structure, only 2.29 Ω·mm.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A current-enhanced multi-channel isolation AlGaN / GaN CAVET device, characterized in that: The device includes: A substrate (102); A GaN buffer layer (103) located on the surface of the substrate (102); a current blocking layer (110) located on the surface of the GaN buffer layer (103); A current isolation structure located on the surface of the GaN buffer layer (103), wherein the current isolation structure separates the current blocking layer (110) into two parts; At least three stacked barrier / channel structures located on the surface of the current blocking layer and the current isolation structure; a channel isolation layer located between the barrier / channel structures; A first source electrode (106) located on the surface of the uppermost barrier / channel structure; A second source electrode (116) perpendicular to the stacking direction of the barrier / channel structure and used for connecting the channel layers in each of the barrier / channel structures, the second source electrode (116) being connected to the first source electrode (106); A passivation layer (107) located on the surface of the uppermost barrier / channel structure and distributed on both sides of the first source electrode (106); Gates (105) located on both sides of the device; and The surface is located on a side of the substrate (102) away from the GaN buffer layer (103).

2. The CAVET device according to claim 1, characterized in that: The current isolation structure comprises a first current isolation layer (111) and a second current isolation layer (117) distributed on both sides of the first current isolation layer (111).

3. The CAVET device according to claim 1, characterized in that: The barrier / channel structure includes a channel layer and a barrier layer, and the barrier layer is located on the upper surface of the channel layer.

4. The CAVET device according to claim 1, characterized in that: The gates (105) located on both sides of the device are insulated from other parts of the device by HfO2 insulating gates (104).

5. The CAVET device according to claim 2 or 4, characterized in that: There is a distance between the second current isolation layer (117) and the HfO2 insulating gate (104), and the distance is 100 to 500 nm.

6. The CAVET device according to claim 1 or 4, characterized in that: There is a gap between the channel isolation layer located between the potential barrier / channel structure and the HfO2 insulating gate (104), and the gap is 100-500nm.

7. The CAVET device according to claim 1, characterized in that: The channel layers in each of the barrier / channel structures have the same thickness, and the barrier layers in each of the barrier / channel structures have the same thickness.

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