MOSFET chip, transistor, power supply and electronic equipment

Abstract

A MOSFET chip, a transistor, a power supply, and an electronic device, the MOSFET chip including a gate pad, at least two gate buses, and at least two primitive cell regions, each of the at least two primitive cell regions including at least one primitive cell unit. Each of the at least two gate buses is connected to a different primitive cell region of the at least two primitive cell regions, and the gate pad is connected to the at least two gate buses. The grid bonding pad is used for driving at least one primitive cell unit to start through at least two grid buses, and the starting time points of at least one primitive cell area in the at least two primitive cell areas are different, so that primitive cells in the MOSFET chip are divided into different areas, and the starting time points of the different areas are different. Through time-sharing starting, the phenomenon of heat aggregation of primitive cells with small spacing in a slow starting stage is avoided, and the reliability of the MOSFET transistor is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of electronic technologies, and in particular, to a MOSFET chip, a transistor, a power supply, and an electronic device. Background Art

[0002] With the continuous development and wide application of communication technologies, the reliability of power supply systems has become particularly important. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a commonly used electronic device in power supply systems.

[0003] Currently, the shutdown of a power supply system will have very serious impacts. Therefore, maintaining the system and replacing faulty components without affecting the operation of the power supply system is a very effective method to improve system reliability. This characteristic of being able to be plugged and unplugged without power interruption and without affecting the normal operation of other components requires the core device MOSFET in the circuit to have a soft-start characteristic. During soft start, the MOSFET device is not fully turned on, and the duration is usually in the order of hundreds of microseconds or even more than ten milliseconds, during which a large inrush current will be generated.

[0004] However, in order to reduce the losses of MOSFET devices and improve device efficiency, the cells in MOSFETs have evolved from a planar structure to a trench structure, making the pitch between cells smaller and smaller. As the pitch between cells becomes smaller and smaller, the MOSFET is more prone to thermal aggregation during the soft-start stage. When the soft-start stage exceeds the single-pulse current that the MOSFET can withstand, the device will be burned out due to overheating. Summary of the Invention

[0005] Embodiments of the present application provide a MOSFET chip for avoiding thermal aggregation of cells with a small pitch in the MOSFET chip during the soft-start stage and improving the reliability of MOSFET transistors. Embodiments of the present application also provide corresponding transistors, power supplies, and electronic devices.

[0006] In a first aspect of the present application, a MOSFET chip is provided. The MOSFET chip includes a gate pad, at least two gate buses, and at least two cell regions; each of the at least two cell regions includes at least one cell unit; each of the at least two gate buses is connected to a different cell region among the at least two cell regions, and the gate pad is connected to the at least two gate buses; the gate pad is configured to drive at least one cell unit to start through the at least two gate buses, and there is at least one cell region among the at least two cell regions whose start time points are different.

[0007] In this application, the MOSFET chip further includes a source pad and a drain pad, and at least two cell regions are also connected to the source pad. The gate buses correspond to the cell regions one by one, that is, each gate bus is responsible for connecting a cell region to the gate pad.

[0008] In this application, among at least two cell regions, there is at least one cell region whose startup time point is different, that is, there is at least one cell region whose startup time point is different from that of other cell regions. By adjusting the startup time points of the cell regions and setting at least one cell region to have a different startup time point from other cell regions, the phenomenon of thermal aggregation caused by each cell region starting up simultaneously can be avoided.

[0009] In a first aspect, the MOSFET chip includes a gate pad, at least two gate buses, and at least two cell regions. Each of the at least two cell regions includes at least one cell unit. Each of the at least two gate buses is connected to a different cell region among the at least two cell regions, and the gate pad is connected to the at least two gate buses. The gate pad is used to drive at least one cell unit to start through the at least two gate buses. Among the at least two cell regions, there is at least one cell region whose startup time point is different. Thus, different regions are divided in the cell of the MOSFET chip, and the startup time points of different regions are different. By starting at different times, the phenomenon of thermal aggregation of cells with small spacing during the soft start stage can be avoided, improving the reliability of the MOSFET transistor.

[0010] In a possible implementation manner of the first aspect, the chip further includes at least two delay units. Each of the at least two gate buses is connected to a different delay unit among the at least two delay units, and the gate pad is connected to the at least two gate buses through the at least two delay units; the at least two delay units are used to extend the startup time points of the at least two cell regions, and the extension time set by each of the at least two delay units is different.

[0011] In this possible implementation manner, the delay unit does not need to change the peripheral circuit of the MOSFET chip. It only needs to integrate units with delay functions such as capacitors on the die of the chip to achieve it. The overall structure complexity is low and the adaptability is high.

[0012] In a possible implementation manner of the first aspect, the at least two delay units are delay circuits composed of capacitors and resistors, and the capacitance values and / or resistance values of the at least two delay units are different.

[0013] In this possible implementation, the delay unit is specifically a delay circuit, which is composed of a capacitor and a resistor. By adjusting the capacitance value of the capacitor and / or the resistance value of the resistor, the extended time set by the delay unit can be changed, thereby changing the start time point of each cell region and improving the feasibility of the solution.

[0014] In a possible implementation of the first aspect, the number of gate pads is at least two. Each of the at least two gate pads is connected to a different gate bus among at least two gate buses, and the driving time points of each of the at least two gate pads are different.

[0015] In this possible implementation, the driving time point of the external driver can also be controlled, and then the start time point of each gate PIN driving each cell region can be changed, so that a more flexible adjustment of the driving time point can be achieved to meet different needs of users.

[0016] In a possible implementation of the first aspect, the chip further includes a driving unit, and the driving unit is used to control the driving time point at which at least two gate pads drive at least one cell unit to start.

[0017] In this possible implementation, the driving unit can be built into the chip, which improves the feasibility of the solution.

[0018] In a possible implementation of the first aspect, the start time points of each of the at least two cell regions are different.

[0019] In this possible implementation, the start time points of each cell region are all different from each other, which ensures that the start time points of adjacent cell regions are different, and further avoids the phenomenon of thermal aggregation of cell units with small pitch.

[0020] In a possible implementation of the first aspect, at least one cell unit is a trench-structured cell.

[0021] In this possible implementation, the cell units in each cell region are all of trench structure, thereby reducing the loss of the MOSFET device and improving the efficiency of the device. Although the trench structure will reduce the pitch between cell units, by combining the method of setting a delay unit or controlling the driving time point in the embodiments of the present application, the phenomenon of thermal aggregation caused by the small pitch of cell units can be avoided.

[0022] The second aspect of the present application provides a MOSFET transistor, which includes a MOSFET chip as described in the above first aspect or any possible implementation of the first aspect.

[0023] A third aspect of the present application provides a power supply, which includes a MOSFET chip and a driving circuit as described in the first aspect or any possible implementation manner of the first aspect, and the driving circuit is coupled to the MOSFET chip.

[0024] A fourth aspect of the present application provides an electronic device, which includes a MOSFET chip as described in the first aspect or any possible implementation manner of the first aspect. Description of the Drawings

[0025] Figure 1 It is an equivalent circuit diagram of the existing MOSFET chip layout design;

[0026] Figure 2 It is a schematic diagram of an embodiment of the MOSFET chip provided by an embodiment of the present application;

[0027] Figure 3 It is a schematic diagram of another embodiment of the MOSFET chip provided by an embodiment of the present application;

[0028] Figure 4 It is a schematic diagram of another embodiment of the MOSFET chip provided by an embodiment of the present application;

[0029] Figure 5 It is a schematic diagram of an embodiment of the electronic device provided by an embodiment of the present application. Detailed Embodiments

[0030] The embodiments of the present application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Those of ordinary skill in the art can know that with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0031] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] As used herein, the term "exemplary" means "serving as an example, instance, or illustration". Any embodiment described as "exemplary" herein is not necessarily to be construed as preferred or better than other embodiments.

[0033] In addition, for a better illustration of the present application, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present application can also be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail so as to highlight the gist of the present application.

[0034] The key terms related to the embodiments of the present application are explained below.

[0035] (1) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)

[0036] The MOSFET transistor (the main component is the MOSFET chip or die, hereinafter simply referred to as MOSFET) is a commonly used electronic device and is widely used in various circuits. It has characteristics such as high current driving ability, low power consumption, and fast response, and is widely used in fields such as power amplification, switch control, and analog signal processing. The MOSFET consists of a metal-oxide-semiconductor (MOS) structure, which includes an insulating layer, a control electrode (gate), and semiconductor material between the two control electrodes.

[0037] The working principle of the MOSFET is to control the current in the channel by controlling the gate voltage. The MOSFET has three working modes: cut-off region, saturation region, and amplification region. In the cut-off region, the MOSFET is in the off state and no current passes through. In the saturation region, the MOSFET can carry a large current, and at this time the voltage can control the magnitude of the current. In the amplification region, the MOSFET can amplify voltage or current signals. The working principle of the MOSFET is based on the field effect. When the gate voltage is zero, no conductive channel is formed in the semiconductor material under the insulating layer, so current cannot flow through. When a positive voltage is applied to the gate, an electric field will be formed under the insulating layer, causing a conductive channel to be formed in the semiconductor material and current can flow through. By changing the gate voltage, the resistance of the conductive channel can be controlled, thereby controlling the magnitude of the current.

[0038] One of the advantages of MOSFET is its low power consumption. Due to the presence of the insulating layer, there is almost no leakage current in the cutoff region of MOSFET, so it hardly consumes energy when not working. This makes MOSFET suitable for applications that require low power consumption, such as mobile devices and battery-powered circuits. Another advantage is that MOSFET has the characteristic of fast response. Due to the presence of the insulating layer, the response time of MOSFET is very short, and it can quickly switch the current on and off. This makes MOSFET suitable for applications that require high-frequency operation, such as radio frequency (RF) circuits and communication devices. MOSFET also has high current driving ability. Due to the presence of the conductive channel, MOSFET can withstand a large current. This makes MOSFET suitable for applications that need to drive high-power loads, such as motor drives and power control.

[0039] In summary, MOSFET is an important electronic device with characteristics such as high current driving ability, low power consumption, and fast response. It is widely used in various circuits, such as power amplification, switch control, and analog signal processing. By controlling the gate voltage, the conductive channel of MOSFET can be controlled, thereby controlling the magnitude of the current and achieving precise control of the circuit.

[0040] (2) MOSFET cell:

[0041] The most basic working unit of MOSFET is called a cell. A cell mainly consists of a source, a drain, a gate, and a substrate. The functions of each part are as follows:

[0042] Source and drain: In the cell structure of MOSFET, the source and drain are the two endpoints used to conduct and cut off the channel. When MOSFET is in the on state, current flows from the source to the drain.

[0043] Gate: The gate is the key part of MOSFET, which controls the switching of the channel. The electric field of the gate can attract or repel electrons in the channel, thereby controlling the flow of current.

[0044] Substrate: The substrate is the foundation of the entire MOSFET, usually a semiconductor material. The main function of the substrate is to provide a path for electron conduction and support the structure of the entire device.

[0045] In addition, the cell structure of the MOSFET also involves some important physical parameters, such as channel length, channel width, etc. These parameters will affect the performance and characteristics of the MOSFET, such as switching speed, on-state resistance, avalanche energy, etc. Generally speaking, the cell structure of the MOSFET is a highly symmetric structure, and its various components work together, enabling the MOSFET to play an important role in semiconductor devices. The typical cells of the MOSFET are divided into planar structures and trench structures. When the cells of the MOSFET are connected together through the gate bus, a MOSFET device (transistor) is formed.

[0046] (3) Gate:

[0047] The gate of the MOSFET is an important component of the MOSFET. It is used to control the on / off state of the field-effect transistor in the MOSFET. A very important feature of the gate of the MOSFET is that it can control the current flow in the MOSFET through an electric field. This means that the gate can control the current flow in the MOSFET by changing the intensity of the electric field. According to the structure of the MOSFET, the gate is usually a very thin metal layer or semiconductor material, which is sandwiched between the source and drain of the MOSFET. When a voltage is applied to the gate, it forms an electric field, and this electric field will control the width of the conductive layer in the MOSFET, thereby controlling the current flow. During the operation of the MOSFET, the voltage of the gate will determine the on / off state of the MOSFET. When a positive voltage is applied to the gate, it will attract electrons, causing the electron layer in the MOSFET to move towards the drain, thereby forming a path and starting the current flow. When a negative voltage is applied to the gate, it will repel electrons, causing the electron layer in the MOSFET to move towards the source, thereby blocking the current flow and making the MOSFET an open circuit. By controlling the voltage of the gate, the current flow in the MOSFET can be effectively controlled, thereby achieving the control of the circuit.

[0048] (4) Gate bus:

[0049] The MOSFET is composed of many parallel independent cell units and is connected together through the gate bus. The bus used to connect the gates of each independent cell inside the MOSFET device is called the gate bus.

[0050] (5) Gate pad:

[0051] The surface of a MOSFET chip generally consists of a source pad, a gate pad, and a drain pad. The gate pad is the PAD interconnected to the gate pin of the device frame. The main function of the gate pad is to transmit the gate signal to each switching unit.

[0052] (6) Safety operation area (SOA):

[0053] SOA refers to the range of conditions under which a power semiconductor device can operate reliably, which is jointly determined by five factors: on-resistance, maximum current, maximum power dissipation, second breakdown power, and maximum breakdown voltage. With the development of technology, the cells of MOSFETs are becoming more and more dense, and the thermal effect of the device is becoming more and more obvious. The typical failure scenario of the ultra-safety operation area (SOA) is the second breakdown caused by thermal aggregation during high-current applications in the linear operating region.

[0054] (7) Gate charge (Qg):

[0055] Qg refers to the gate charge of a transistor, also known as gate charge or gate charge quantity. In a MOSFET device, Qg refers to the amount of charge required for charging and discharging the gate capacitor. The magnitude of Qg is related to factors such as gate length, gate area, and insulation layer thickness. The magnitude of Qg will affect performance indicators such as the switching speed, power consumption, and thermal stability of the device.

[0056] The following is an example of the application scenario involved in the embodiments of the present application in combination with the above key term definitions.

[0057] With the continuous development and wide application of communication technologies, the reliability of power systems has become particularly important. MOSFET is a commonly used electronic device in power systems. Currently, even a one-second interruption of the power system can have very serious consequences. Therefore, being able to maintain the system and replace faulty components without affecting the operation of the power system is a very effective method to improve system reliability. This characteristic of being able to be plugged and unplugged without power interruption and without affecting the normal operation of other components requires the core device MOSFET in the circuit to have the characteristic of soft start. The duration of the soft start of a single board is usually in the range of hundreds of microseconds or even more than ten milliseconds, and a large inrush current will be generated during the process. However, under normal circumstances, the normal operating time of a power MOSFET device under this condition is only a few microseconds or even shorter. Therefore, the inrush current and duration generated during soft start exceed the safe operating area (SOA) of the device, ultimately resulting in device damage. As the next-generation products of telecommunication networks evolve towards large capacity and low loss, low-loss, high-reliability wide-SOA power MOSFET devices are required.

[0058] At present, in order to pursue a lower characteristic on-resistance, reduce the loss of the MOSFET device, and improve the efficiency of the device, the cell evolves from a planar structure to a trench structure, continuously reducing the cell size of the MOSFET device, resulting in a further increase in the power density of the MOSFET device, and the distance between cells is getting smaller and smaller.

[0059] However, as Figure 1 shown, the design of traditional MOSFET chips is that all cells are interconnected to a gate bus (usually interconnected with a metal material, such as aluminum Al). When a voltage is applied to the gate when the MOSFET is started, all cells inside the MOSFET device start simultaneously. In the application scenario of soft start, when the MOSFET device is not fully turned on, a high voltage, large current, and relatively long duration will be applied between the drain and the source. As the distance between cells gets smaller, thermal aggregation is more likely to occur during the soft start phase, inevitably resulting in a significant reduction in the SOA of the device. When the soft start phase exceeds the single-pulse current that the MOSFET can withstand, the device will burn out due to overheating.

[0060] The existing solution to improve the soft start performance of MOSFET devices is to increase the distance between cells without reducing the number of MOSFET cells, increase heat dissipation, and reduce thermal aggregation during the soft start phase, thereby improving the soft start ability of MOSFET devices. The consequence of this is that the area of the chip will increase. In short, the SOA ability of MOSFET is improved by increasing the chip area.

[0061] Increasing the chip area, the most typical problem is that it will increase the total gate charge Qg. And the increase in the total gate charge Qg will lead to the following problems:

[0062] 1. Increase in input capacitance: The larger Qg is, the larger the input capacitance is. The size of the input capacitance will affect the input impedance and frequency response of the MOSFET, thereby changing the input characteristics of the device.

[0063] 2. Decrease in switching speed: When the gate voltage changes, the larger the gate charge Qg is, the slower the switching speed is. This is mainly because the larger Qg is, the longer it takes for the drive circuit of the MOS transistor to charge or discharge, resulting in a decrease in the switching speed.

[0064] 3. Increase in power consumption: Since Qg increases, the gate drive circuit needs to provide a larger current to meet the charge demand, resulting in an increase in power consumption. This may lead to problems such as device overheating and reduced efficiency.

[0065] 4. Reduced device lifespan: An increase in Qg may lead to a decrease in the switching times of the MOS transistor, thereby reducing the service life of the device. This is mainly because after Qg increases, the switching speed of the MOS transistor slows down, increasing the switching loss and thermal loss, resulting in accelerated device aging.

[0066] Therefore, when designing the MOSFET layout, it is necessary to minimize the gate charge Qg as much as possible, improve the switching performance of the MOSFET, reduce the switching loss of the MOSFET device, and enhance the soft-start performance of the MOSFET device. Based on this, the embodiments of the present application provide a MOSFET chip to avoid the phenomenon of thermal aggregation in the cells with small pitch during the soft-start stage of the MOSFET chip and improve the reliability of the MOSFET transistor. The embodiments of the present application also provide corresponding transistors, power supplies, and electronic devices. The following will be described in detail respectively.

[0067] The MOSFET chip provided by the embodiments of the present application will be described below in combination with the above key term definitions and application scenarios.

[0068] As Figure 2 shown, the embodiments of the present application provide a MOSFET chip. An embodiment of the MOSFET chip includes a gate pad 100, at least two gate buses 200, and at least two cell regions 300.

[0069] Among them, each of the at least two cell regions 300 includes at least one cell unit 310. Each of the at least two gate buses 200 is connected to a different cell region among the at least two cell regions 300, and the gate pad 100 is connected to the at least two gate buses 200. The gate pad 100 is used to drive at least one cell unit 310 to start through the at least two gate buses 200, and there is at least one cell region among the at least two cell regions 300 whose start time points are different.

[0070] Specifically, the MOSFET chip (hereinafter simply referred to as the chip) further includes a source pad 400 and a drain pad (the drain and the drain pad are located on the back of the chip and are not shown in the figure), and the at least two cell regions 300 are also connected to the source pad 400. The gate buses 200 correspond to the cell regions 300 one by one, that is, each gate bus 200 is responsible for connecting a cell region 300 to the gate pad 100.

[0071] It should be understood that the MOSFET chip described in the embodiments of the present application is a key component of the MOSFET transistor. In some implementation manners or descriptions, the relationship between the MOSFET chip and the MOSFET transistor can be equivalent.

[0072] Exemplarily, the chip includes two gate buses 200, a cell region A, and a cell region B. Both the cell region A and the cell region B include three cell units 310. The gate pad 100 is used to drive the cell region A and the cell region B to start. The start time point of the cell region A is a, and the start time point of the cell region B is b. a and b are not equal, that is, the start time points of the cell region A and the cell region B are different, thus avoiding the heat aggregation phenomenon caused by the simultaneous start of the cell region A and the cell region B.

[0073] It should be understood that when there are more cell regions 300, at least one start time point of one cell region 300 needs to be different from the start time points of other cell regions 300, and the start time points of other cell regions 300 may be the same. The embodiments of the present application do not limit this.

[0074] In the embodiments of the present application, among at least two cell regions 300, at least one start time point of one cell region 300 is different, that is, at least one start time point of one cell region 300 is different from the start time points of other cell regions 300. By adjusting the start time points of the cell regions 300 and setting at least one start time point of one cell region 300 to be different from the start time points of other cell regions 300, the heat aggregation phenomenon caused by the simultaneous start of each cell region 300 can be avoided.

[0075] Optionally, in order to further avoid the heat aggregation phenomenon of the cell units 310 with small pitch, the start time points of each cell region 300 among at least two cell regions 300 are different, that is, the start time points of each cell region 300 are all different from each other. And there are various ways to control the start time points of the cell regions 300, which will be described in detail below.

[0076] I. Setting delay units

[0077] At this time, the chip further includes at least two delay units. Each of at least two gate buses is connected to a different delay unit among at least two delay units. The gate pad is connected to at least two gate buses through at least two delay units. The at least two delay units are used to extend the start time points of at least two cell regions. The extended time points set by each of the at least two delay units are different, so that the start time points of each cell region are different.

[0078] Specifically, the delay units correspond to the gate buses one by one, and the delay units also correspond to the cell regions one by one, that is, each delay unit is only responsible for extending the start time point of one cell region.

[0079] Exemplarily, such as Figure 3As shown (the actual gate bus is connected to each cell unit), at least two delay units are RC delay circuits composed of capacitors and resistors. At least two cell regions are region A, region B, and region C respectively. Each cell region includes multiple cell units. At least two delay units are delay circuits composed of capacitor A and resistor A, delay circuit composed of capacitor B and resistor B, and delay circuit composed of capacitor C and resistor C. The corresponding gate buses are also three. The gate bus of region A is connected to the gate pad through capacitor A, the gate bus of region B is connected to the gate pad through capacitor B, and the gate bus of region C is connected to the gate pad through capacitor C.

[0080] When the gate pad drives the cell unit to start and applies voltage, first, three capacitors, namely capacitor A, capacitor B, and capacitor C, need to be charged. Since the capacitance values of capacitor A, capacitor B, and capacitor C are different, the charging time points are different. Therefore, the time points when the cell units on the gate buses of region A, region B, and region C are powered on by the gate are also different. Thus, the start time points of the cell units in region A, region B, and region C are different.

[0081] Optionally, the interval between the start time points of each cell region in at least two cell regions is greater than the time points required for each cell region in at least two cell regions to start. That is, when the capacitance values of the capacitors interconnected with the gate bus are set reasonably, when all the cell units in region A start, the cell units in two of region B and region C have not started to start. When the cell units in region A complete starting, the cell units in region B start to start, and the cell units in region C have not started to start. When the cell units in two of region A and region B complete starting, the cell units in region C start to start. When the starting of the cell units in region C is completed, the entire MOSFET chip completes starting.

[0082] Thus, by setting the delay units, the purpose of region-by-region and time-sharing soft start can be achieved. Moreover, during region-by-region soft start, the regions that are not starting or have completed starting will not have the thermal aggregation effect during the soft start stage. In addition, this delay unit does not need to change the peripheral circuit of the MOSFET chip. It only needs to integrate delay function units such as capacitors on the die of the chip to achieve it. The overall structure complexity is low and the adaptability is high.

[0083] It should be understood that the delay unit can be replaced by other units or components with delay functions in addition to the delay circuit composed of capacitors and resistors. For example, a delay circuit composed of capacitors, resistors, and inductors, etc., as long as the delay effects are inconsistent. The embodiments of the present application do not limit this.

[0084] II. Control the driving time point

[0085] At this time, the number of gate pads is at least two, each of the at least two gate pads is connected to a different gate bus among at least two gate buses, and the driving time points of each of the at least two gate pads are different.

[0086] Specifically, the gate pads correspond to the gate buses one by one, and the gate pads also correspond to the cell regions one by one, that is, each gate pad is only responsible for driving one cell region.

[0087] Exemplarily, as Figure 4 shown (the actual gate buses are connected to each cell unit), each cell region has an independent gate pad (gate pad in region A, gate pad in region B, and gate pad in region C), and the start time points of the cell units in regions A, B, and C are driven by an external driver (such as a driving circuit IC outside the transistor) through different gate PINs. When the driving time points of the driver are set reasonably, when all the cell units in region A start, the cell units in two of regions B and C have not started yet. When the cell units in region A complete starting, the cell units in region B start, and the cell units in region C have not started yet. When the cell units in two of regions A and B complete starting, the cell units in region C start. When the starting of the cell units in region C is completed, the entire MOSFET chip completes starting.

[0088] Optionally, the chip further includes a driving unit, and the driving unit is used to control the driving time points at which at least two gate pads drive at least one cell unit to start. That is, instead of controlling each gate PIN through an external driver, the driving unit can be built into the chip, and the driving time points at which each gate pad drives each cell region to start are controlled by the built-in driving unit.

[0089] Thus, by setting multiple gate pads, the purpose of region-by-region and time-sharing soft start can be achieved. Moreover, during region-by-region soft start, the regions that are not starting or have completed starting will not have the thermal aggregation effect during the soft start stage. In addition, by controlling the driving time points of the external driver, the starting time points at which each gate pad drives each cell region can be changed, so that more flexible adjustment of the driving time points can be realized to meet different needs of users.

[0090] Optionally, at least one cell unit is a trench-structured cell, such as a shield gate (SGT) structure or a super junction (SJ) structure. That is, the cell units in each cell region are all of trench structure, thereby reducing the loss of the MOSFET device and improving the efficiency of the device. Although the trench structure will reduce the spacing between cell units, by combining the method of setting a delay unit or controlling the driving time point in the embodiment of the present application, the thermal aggregation phenomenon caused by the small spacing of cell units can be avoided.

[0091] It should be understood that in the embodiments of the present application, at least two cell regions can be divided from all the cell units in the MOSFET chip. The maximum value of the cell region is the number of cell units, that is, each cell unit can be separately divided into a single cell region. The specific division rule can be determined based on the user's needs, as long as it is ensured that there are at least two cell regions that can be started in a time-sharing and region-by-region manner.

[0092] In the embodiments of the present application, the MOSFET chip includes a gate pad, at least two gate buses, and at least two cell regions. Each cell region in the at least two cell regions includes at least one cell unit. Each of the at least two gate buses is connected to a different cell region among the at least two cell regions, and the gate pad is connected to the at least two gate buses. The gate pad is used to drive at least one cell unit to start through the at least two gate buses. There is at least one cell region in the at least two cell regions whose start time points are different. Thus, the cells in the MOSFET chip are divided into different regions, and the start time points of different regions are different. By starting in a time-sharing manner, the phenomenon of thermal aggregation of cells with small spacing during the soft start stage is avoided, and the reliability of the MOSFET transistor is improved.

[0093] The MOSFET chip provided in the embodiments of the present application is introduced above. Next, the transistor, power supply, and electronic device provided in the embodiments of the present application will be introduced with reference to the accompanying drawings.

[0094] As Figure 5 shown, the embodiments of the present application provide an electronic device 500. The electronic device 500 includes a power supply 510 and a power-consuming unit 520. The power supply 510 includes a MOSFET transistor 511 and a driving circuit 512 coupled to the MOSFET transistor 511. The MOSFET transistor 511 includes the MOSFET chip provided in the embodiments of the present application.

[0095] Specifically, the electronic device 500 can be any device that needs to use the power supply 510 or the MOSFET transistor 511. The embodiments of the present application do not limit this.

[0096] Exemplarily, when the electronic device 500 needs to be used, the driving circuit 512 drives the MOSFET transistor 511 to start the power supply 510. The power supply 510 provides a working voltage to the power-consuming unit 520, enabling the electronic device 500 to work properly.

[0097] When maintenance or fault replacement of the power-consuming unit is required, it is necessary to ensure that the power supply does not stop working. At this time, the MOSFET transistor enters the soft-start mode, and the MOSFET transistor provided by the embodiment of the present application can perform soft-start in a region-by-region and time-sharing manner, so thermal aggregation effects will not occur, ensuring the reliability of the entire electronic device.

[0098] Optionally, the MOSFET transistor provided by the embodiment of the present application can also be applied to other power devices such as DrMOS, and the embodiment of the present application does not limit this.

[0099] Those of ordinary skill in the art can realize that the structural units of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0100] In several embodiments provided by the present application, it should be understood that the disclosed structure can be implemented in other ways. For example, the above-described embodiments are merely illustrative. For example, the division of the structure may have other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another structure, or some features can be ignored. The part or all of the structure can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, indirect couplings or communication connections of structures or units, and can be in electrical, mechanical or other forms.

[0101] In addition, the various structures in the embodiments of the present application can be integrated into one structure, or each structure can exist physically alone, or two or more structures can be integrated into one structure.

[0102] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A MOSFET chip, characterized in that, It includes a gate pad, at least two gate buses, and at least two cell regions; Each of the at least two cell regions includes at least one cell unit; Each of the at least two gate buses is connected to a different cell region among the at least two cell regions, and the gate pad is connected to the at least two gate buses; The gate pad is used to drive the at least one cell unit to start through the at least two gate buses, and the start time points of at least one of the at least two cell regions are different.

2. The chip according to claim 1, characterized in that, The chip further includes at least two delay units. Each of the at least two gate buses is connected to a different delay unit among the at least two delay units, and the gate pad is connected to the at least two gate buses through the at least two delay units; The at least two delay units are used to extend the start time points of the at least two cell regions, and the extension time set by each of the at least two delay units is different.

3. The chip according to claim 2, characterized in that, The at least two delay units are delay circuits composed of capacitors and resistors, and the capacitance values and / or resistor values of the at least two delay units are different.

4. The chip according to claim 1, characterized in that, The number of the gate pads is at least two. Each of the at least two gate pads is connected to a different gate bus among the at least two gate buses, and the driving time points of each of the at least two gate pads are different.

5. The chip according to claim 4, characterized in that, The chip further includes a driving unit, and the driving unit is used to control the driving time points at which the at least two gate pads drive the at least one cell unit to start.

6. The chip according to any one of claims 1-5, characterized in that, The start time points of each of the at least two cell regions are different.

7. The chip according to any one of claims 1-6, characterized in that, The at least one cell unit is a trench-structured cell.

8. A MOSFET transistor, characterized in that, The transistor includes the MOSFET chip according to any one of claims 1-7.

9. A power supply, characterized in that, The power supply includes the MOSFET chip according to any one of claims 1-7 and a driving circuit, and the driving circuit is coupled to the MOSFET chip.

10. An electronic device, characterized in that, The electronic device includes the MOSFET chip according to any one of claims 1-7.

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