Interconnection structure and method for SerDes between bare chips

Abstract

The invention discloses a SerDes interconnection structure and method between bare chips. The bare chips are arranged in the packaging body or on the packaged PCB according to the set clock direction, and each bare chip is provided with a plurality of pairs of TX / RX signal channels. Each pair of TX / RX signal channels comprises a TX pin, a calculation module and an RX pin, and the TX pins and the RX pins are positioned on the same side of the bare chips, so that forward data and reverse data can be transmitted among the bare chips according to a set clock direction. Forward data is sent out from the starting bare chip and then directly transmitted to the end point bare chip according to the set hour hand direction, and reverse data is sent out from the end point bare chip and then transmitted to the starting bare chip after passing through all the bare chips except the starting bare chip and the end point bare chip according to the set hour hand direction. According to the invention, by changing a conventional SerDes interconnection structure between bare chips, the bandwidth utilization rate and the system performance are improved, and the delay is reduced.

Description

Technical Field

[0001] The present invention relates to a SerDes interconnection structure and method between bare chips, and more particularly, to a SerDes interconnection structure and method between different bare chips within the same package or on a PCB after packaging. Background Art

[0002] SerDes is short for SERializer / DESerializer, which is a mainstream time-division multiplexing (TDM), point-to-point (P2P) serial communication technology and a common communication method for communication between bare chips (corresponding to the English die, also known as die or bare chip).

[0003] The channels involved in SerDes include TX / RX signal channels. For example, Figure 2 , taking 2 TX / RX signal channels as an example, data enters from the RX1 pin on the left side of the bare chip 10, passes through a pipeline 12 and then enters the calculation module 11. After the calculation is completed, it passes through another pipeline 12 and is sent out from the TX1 pin on the right side of the bare chip 10. Similarly, data enters from the RX2 pin on the right side of the bare chip 10, passes through a pipeline 12 and then enters the calculation module 11. After the calculation is completed, it passes through another pipeline 12 and is sent out from the TX2 pin on the left side of the bare chip 10. Each bare chip is usually arranged in a clockwise direction. Usually, the layout of TX and RX pins on each bare chip is the same, and as Figure 1 and Figure 2 shown, positive data is transmitted between each bare chip 10 in a clockwise direction from left to right. On the contrary, reverse data is transmitted between each bare chip 10 in a counterclockwise direction from right to left. It can be seen that according to the above transmission method, the TX1 and RX2 pins of one bare chip 10 can be directly connected to the RX1 and TX2 pins of another bare chip 10 directly. Such a design is relatively simple for substrate / PCB wiring, with a short wiring distance and no signal crossovers, which is especially friendly for large-scale SerDes interconnections. Figure 1 The double-dashed line in

[0004] However, it can be found from actual use that Figure 1 this transmission method shown in Figure 1The bandwidth for the bare die 1 to transfer data to the bare die 2 is similar to that for the bare die 2 to transfer data to the bare die 1, that is, it is applicable to conventional transfer methods such as PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard). However, if it is used in a transfer method with unbalanced bandwidth and a pursuit of maximizing bandwidth, there will be a problem of huge waste of bandwidth. Taking Figure 1 the 4 bare dies shown in as an example, if a large amount of main data (forward data) is transmitted in the clockwise direction among the bare dies 10, and a small amount of control data (reverse data) is transmitted in the counterclockwise direction, that is, a large amount of main data is transmitted in the clockwise direction of bare die 1, bare die 2, bare die 3, bare die 4, bare die 1, and a small amount of control data is transmitted in the counterclockwise direction, then it can be seen that in the counterclockwise direction, each SerDes is almost idle, the bandwidth utilization rate is poor, and the system performance is affected. Summary of the Invention

[0005] The object of the present invention is to provide a SerDes interconnection structure and method between bare dies, which improves the bandwidth utilization rate and system performance and reduces the latency by changing the traditional SerDes interconnection structure between bare dies.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A SerDes interconnection structure between bare dies is used for SerDes interconnection between different bare dies in the same package or on a PCB after packaging. Each of the bare dies is arranged in a set clockwise direction, and multiple pairs of TX / RX signal channels are provided on each of the bare dies, where: each pair of the TX / RX signal channels includes a TX pin, a calculation module, and an RX pin. The TX pin and the RX pin are located on the same side of the bare die, so that positive data and reverse data can be transmitted between the bare dies in the set clockwise direction. Among them, the positive data is directly transmitted from the starting bare die to the ending bare die in the set clockwise direction after being sent out, and the reverse data is transmitted from the ending bare die to the starting bare die in the set clockwise direction after passing through all other bare dies except the starting bare die and the ending bare die.

[0007] The advantages of the present invention are: Compared with the traditional SerDes interconnection between bare chips, the present invention improves the bandwidth utilization rate, enhances the system performance, and has lower latency by changing the layout of the TX / RX signal channels within the bare chips and redefining the data transmission direction between the bare chips. The present invention is applicable to SerDes interconnections between different bare chips (dies) within the same package or on a PCB after packaging, without being limited by scale, and the beneficial effects are more significant when used for large-scale SerDes interconnections. It is particularly applicable to transmission methods with unbalanced bandwidth and the pursuit of maximum bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a schematic diagram of the traditional SerDes interconnection structure between bare chips.

[0009] Figure 2 is Figure 1 a schematic diagram of the TX / RX signal channels within the bare chip in FIG.

[0010] Figure 3 FIG. is a schematic diagram of an embodiment of the SerDes interconnection structure between bare chips of the present invention.

[0011] Figure 4 FIG. is a schematic diagram of another embodiment of the SerDes interconnection structure between bare chips of the present invention.

[0012] Figure 5 is a schematic diagram of the TX / RX signal channels within the bare chip in the SerDes interconnection structure between bare chips of the present invention.

[0013] Figure 6 FIG. is a schematic diagram of still another embodiment of the SerDes interconnection structure between bare chips of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The present invention provides a SerDes interconnection structure between bare chips for SerDes interconnections between different bare chips (dies) within the same package or on a PCB after packaging. As shown in FIG., each bare chip 10 is arranged within the package or on the PCB after packaging in a set clockwise direction. Each bare chip 10 is provided with multiple pairs of TX / RX signal channels, where: each pair of TX / RX signal channels includes a TX pin, a calculation module 11, and an RX pin. The TX pin and the RX pin are located on the same side of the bare chip 10 (as shown in FIG. Figures 3 to 6 Figure 5 ​), so that positive data and reverse data can be transmitted between the bare chips 10 in a set clockwise direction. Among them, after the positive data is sent from the starting bare chip, it is directly transmitted to the ending bare chip in the set clockwise direction. After the reverse data is sent from the ending bare chip, it is transmitted to the starting bare chip in the set clockwise direction through all other bare chips except the starting bare chip and the ending bare chip (the number of bare chips here is the total number of bare chips minus 2). Here, the starting bare chip and the ending bare chip are two adjacent bare chips arranged in the set clockwise direction.

[0015] In the present invention, the corresponding English for the bare chip is die, also known as a chip or a bare die.

[0016] For the TX / RX signal channel, such as Figure 5 , the calculation module 11 is preferably arranged close to the TX pin and the RX pin. Such a structural design reduces the pipeline length of the TX / RX signal channel. Of course, the layout position of the calculation module 11 is not limited by the above, for example, it can also be arranged far from the TX pin and the RX pin.

[0017] Furthermore, the TX pin and the calculation module 11, and the RX pin and the calculation module 11 are connected through a pipeline 12. Of course, they can also be connected through other logic modules or signal lines. Such as Figure 5 , the figure shows the pipeline 12 connecting the TX1 pin, the RX1 pin and the calculation module 11, and the pipeline 12 connecting the TX2 pin, the RX2 pin and the calculation module 11.

[0018] In the present invention, the set clockwise direction is the clockwise direction or the counterclockwise direction. Of course, usually, it is customary to arrange the bare chips and transmit the positive data in the clockwise direction.

[0019] In actual application, the positive data is the main data, and the reverse data is the control data. The data volume of the control data is much smaller than that of the main data. Of course, the positive data and the reverse data can be various types of data without limitation. However, when the present invention transmits a large amount of main data as the positive data and a small amount of control data as the reverse data, the beneficial effect is more significant.

[0020] In actual design, the TX / RX signal channel layouts on the bare chips 10 arranged in the set clockwise direction are the same or different. In other words, the TX / RX signal channel layouts on the bare chips 10 can be the same or different. As long as the TX pin and the RX pin of each pair of TX / RX signal channels on each bare chip 10 are designed on the same side of the bare chip 10, the positive data and the reverse data can be transmitted between the bare chips 10 in the set clockwise direction.

[0021] For example, Figure 3and Figure 4 The TX / RX signal channel layouts on the bare chips 1 - 4 shown are the same ( Figure 3 and Figure 4 only 2 TX / RX signal channels are shown), where the TX pins and RX pins are on the same side of the bare chip 10, and the bare chips 1 - 4 are arranged in a clockwise direction according to custom. Based on the design concept of the present invention, the bare chips 1 - 4 achieve the transmission of forward data and reverse data in a clockwise direction. In Figure 3 and Figure 4 , the blue solid line and the red solid line show the two paths for transmitting forward data and reverse data. The forward data and the reverse data are simultaneously mixed and transmitted on these two paths to fully utilize all the bandwidths of these two paths and achieve the purpose of maximizing the bandwidth. Figure 3 , Figure 4 The double-dashed lines in Figure 3 and Figure 4 represent the data transmission paths realized by the TX / RX signal channels within the bare chips. Therefore, it can be seen from Figure 3 and Figure 4 that when the TX / RX signal channel layouts on each bare chip are the same, there is more than one way to transmit forward and reverse data in a clockwise direction. When the bare chip 10 is designed with more than 2 TX / RX signal channels, cross phenomena will occur in the SerDes interconnection between the bare chips 10, which can be realized through multi-layer substrate / PCB routing in practice.

[0022] Figure 6 The TX / RX signal channel layouts on the bare chips 1 - 4 shown are different ( Figure 6 only 2 TX / RX signal channels are shown), and this situation is not common. For example, compared with the TX pins and RX pins of the TX / RX signal channels on both sides of the bare chip 1, the TX pins and RX pins of the TX / RX signal channels on both sides of the bare chip 2 are upside down. However, the bare chips 1 - 4 are arranged in a clockwise direction and the TX pins and RX pins are located on the same side of the bare chip 10. Therefore, based on the design concept of the present invention, the bare chips 1 - 4 can still achieve the transmission of forward data and reverse data in a clockwise direction. It's just that when designing the substrate / PCB, it is necessary to rotate the bare chip 2 by 180 degrees relative to the bare chip 1 for layout implementation. In Figure 6 , the blue solid line and the red solid line show the two paths for transmitting forward data and reverse data. The forward data and the reverse data are simultaneously mixed and transmitted on these two paths to fully utilize all the bandwidths of these two paths and achieve the purpose of maximizing the bandwidth. Figure 6The double-dashed line therein represents the data transmission path realized by the TX / RX signal channels within the bare chip. Similarly, when the TX / RX signal channel layouts on each bare chip are inconsistent, there is more than one way to transmit the forward and reverse data in the clockwise direction. When the bare chip 10 is designed with more than 2 TX / RX signal channels, cross phenomena will occur in the SerDes interconnection between the bare chips 10, which can also be realized by multi-layer substrate / PCB routing in practice.

[0023] Based on the above design of the present invention, such as Figure 3 , Figure 4 and Figure 6 , taking the SerDes interconnection of four bare chips as an example, the forward data is transmitted in the clockwise direction, that is, bare chip 1, bare chip 2, bare chip 3, bare chip 4, bare chip 1, and the reverse data is also transmitted in the clockwise direction, that is, bare chip 1, bare chip 2, bare chip 3, bare chip 4, bare chip 1. Further, if it is assumed that the bare chip 1 is the starting bare chip and the bare chip 2 is the ending bare chip, then the forward data is directly transmitted to the bare chip 2 in the clockwise direction after being sent from the bare chip 1, while the reverse data needs to be transmitted to the bare chip 1 after passing through the bare chip 3 and the bare chip 4 in the clockwise direction after being sent from the bare chip 2.

[0024] The reason why the present invention can achieve the above transmission method is that the control logic within the bare chip is changed so that the reverse data can be transmitted in the same direction as the forward data transmission direction, that is, if the forward data is transmitted in the clockwise direction, the reverse data is also transmitted in the clockwise direction. Here, the change of the control logic within the bare chip is as Figure 5 shown, that is, the TX pin and the RX pin belonging to the same TX / RX signal channel are located on the same side of the bare chip 10. More preferably, the calculation module 11 is arranged close to the TX pin and the RX pin, which has been described in detail above.

[0025] From Figure 3 , Figure 4 and Figure 6 it can be seen that compared with the traditional SerDes interconnection between bare chips, when the reverse data is a small amount of control data, the present invention obviously improves the bandwidth utilization rate of the SerDes interconnection. However, this transmission path of the present invention obviously has a longer transmission distance and a greater delay when transmitting the reverse data, and occupies more SerDes bandwidth (because there are more bare chips crossed). However, when transmitting a small amount of control data, since the amount of control data is extremely small compared with a large amount of main data, the overall bandwidth overhead is very small and has almost no impact on the system performance.

[0026] At the same time, by comparing the on-chip designs of Figure 2 and Figure 5 , it can be found that for Figure 2In the traditional method shown, data will pass through two pipelines 12 within the chip and be transmitted across the entire bare chip, which takes a long time and is more obvious when the area of the bare chip is large. As Figure 2 , the figure shows the pipeline 12 connecting the TX1 pin, RX1 pin and the computing module 11, and the pipeline 12 connecting the TX2 pin, RX2 pin and the computing module 11. However, the present invention changes the in-chip data transmission path. That is, after the data enters the bare chip, it no longer crosses the entire bare chip, but is directly output from the TX pin on the same side of the bare chip as the RX pin. The pipeline length of the TX / RX signal channel is greatly reduced, that is, the data transmission path is significantly shortened and the delay is smaller, which is more obvious when the area of the bare chip is large. In addition, although the length of the substrate / PCB trace outside the bare chip is longer than that of the traditional method, only the wire delay is involved outside the chip, and there is no delay of devices (such as buffers, inverters, flip-flops, etc.) and cross-clock domain overhead. Therefore, the data transmission speed achieved by the present invention will be faster and the data transmission delay will be smaller. On the contrary, the system performance is improved. In short, the present invention improves the bandwidth utilization rate and system performance and reduces the delay.

[0027] Based on the above-mentioned SerDes interconnection structure between bare chips of the present invention, the present invention also proposes a method for SerDes interconnection between bare chips. Specifically, when each bare chip 10 is arranged in the package or on the PCB after packaging in a set clockwise direction, positive data and reverse data are also transmitted between each bare chip 10 in the set clockwise direction. Among them, the positive data is directly transmitted from the starting bare chip to the ending bare chip in the set clockwise direction, and the reverse data is transmitted from the ending bare chip to the starting bare chip in the set clockwise direction after passing through all other bare chips (the number of bare chips here is the total number of bare chips minus 2) except the starting bare chip and the ending bare chip. Here, the starting bare chip and the ending bare chip are two adjacent bare chips arranged in the set clockwise direction. The set clockwise direction is the clockwise direction or the counterclockwise direction.

[0028] The beneficial effects of the present invention are as follows: Compared with the traditional SerDes interconnection between bare chips, the present invention improves the bandwidth utilization rate, improves the system performance and has a lower delay by changing the layout of the TX / RX signal channel within the bare chip and redefining the data transmission direction between bare chips. The present invention is applicable to SerDes interconnection between different bare chips (dies) in the same package or on the PCB after packaging, and is not limited by scale. The beneficial effects are more significant when used for large-scale SerDes interconnection, and it is particularly applicable to the transmission mode with unbalanced bandwidth and the pursuit of maximum bandwidth.

[0029] The above is a preferred embodiment of the present invention and the technical principles applied therein. For those skilled in the art, any obvious changes such as equivalent transformations and simple substitutions based on the technical solution of the present invention without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention.

Claims

1. A bare chip SerDes interconnection structure, used for SerDes interconnection between different bare chips in the same package or on a packaged PCB, characterized in that: The bare chips are arranged in a set clockwise direction, and each bare chip is provided with a plurality of pairs of TX / RX signal channels, wherein: each pair of the TX / RX signal channels comprises a TX pin, a computing module and an RX pin, and the TX pin and the RX pin are located on the same side of the bare chip, so that forward data and reverse data can be transmitted between the bare chips in a set clockwise direction, wherein the forward data is directly transmitted to the end point bare chip in a set clockwise direction after being sent from the starting bare chip, and the reverse data is transmitted to the starting bare chip in a set clockwise direction after passing through all other bare chips except the starting bare chip and the end point bare chip.

2. The SerDes interconnect structure between bare chips according to claim 1, characterized in that: For the TX / RX signal channel, the calculation module is arranged close to the TX pin and the RX pin, wherein the calculation module is inside the bare chip.

3. The SerDes interconnect structure between bare chips as claimed in claim 2, characterized in that: The TX pin and the computing module, and the RX pin and the computing module are connected via a pipeline.

4. The SerDes interconnect structure between bare chips according to claim 1, characterized in that: The set clockwise direction is clockwise or counterclockwise.

5. The SerDes interconnect structure between bare chips according to claim 1, characterized in that: The forward data is main data, and the reverse data is control data. The amount of the control data is smaller than the amount of the main data.

6. The SerDes interconnect structure between bare chips according to claim 1, characterized in that: The layouts of the TX / RX signal channels on the bare chips arranged in a set clockwise direction are consistent or different.

7. A bare chip SerDes interconnection method implemented based on the bare chip SerDes interconnection structure according to any one of claims 1 to 6, characterized in that: When the bare chips are arranged in the package body or on the packaged PCB according to a set clockwise direction, the forward data and the reverse data are transmitted between the bare chips according to the set clockwise direction.

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