Simulation method for dynamically adjusting netlist configuration based on key event node

Abstract

A simulation method for dynamically adjusting netlist configuration based on key event nodes is used for simulation of chips such as a generic analog chip, a digital-analog hybrid chip and a multi-core heterogeneous chip and comprises the steps that a plurality of key event nodes are preset in the simulation process according to the types of the chips, and the key event nodes are used for dynamically adjusting netlist configuration after chip power-on simulation is completed or a chip clock is stable; setting nodes according to the key event selected by the user; determining netlist configuration of a function module of each key event node based on preset key event nodes; and when the simulation process reaches a certain key event node, dynamically adjusting the netlist of the functional module according to preset netlist configuration. According to the simulation method, aiming at the problems of low simulation speed and lack of flexibility in the simulation process in a traditional chip simulation method, the invention innovatively proposes that the netlist configuration in the simulation process is dynamically adjusted through the key trigger event node, so that the simulation speed of the chip is greatly improved, the accuracy of a simulation result is ensured, and the simulation efficiency is improved. And the flexibility of the simulation process is enhanced.

Description

Technical Field

[0001] This application relates to the field of electronic design automation (EDA), and particularly to a simulation method for dynamically adjusting netlist configuration based on key event nodes. Background Art

[0002] With the continuous increase in the scale and complexity of integrated circuit design, a large number of data files need to be processed in the design process. Due to the huge amount of data, reading and processing these files often become the bottleneck of system performance.

[0003] In the fields of mixed-signal chips, large-scale storage chips, high-precision high-speed analog chips, general analog chips (analog, radio frequency, silicon photonics, optoelectronics, MEMS, computing, third-generation wide bandgap, radio frequency, etc.), multi-core heterogeneous chip systems with two or more cores, etc., as the chip scale expands day by day, the speed problem of chip simulation (mixed-signal simulation) becomes more prominent. Especially when the circuit contains high-frequency oscillation modules such as OSC (oscillator) and PLL (phase-locked loop), the simulation process becomes extremely slow. In addition, the design complexity of modern chips is extremely high. The number of MOS transistors in some modules even exceeds 10k, and it may take hundreds or even about 20k simulation cycles to complete a specific function. At the same time, various modes such as mixed-signal interaction control, calibration, and DFT (design for testability) make the chip configuration modes reach more than a hundred, or even 300 - 400 kinds. Such complex mixed-signal configurations are extremely likely to cause errors in chip design.

[0004] In the current mixed-signal simulation method, if the analog part is completely simulated using circuit schematics, the simulation speed will be severely affected; if the model-based verification method is used, an accurate model needs to be established and it is necessary to ensure that the model can accurately reflect the behavior of the circuit schematic. Summary of the Invention

[0005] To solve the defects of the prior art, the purpose of this application is to provide a simulation method for dynamically adjusting netlist configuration based on key event nodes. Aiming at the problems of slow mixed-signal simulation speed, difficult to guarantee model accuracy, and lack of flexibility in the simulation process in the prior art, during the simulation process, the netlist configuration in the simulation process is dynamically adjusted by triggering key event nodes. Without establishing an accurate model, the simulation speed can be improved, the accuracy of the simulation results can be ensured, and the flexibility of the simulation process can be enhanced.

[0006] To achieve the above purpose, the simulation method for dynamically adjusting netlist configuration based on key event nodes provided by this application includes the following steps:

[0007] According to the chip type, multiple key event nodes are preset in the simulation process. The key event nodes are nodes set according to the key events selected by the user after the power-on simulation of the chip is completed or the chip clock is stable.

[0008] Based on the preset key event nodes, determine the netlist configuration of the functional modules of each key event node.

[0009] When the simulation process reaches a certain key event node, dynamically adjust the netlist of the functional module according to the preset netlist configuration.

[0010] Further, the chip types include: general analog chips, mixed-signal chips, and multi-core heterogeneous chips.

[0011] Further, the step of determining the configuration of the functional modules of each key event node based on the preset key event nodes further includes: receiving the selection of the user and determining the netlist configuration of the functional modules of each preset key event node.

[0012] Furthermore, the netlist configuration includes: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model, C model, simplified circuit diagram, Protocol model, criticalpart model.

[0013] To achieve the above object, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor is used to execute the computer program stored in the memory to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on the key event nodes as described above.

[0014] To achieve the above object, the present application also provides a computer-readable storage medium. A computer program is stored in the storage medium, and the computer program is loaded and executed by the processor to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on the key event nodes as described above.

[0015] The simulation method for dynamically adjusting the netlist configuration based on the key event nodes provided by the present application has the following beneficial effects compared with the prior art:

[0016] 1) Significantly improves the simulation speed: By dynamically adjusting the netlist configuration in the simulation process when triggering the key event nodes, unnecessary computational overhead is reduced, thereby greatly shortening the simulation time and improving the design verification efficiency.

[0017] 2) Ensured the accuracy of simulation results: During the simulation process, models with different precisions were dynamically switched according to actual requirements to ensure that accurate circuit schematic views and post-simulation netlist simulations were used during critical verification phases, while model (such as.v model,.vams model, etc.) simulations were switched to during phases where speed needed to be increased. This not only accelerated the simulation process but also improved the simulation accuracy.

[0018] 3) Enhanced the flexibility of the simulation process: Dynamically adjusting the netlist configuration during the simulation process (dynamic netlist simulation technology) allows for flexible adjustment of the netlist configuration according to the actual working phases and verification requirements of the circuit during the simulation process. It can be switched from circuit schematic (Schematic) simulation to model (Model), or from model (Model) to circuit schematic (Schematic) simulation. In short, free switching of the dynamic netlist can be performed among models such as schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model, C model, simplified circuit diagram, Protocol model, critical part model, etc. This makes the simulation process closer to real application scenarios and improves the effectiveness and pertinence of verification.

[0019] By establishing a dynamic netlist simulation system, the present invention enables different configuration views (config view) to be used in the same simulation process. In this way, within the verification scope that designers are concerned about, the most accurate circuit schematic view can be adopted for precise verification; while when a large number of scenarios need to be quickly verified or the simulation performance needs to be optimized, it can be flexibly switched to other simplified models, such as.v model,.vams model,.sv model, real number model (RNM), etc., thereby greatly improving the simulation efficiency, significantly reducing the R & D cost, effectively shortening the R & D cycle, and improving the R & D quality.

[0020] Other features and advantages of the present application will be described in the subsequent specification, and some of them will become obvious from the specification or be understood by implementing the present application. Description of the Drawings

[0021] The drawings are used to provide further understanding of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation to the present application. In the drawings:

[0022] Figure 1 It is a flowchart of a simulation method for dynamically adjusting netlist configuration based on key event nodes according to Embodiment 1 of the present application;

[0023] Figure 2 Schematic diagram of dynamically adjusting netlist configuration based on key event nodes according to an embodiment of the present application;

[0024] Figure 3 Block diagram of a digital - analog hybrid SOC chip according to an embodiment of the present application;

[0025] Figure 4 Flowchart of a simulation method for dynamically adjusting netlist configuration based on key event nodes according to Embodiment 2 of the present application;

[0026] Figure 5 Schematic diagram of application types and scenarios of a simulation method for dynamically adjusting netlist configuration based on key event nodes according to an embodiment of the present application;

[0027] Figure 6 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0028] The following describes the preferred embodiments of the present application with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for the purpose of illustration and explanation of the present application, and are not used to limit the present application.

[0029] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0030] The term "including" and its variations used herein are open - ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0031] It should be noted that the concepts such as "first" and "second" that may be mentioned in the present application are only used to distinguish different devices, components or parts, and are not used to limit the order of functions performed by these devices, components or parts or their interdependent relationships.

[0032] It should be noted that the modifiers "one" and "multiple" that may be mentioned in the present application are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.

[0033] It should be noted that the chips mentioned in this application can be analog chips, general-purpose analog chips, mixed-signal chips, multi-core heterogeneous chips, etc.

[0034] Embodiment 1

[0035] In current chip simulation, if the analog part is completely simulated using circuit schematics, the simulation speed will be severely affected; while if the Model Based verification method is used, an accurate model needs to be established and it is ensured that the model can accurately reflect the behavior of the circuit schematic. In the actual simulation process, the following problems exist:

[0036] 1) In large chips, modules such as OSC, PLL, and GPIO are common modules, but they severely slow down the simulation speed. In addition, current Verilog models (.v files), VerilogAMS models (.vams files), and SystemVerilog models (.sv files) are usually generated manually, making it difficult to ensure complete matching with the circuit schematic (Schematic). When the circuit design is updated, the model often cannot be updated in a timely manner.

[0037] 2) Currently, all simulation processes determine the netlist at the beginning and keep it unchanged throughout the simulation process. However, the modules that a real SOC focuses on are different at different working stages of the chip. Therefore, if the same netlist and view list are used throughout the process, the circuit schematic may slow down the simulation speed, or the model may not be able to truly reflect the nodes of concern.

[0038] It is worth noting that currently all simulators globally, whether pure analog simulation, digital simulation, or mixed-signal simulation, use the same netlist at the beginning of the simulation and do not modify it throughout the simulation process.

[0039] To address the above problems, the simulation method based on dynamically adjusting the netlist configuration at key event nodes in this application uses the key event nodes of the simulation: E0, E1, E2, E3... En as the key trigger points for switching the netlist. When the simulation process reaches the preset key event nodes, the system automatically adjusts to the netlist configuration (Config). Different functional modules can switch from circuit schematic (Schematic) simulation to model (Model) simulation, or from model (Model) simulation to circuit schematic (Schematic) simulation, which can improve the simulation speed and accuracy of the chip.

[0040] Figure 1The following is a flowchart of a simulation method for dynamically adjusting netlist configuration based on key event nodes according to Embodiment 1 of the present application. Reference will be made to Figure 1 to describe in detail the simulation method for dynamically adjusting netlist configuration based on key event nodes of the present application.

[0041] First, in step 101, the chip type is confirmed, and multiple key event nodes are preset in the simulation process as key trigger points for dynamically adjusting the netlist configuration.

[0042] In the embodiment of the present application, according to the type of the chip, multiple key event nodes: E0, E1, E2, E3,..., En are set in the chip simulation process as key trigger points for adjusting the netlist configuration. As Figure 2 shown, when the simulation process reaches the preset key event node, the system automatically switches to the corresponding netlist configuration, where different modules will perform operations using netlists at different model levels.

[0043] In the embodiment of the present application, between two adjacent key event nodes, different simulation stages are configured. Multiple key event nodes can be preset in the simulation process to simulate different functional modules of the chip at different key event nodes.

[0044] In the embodiment of the present application, according to the type of the chip, the functional modules can be divided into: functional modules related to power-on, functional modules related to power supply, functional modules related to clock, functional modules related to signal processing, functional modules related to data processing, functional modules related to signal conversion, functional modules related to storage, functional modules related to communication, functional safety modules, monitoring and protection functional modules, etc., where:

[0045] Functional modules related to power-on include, but are not limited to: bandgap reference voltage source BG, reference voltage source BG, bias current source lbias, etc.;

[0046] Functional modules related to power supply include, but are not limited to: reference voltage source, reference current source, under-voltage protection UVLO, power-on detection POR, voltage regulator, charge pump Charge Pump, etc.;

[0047] Functional modules related to clock include, but are not limited to: oscillator, PLL phase-locked loop, external crystal oscillator, low-frequency oscillator, high-frequency oscillator, etc.

[0048] Functional modules related to signal processing include, but are not limited to: signal generator, amplifier circuit, feedback circuit, filter circuit, coupling circuit, etc.;

[0049] Functional modules related to data processing include, but are not limited to: arithmetic circuit, etc.

[0050] Function modules related to signal conversion, including but not limited to: analog-to-digital converters, digital-to-analog converters, etc.;

[0051] Function modules related to storage, including but not limited to: Memory Array, SRAM, DRAM, Sense amplifier, driving circuits, etc.;

[0052] Function modules related to communication include but not limited to: wireless communication modules (such as Wi-Fi modules, ZigBee modules, Bluetooth modules, etc.), wired communication modules (such as Ethernet modules, serial communication modules, CAN bus modules, etc.), and dedicated communication modules (such as LoRa modules, NB-IoT modules, etc.). In step 102, based on preset key event nodes, the netlist configuration of the function modules for each key event node is determined.

[0053] In the embodiments of the present application, first, according to the type of the chip, the types and quantities of the function modules in the chip are confirmed. For example, in a mixed-signal SOC chip, it has an analog schematic part and also digital design parts such as RTL / Gate. Among them, in the analog circuit, there are modules related to power-on, such as a bandgap reference voltage source BG, a reference voltage source BG, a bias current source lbias, a power-on monitoring module POR, etc.; and an oscillator with a relatively low operating frequency (such as 32 kHz) that helps with deglitching; and a high-frequency oscillating OSC (such as 16 MHz) that provides a high-speed clock, and a high-frequency PLL (such as 160 MHz). The mixed-signal SOC chip also includes various communication interfaces, such as general-purpose input / output ports (GPIO), I2C, SPI, and HDMI interface modules. The mixed-signal SOC chip also covers various function modules, such as key function modules like impedance detection, analog-to-digital converter ADC, digital-to-analog converter DAC, programmable gain amplifier PGA (Programmable Gain Amplifier), trans-impedance amplifier TIA (Trans-Impedance Amplifier), power amplifier PA, etc.; and modules related to Function Safety.

[0054] In the embodiments of the present application, multiple key event nodes can be set during the simulation process of the chip. The key event nodes can be set by the user after the power-on simulation of the chip is completed and the clock is stable according to the progress of the simulation.

[0055] It can be understood that in the embodiments of the present application, the moment when the power-on related circuits of the chip (such as the reference voltage source BG, bias current source, power-on monitoring module, low-frequency oscillator, etc.) finish simulation and 10 additional low-frequency oscillation periods are completed can be selected as the key event node to adjust the netlist configuration of the power-on related circuits and change the power-on related netlist configuration.

[0056] It can be understood that in the embodiments of the present application, the moment when the high-frequency OSC (such as 16 MHz) and PLL loop of the chip finish simulation and 10 additional PLL oscillation periods are completed can be selected as the key event node to adjust the netlist configuration of the power-on related circuits and change the power-on related netlist configuration.

[0057] It can be understood that in the embodiments of the present application, the moment when the ADC module of the chip finishes simulation and 10 additional PLL oscillation periods are completed can be selected as the key event node to adjust the netlist configuration of the power-on related circuits and change the power-on related netlist configuration.

[0058] It can be understood that in the embodiments of the present application, the moment when the analog function module (such as impedance detection circuit) of the chip finishes simulation and 10 additional PLL oscillation periods are completed can be selected as the key event node to adjust the netlist configuration of the power-on related circuits and change the power-on related netlist configuration.

[0059] In step 103, start the simulation and when the simulation process reaches a certain key event node, dynamically adjust the netlist of the function module according to the preset netlist configuration.

[0060] In the embodiments of the present application, the netlist configuration includes but is not limited to: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model (RNM), C model, simplified circuit diagram, Protocolmodel, critical part model.

[0061] In the embodiments of the present application, taking the simulation of a mixed-signal chip as an example, the reference voltage source BG, the bias current source lbias, and the power-on monitoring module POR use.vams (Verilog-AMS) models. At the same time, a.v (Verilog) model is used for the 32kHz low-frequency OSC; the modules related to high-frequency oscillation are changed to the digital domain, and.v models are used for the high-frequency OSC and the ultra-high-frequency PLL to ensure that all the circuits they are connected to are digital signals, no longer analog signals; for general GPIO / I2C / SPI / HDMI and other modules, according to the actual chip design requirements, a.v model, a.vams model, or a model at the RNM (Real number model) level can be used; the impedance detection module is replaced with a.vams model, the ADC module is changed from a transistor-level circuit to a.vams model, and the analog-related modules on the signal chain such as PGA and TIA are also replaced with.vams models; finally, all the analog modules in the circuit are replaced with.v (verilog) models.

[0062] Embodiment 2

[0063] Figure 4 FIG. is a simulation flowchart for dynamically adjusting netlist configuration based on key event nodes according to Embodiment 2 of the present application. The following will refer to Figure 4 to describe in detail the simulation process of dynamically adjusting netlist configuration based on key event nodes in the embodiments of the present application.

[0064] In the embodiments of the present application, taking a mixed-signal SOC chip as an example, the simulation method for dynamically adjusting netlist configuration based on key event nodes of the present application is described in detail.

[0065] Figure 3 FIG. is a structural block diagram of a mixed-signal SOC chip according to the embodiments of the present application, as Figure 3As shown, the digital-analog hybrid SOC chip of the present application includes an analog circuit part and also has digital circuit parts such as RTL / Gate. In the analog circuit, there are power-on related modules, such as a bandgap reference voltage source BG, a reference voltage source BG, a bias current source lbias, a power-on monitoring module POR, etc.; and an oscillator with a lower operating frequency (such as 32 kHz) to help with deglitching (pulses); and a high-frequency oscillator OSC (such as 160 MHz) that provides a high-speed clock, and a high-frequency phase-locked loop PLL (such as 160 MHz). The digital-analog hybrid SOC chip also includes various communication interfaces, such as general-purpose input / output ports (GPIO), I2C, SPI, and HDMI interface modules. The chip also covers various functional modules, such as key functional modules like an impedance detection module (impedance detection), an analog-to-digital converter ADC, a digital-to-analog converter DAC, a programmable gain amplifier PGA, a transimpedance amplifier TIA, a power amplifier PA, etc.; and modules related to automotive reliability such as Function Safety.

[0066] To meet the demand for improving simulation speed and address a wide range of application scenarios and diverse simulation verification requirements, we propose a new module-based hierarchical structure system and a simulation method that enables dynamic switching of netlist configurations at key event nodes. This system gives users great flexibility. Users can, according to actual needs, flexibly select the most appropriate view for each independent block (whichever view the different small blocks want to select, they can select), and then achieve free combinations of various configurations to meet different simulation scenarios. By dynamically adjusting the netlist form of the selected module (dynamically changing the netlist form of the selected block), using the simulation method of dynamically switching netlist configurations at key event nodes, the adaptability and efficiency of the simulation can be significantly improved, ensuring that the simulation process is both efficient and accurate.

[0067] 1. At the initial moment: Check the circuit related to power-on.

[0068] At this key event moment, which is the initial simulation stage, the entire analog IC schematic circuit diagram is used; thus ensuring that all simulations are in the most realistic situation. Especially during the power-on stage, through the simulation of the real circuit, check whether there is abnormal leakage in the circuit related to power-on, whether it can resist interference on the power supply line, whether the reference voltage source BG and the bias current source lbias can start normally, whether the power-on monitoring module POR and other modules can normally monitor the power supply voltage information, etc. Whether the low-frequency oscillator OSC can start normally and whether it can output a clock signal with the correct power level, etc.

[0069] 2. At the critical event moment (E1) completed within 10 low-frequency oscillation periods after the POR signal goes high, adjust the netlist configuration of the power-on related circuits.

[0070] At this critical event moment, the power-on monitoring of the circuit has been completed and it is shown that normal power-on is possible. The reference voltage source BG and the bias current source lbias can stably output the expected reference voltage and reference current values respectively; meanwhile, the low-frequency oscillator OSC can stably output a periodic square wave.

[0071] In the embodiment of the present application, at the critical event moment completed within 10 low-frequency oscillation periods after the POR signal goes high, the entire simulation system starts to change the netlist configuration related to power-on. Use the.vams (Verilog-AMS) model for the reference voltage source BG, the bias current source lbias, and the power-on monitoring module POR, and use the.v (Verilog) model for the 32kHz low-frequency OSC. Thereby, the simulation of the power-on related modules is accelerated, the number of simulated transistors is reduced, and the simulation speed is increased.

[0072] In the simulation after changing the netlist configuration related to power-on in the embodiment of the present application, the key points are to check whether the high-frequency OSC (such as 160MHz) starts to oscillate and whether the output is normal; and whether it can drive the high-frequency PLL (such as 160MHz) to work properly, whether the PLL loop is stable, whether it can stably output a high-frequency signal, and whether the PLL can be locked, etc.

[0073] 3. At the critical event moment (E2) completed within 10 PLL oscillation periods after the PLL Lock signal goes high, adjust the netlist configuration of the modules related to high-frequency oscillation.

[0074] At this critical event moment, the high-frequency OSC has been able to stably output the correct 160MHz signal, and the Lock signal of the PLL module has also been sent for several cycles. The PLL outputs the expected 160MHz high-frequency clock. At the same time, interface communication modules, such as GOIO, I2C, SPI, HDMI, etc., have been able to communicate normally, and in the simulation, it is found that their delays are the same as the trend of the individual Block simulation, and they can communicate normally with the digital logic control module through the Buffer according to the control.

[0075] In the embodiments of the present application, at the critical event moment completed within 10 PLL oscillation periods after the PLL Lock signal goes high, for example, at the moment of 1300 us, the system continues to dynamically change the netlist, changing the modules related to high-frequency oscillation to the digital domain, using the.v model for high-frequency OSC and ultra-high-frequency PLL to ensure that all the circuits they are connected to are digital signals rather than analog signals; while for general GPIO / I2C / SPI / HDMI and other modules, according to the actual chip design requirements, the.v model or.vams, or models at the RNM (Real number model) level can be used. Since then, in all chips, the high-frequency signals that greatly affect the calculation of the analog simulator and thus slow down the entire mixed-signal simulation speed have had their netlist configurations changed, no longer using the transistor-level schematic view, but instead using different-level models such as.v and.vams, which speeds up the simulation.

[0076] After changing the netlist configuration, the circuit continues to operate. After waiting for several PLL cycles and the circuit stabilizes, some important analog function modules can be enabled, such as enabling the impedance detection circuit.

[0077] In the embodiments of the present application, a hierarchical structure based on different blocks can be constructed according to the simulation verification requirements. Different small blocks can select views according to the requirements, thereby realizing different combinations of various configurations (config).

[0078] 4. At the critical event moment (E3) completed within 10 PLL oscillation periods after the impedance detection is completed, adjust the netlist configuration of the impedance detection module.

[0079] At this critical event moment, through the transistor-level circuit of the linear regulator LDO based on the circuit schematic diagram, and the transistor-level circuit of the impedance detection module that is turned on, combined with a suitable excitation source, different configurations (such as accuracy and calibration, etc.) of the impedance detection circuit, measurements of different detection ranges, etc. have been completed. For example, noise has also been turned on / off in the middle, and the circuit performance of the impedance detection module under the influence of noise has been obtained; even in some chip designs, the module can be turned off functionally, so when it is disabled, the output may be in a stable or high-impedance state, which will not cause a large drag on the simulation speed; at this time, the functional performance simulation of the impedance detection circuit module has been completed.

[0080] In the embodiments of the present application, at the critical event moment completed within 10 PLL oscillation periods after the impedance detection is completed, the impedance detection module is replaced with the.vams model, no longer using the transistor level; further reducing the complexity of analog / mixed-signal simulation.

[0081] In the embodiment of the present application, after changing the netlist configuration of the impedance detection module, the circuit continues to operate. After waiting for several PLL cycles until the circuit stabilizes, the functions of the ADC module can be started and checked.

[0082] 5. At the critical event moment (E4) completed within 10 PLL oscillation cycles after the simulation of all functions of the ADC is completed, adjust the netlist configuration related to the ADC module.

[0083] At this critical event moment, through the LDO transistor-level circuit based on the circuit schematic diagram, the turned-on ADC transistor-level circuit, and the cooperation of a suitable excitation source, different configurations and different calibration schemes of the ADC have been completed. At the same time, for different analog input signals, such as signals transmitted from modules such as a programmable gain amplifier (PGA) or a transimpedance amplifier (TIA), after passing through the ADC circuit module, the converted digital signals can be checked through simulation to see if they are correct and whether their functional performance meets the expectations. At this time, the relevant simulation of the ADC has been completed.

[0084] In the embodiment of the present application, at the critical event moment completed within 10 PLL oscillation cycles after the simulation of all functions of the ADC is completed, the system continues to change the netlist, replacing the ADC module from the transistor-level circuit with a.vams model, and even replacing the analog-related modules on the signal chain such as the PGA and TIA with.vams models, no longer using the transistor level, further reducing the complexity of the analog / digital mixed simulation.

[0085] In the embodiment of the present application, after changing the netlist, the circuit continues to operate. After waiting for several PLL cycles until the circuit stabilizes, the functions of the remaining analog modules are started and checked.

[0086] 6. At the critical event moment (E5) completed within 10 PLL oscillation cycles after the simulation of all analog-related modules is completed, adjust the netlist configuration of all analog function modules in the circuit.

[0087] At this critical event moment, the functional performance of all analog function modules that need to be verified in the analog / digital mixed simulation has been verified. However, there are still a large number of complex functions in the pure digital part, such as automotive function verification (Function Safety), etc.

[0088] In the embodiment of the present application, at the critical event moment completed within 10 PLL oscillation cycles after the simulation of all analog-related modules is completed, all analog function modules in the circuit are replaced with.v (Verilog) models, thus completely changing the analog / digital mixed simulation into a pure digital simulation.

[0089] In the embodiment of the present application, after the netlist is changed, the circuit continues to operate. After waiting for several PLL cycles and the circuit stabilizes, pure digital simulation can be performed under pure digital and Boolean operations. Since there are no analog modules in the circuit, the speed will be very fast. The system verifies digital functions, such as key functions like automotive functional safety, to ensure that the system meets the design requirements in terms of both function and safety. Since the digital netlist configurations at this time are all obtained through successive simulations at the analog circuit level before, they are very accurate, thus greatly reducing the risk of errors in manual configuration and enjoying high-speed simulation under a pure digital simulator.

[0090] The simulation method for dynamically adjusting the netlist configuration based on key event nodes in the present application controls the dynamic switching of the netlist through preset key event nodes to meet the requirements of different simulation stages, thereby improving the simulation efficiency and accuracy and effectively avoiding accuracy problems and version updates that may be brought about by directly using the Model.

[0091] The simulation method for dynamically adjusting the netlist configuration based on key event nodes in the present application is also applicable to the dynamic simulation of general analog circuits, especially those with large scale and complex structures (in this scenario, subsequent steps such as key event node T5 can be omitted). In addition, for application scenarios such as large-capacity storage circuits, dynamically modifying the netlist configuration can also play an excellent role. Through this method, we can adjust the netlist in real time during the simulation process, thereby greatly accelerating the simulation verification process, shortening the product R & D cycle, and effectively reducing the R & D cost.

[0092] The simulation method for dynamically adjusting the netlist configuration based on key event nodes in the present application is also applicable to the dynamic simulation of multi-core heterogeneous chips. A multi-core heterogeneous chip integrates multiple different types of processor cores, which come from different processes, adopt different instruction set architectures (ISAs), and have different performance characteristics and power consumption requirements. Common heterogeneous multi-core chips include high-performance general-purpose processor cores and dedicated cores designed for specific tasks, such as graphics processing units (GPUs), digital signal processors (DSPs), or neural network processors (NPUs), etc.

[0093] For the simulation of processor cores of multiple cross-process platforms in a multi-core heterogeneous chip, such as a multi-core heterogeneous chip having N1, N2, N3... Nn processor cores, and each processor core coming from a different process, etc., during the simulation, different configs can be used to change the netlist of the processor core through different key event nodes to achieve dynamic replacement of the netlist during the simulation process, thereby accelerating or verifying different work contents for different stages.

[0094] Figure 5Schematic diagram of the application type and scenario of the simulation method for dynamically adjusting netlist configuration based on key event nodes according to an embodiment of the present application, as Figure 5 shown, the simulation method for dynamically adjusting netlist configuration based on key event nodes according to an embodiment of the present application is applicable to chip types and scenarios, including general analog chips, mixed-signal chips, and multi-chips on multi-core heterogeneous / cross-process platforms (newly added), etc. For different simulation verification purposes, at selected key event nodes, config / model can be automatically switched. For example, most of the time, VerilogAMS, RNM, etc. can be selected to simplify the simulation. Also, according to actual needs, some important functional modules can be changed to post-simulation netlists and accurately simulated after power-on.

[0095] Embodiment 3

[0096] In an embodiment of the present application, a dynamic simulation method for multi-core heterogeneity is also provided. For example, in the simulation of a cross-process platform, there are N1, N2, N3... Nn chips, and each chip comes from a different process, etc. During the simulation, at key event nodes, different configs can be used to achieve dynamic replacement of netlists during the simulation process, so as to accelerate or verify different work contents for different stages.

[0097] Embodiment 4

[0098] In an embodiment of the present application, an electronic device is also provided. Figure 6 Schematic diagram of the structure of the electronic device according to an embodiment of the present application, as Figure 6 shown, the electronic device of the present application includes a processor 601 and a memory 602, wherein

[0099] the memory 602 stores a computer program, and when the computer program is read and executed by the processor 601, it executes the steps in the above-mentioned embodiment of the simulation method for dynamically adjusting netlist configuration based on key event nodes.

[0100] Embodiment 5

[0101] In an embodiment of the present application, a computer-readable storage medium is also provided. The computer-readable storage medium stores a computer program, and the computer program is configured to execute the steps in the above-mentioned embodiment of the simulation method for dynamically adjusting netlist configuration based on key event nodes when running.

[0102] In this embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0103] Those of ordinary skill in the art can understand that the above are only preferred embodiments of the present application and are not used to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A simulation method for dynamically adjusting netlist configuration based on key event nodes, comprising the following steps: According to the chip type, multiple key event nodes are preset in the simulation process. The key event nodes are nodes set according to the key events selected by the user after the chip power-on simulation is completed or the chip clock is stable; Based on the preset key event nodes, determine the netlist configuration of the functional modules of each key event node; When the simulation process reaches a certain key event node, the netlist of the functional module is dynamically adjusted according to the preset netlist configuration.

2. The simulation method for dynamically adjusting netlist configuration based on key event nodes according to claim 1, characterized in that: The chip types include: pan-analog chips, digital-analog hybrid chips, and multi-core heterogeneous chips.

3. The simulation method for dynamically adjusting netlist configuration based on key event nodes according to claim 1, characterized in that: The step of determining the configuration of each key event node functional module based on the preset key event node also includes: receiving a user's selection and determining the netlist configuration of each preset key event node functional module.

4. The simulation method for dynamically adjusting netlist configuration based on key event nodes according to claim 1, characterized in that: The netlist configuration includes: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, RealNumber Model, C model, simplified circuit diagram, Protocolmodel, and critical part model.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor is used to execute the computer program stored in the memory to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on key event nodes as described in any one of claims 1-4.

6. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which is loaded and executed by a processor to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on key event nodes as described in any one of claims 1 to 4.

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