Simulation method for dynamically adjusting netlist configuration based on time nodes

Abstract

A simulation method for dynamically adjusting netlist configuration based on time nodes is used for simulation of chips such as a generic analog chip, a digital-analog hybrid chip and a multi-core heterogeneous chip, and comprises the following steps: presetting a plurality of time nodes in a simulation process according to chip types; determining netlist configuration of the function module of each time node based on preset time nodes; and when the simulation process reaches a certain time node, dynamically adjusting the netlist of the functional module according to preset netlist configuration. According to the simulation method for dynamically adjusting the netlist configuration based on the time node, aiming at the problems that the simulation speed is low and the simulation process is lack of flexibility in a traditional chip simulation method, the simulation speed of a chip is greatly improved by dynamically adjusting the netlist configuration in the simulation process, the accuracy of a simulation result is ensured, and the simulation efficiency is improved. And the flexibility of the simulation process is enhanced.

Description

Technical Field

[0001] This application relates to the field of electronic design automation (EDA), and particularly to a simulation method for dynamically adjusting netlist configuration based on time nodes. Background Art

[0002] With the continuous increase in the scale and complexity of integrated circuit design, a large number of data files need to be processed in the design process. Due to the huge amount of data, reading and processing these files often become the bottleneck of system performance.

[0003] In the fields of mixed-signal chips, large-scale storage chips, high-precision high-speed analog chips, general-purpose analog chips (analog, radio frequency, silicon photonics, optoelectronics, MEMS, computing, third-generation wide bandgap, radio frequency, etc.), multi-core heterogeneous chip systems with two or more cores, etc., as the chip scale expands day by day, the speed problem of chip simulation (such as mixed-signal simulation) becomes increasingly prominent. Especially when the circuit contains high-frequency oscillation modules such as OSC (oscillator) and PLL (phase-locked loop), the simulation process becomes extremely slow. In addition, the design complexity of modern chips is extremely high. The number of MOS transistors in some modules even exceeds 10k, and it may take hundreds or even about 20k simulation cycles to complete a specific function. At the same time, various modes such as mixed-signal interaction control, calibration, and DFT (design for testability) make the chip configuration modes reach up to hundreds, or even 300 - 400 kinds. Such complex mixed-signal configurations are extremely likely to cause errors in chip design.

[0004] In the current mixed-signal simulation method, if the analog part is completely simulated using circuit schematics, the simulation speed will be severely affected; if the model-based verification method is used, an accurate model needs to be established and it is necessary to ensure that the model can accurately reflect the behavior of the circuit schematic. Summary of the Invention

[0005] To solve the defects of the prior art, the purpose of this application is to provide a simulation method for dynamically adjusting netlist configuration based on time nodes. Aiming at the problems of slow mixed-signal simulation speed, difficult to guarantee model accuracy, and lack of flexibility in the simulation process in the prior art, by dynamically adjusting the netlist configuration in the simulation process, it is possible to improve the simulation speed, ensure the accuracy of simulation results, and enhance the flexibility of the simulation process without establishing an accurate model.

[0006] To achieve the above purpose, the simulation method for dynamically adjusting netlist configuration based on time nodes provided by this application includes the following steps:

[0007] Preset multiple time nodes in the simulation process according to the chip type;

[0008] Based on preset time nodes, determine the netlist configuration of the functional modules at each time node;

[0009] When the simulation process reaches a certain time node, dynamically adjust the netlist of the functional module according to the preset netlist configuration.

[0010] Further, the chip types include: general analog chips, mixed-signal chips, and multi-core heterogeneous chips.

[0011] Further, the step of determining the configuration of the functional modules at each time node based on the preset time nodes further includes: receiving the user's selection and determining the netlist configuration of the functional modules at each preset time node.

[0012] Furthermore, the netlist configuration includes: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model, C model, simplified circuit diagram, Protocol model, criticalpart model.

[0013] To achieve the above object, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor is configured to execute the computer program stored in the memory to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on time nodes as described above.

[0014] To achieve the above object, the present application also provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on time nodes as described above.

[0015] The simulation method for dynamically adjusting the netlist configuration based on time nodes provided by the present application has the following beneficial effects compared with the prior art:

[0016] 1) Significantly improves the simulation speed: By dynamically adjusting the netlist configuration during the simulation process, unnecessary computational overhead is reduced, thereby greatly shortening the simulation time and improving the design verification efficiency.

[0017] 2) Ensures the accuracy of the simulation results: During the simulation process, different-precision models are dynamically switched according to actual needs to ensure that accurate circuit schematic diagrams (schematic view) and post-simulation netlist simulations are switched to during critical verification stages, while model (such as.v model,.vams model, etc.) simulations are switched to during stages where speed needs to be improved, thereby improving the simulation accuracy while ensuring an accelerated simulation process.

[0018] 3) Enhances the flexibility of the simulation process: Dynamically adjusting the netlist configuration during the simulation process (dynamic netlist simulation technology) allows for flexible adjustment of the netlist configuration according to the actual working stage of the circuit and verification requirements during the simulation. It can switch from schematic simulation to model simulation, or from model simulation to schematic simulation. In short, it can freely switch the dynamic netlist among models such as schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model, C model, simplified circuit diagram, Protocol model, critical part model, etc. This makes the simulation process closer to real application scenarios and improves the effectiveness and pertinence of verification.

[0019] By establishing a dynamic Netlist simulation system, the present invention enables different configuration views (config view) to be used in the same simulation process. In this way, within the verification scope concerned by designers, the most accurate schematic diagram view of the circuit can be adopted for precise verification; while when it is necessary to quickly verify a large number of scenarios or optimize the simulation performance, it can be flexibly switched to other simplified models, such as.v model,.vams model,.sv model, real number model (RNM), etc., thereby greatly improving the simulation efficiency, significantly reducing the R & D cost, effectively shortening the R & D cycle, and improving the R & D quality.

[0020] Other features and advantages of this application will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings are used to provide further understanding of this application, and constitute a part of the specification. Together with the embodiments of this application, they are used to explain this application and do not constitute a limitation to this application. In the drawings:

[0022] Figure 1 It is a flowchart of a simulation method for dynamically adjusting the netlist configuration based on time nodes according to an embodiment of this application;

[0023] Figure 2 It is a schematic diagram of dynamically adjusting the netlist configuration based on time nodes according to an embodiment of this application;

[0024] Figure 3 It is a block diagram of a digital-analog hybrid SOC chip structure according to an embodiment of this application;

[0025] Figure 4It is a simulation flowchart for dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application;

[0026] Figure 5 It is a schematic diagram of application types and scenarios of a simulation method for dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application;

[0027] Figure 6 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0028] The preferred embodiments of the present application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0029] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0030] The term "including" and its variations used herein are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0031] It should be noted that the concepts of "first", "second", etc. that may be mentioned in the present application are only used to distinguish different devices, components or parts, and are not used to limit the order or interdependence relationship of the functions performed by these devices, components or parts.

[0032] It should be noted that the modifiers "one" and "multiple" that may be mentioned in the present application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more". "Multiple" should be understood as two or more.

[0033] It should be noted that the chips mentioned in the present application can be analog chips, general analog chips, analog-digital hybrid chips, multi-core heterogeneous chips, etc.

[0034] Embodiment 1

[0035] In current chip simulation, if the simulation of the analog part completely uses the circuit schematic for simulation, the simulation speed will be severely affected; while if the Model Based verification method is adopted, an accurate model needs to be established and it is ensured that the model can accurately reflect the behavior of the circuit schematic. In the actual simulation process, the following problems exist:

[0036] 1) In large chips, modules such as OSC, PLL, and GPIO are common modules, but they seriously slow down the simulation speed. In addition, the current Verilog models (.v files), VerilogAMS models (.vams files), and SystemVerilog models (.sv files) are usually generated manually, and it is difficult to ensure a complete match with the circuit schematic (Schematic). When the circuit design is updated, the model (Model) often cannot be updated in a timely manner.

[0037] 2) Currently, all simulation processes determine the netlist at the beginning and keep it unchanged throughout the simulation process. However, the modules that the real SOC focuses on are different at different working stages of the chip. Therefore, if the same netlist and view list are used throughout the process, the circuit schematic may slow down the simulation speed, or the model may not be able to truly reflect the nodes of concern.

[0038] It should be noted that currently all simulators globally, whether pure analog simulation, digital simulation, or mixed signal simulation, adopt the same netlist at the beginning of the simulation and do not modify it throughout the simulation process.

[0039] To address the above problems, the simulation method based on dynamically adjusting the netlist configuration according to time nodes in this application uses the simulation time nodes: T1, T2, T3... Tn as the key trigger points for switching the netlist. When the simulation process reaches the preset time node, the system automatically adjusts to the netlist configuration (Config). Different functional modules can switch from circuit schematic (Schematic) simulation to model (Model) simulation, or from model (Model) simulation to circuit schematic (Schematic) simulation, which can improve the simulation speed and accuracy of the chip.

[0040] Figure 1 For the flowchart of the simulation method based on dynamically adjusting the netlist configuration according to the embodiments of this application, the following will refer to Figure 1 and describe in detail the simulation method based on dynamically adjusting the netlist configuration of this application.

[0041] First, in step 101, confirm the chip type and preset multiple time nodes in the simulation process as the key trigger points for adjusting the netlist configuration.

[0042] In the embodiments of the present application, according to the type of the chip, multiple time nodes: T0, T1, T2, T3,..., Tn are set in the chip simulation process as the key trigger points for adjusting the netlist configuration. As Figure 2 shown, when the simulation process reaches the preset time node, the system automatically switches to the corresponding netlist configuration (Config), where different modules will perform operations using netlists of different model levels.

[0043] In the embodiments of the present application, between two adjacent time nodes, different simulation stages are configured. Multiple time nodes can be preset in the simulation process to simulate different functional modules of the chip at different time nodes.

[0044] In the embodiments of the present application, according to the type of the chip, the functional modules can be divided into: power-on related functional modules, power related functional modules, clock related functional modules, signal processing related functional modules, data processing related functional modules, signal conversion related functional modules, storage related functional modules, communication related functional modules, functional safety modules, monitoring and protection functional modules, etc., and also include any other functional modules in SOC, general simulation, analog-digital hybrid, multi-core heterogeneous, where:

[0045] Power-on related functional modules include, but are not limited to: bandgap reference voltage source BG, reference voltage source BG, bias current source lbias, etc.;

[0046] Power related functional modules include, but are not limited to: reference voltage source, reference current source, under-voltage lockout (UVLO), power-on reset (POR), voltage regulator, charge pump Charge Pump, etc.;

[0047] Clock related functional modules include, but are not limited to: oscillator, phase-locked loop (PLL), external crystal oscillator, low-frequency oscillator, high-frequency oscillator, etc.

[0048] Signal processing related functional modules include, but are not limited to: signal generator, amplifier circuit, feedback circuit, filter circuit, coupling circuit, etc.;

[0049] Data processing related functional modules include, but are not limited to: arithmetic circuit, etc.

[0050] Signal conversion related functional modules include, but are not limited to: analog-to-digital converter, digital-to-analog converter, etc.;

[0051] Function modules related to storage, including but not limited to: Memory Array, SRAM, DRAM, Sense amplifier, driving circuit, etc.;

[0052] Function modules related to communication include but not limited to: wireless communication modules (such as Wi-Fi module, ZigBee module, Bluetooth module, etc.), wired communication modules (such as Ethernet module, serial communication module, CAN bus module, etc.), dedicated communication modules (such as LoRa module, NB-IoT module, etc.).

[0053] It also includes any other functional modules in SOC, general simulation, analog-digital hybrid, multi-core heterogeneous.

[0054] In step 102, based on the preset time nodes, determine the netlist configuration of the functional modules at each time node.

[0055] In the embodiments of the present application, first, according to the type of the chip, confirm the types and quantities of the functional modules in the chip. For example, an analog-digital hybrid SOC chip has an analog schematic part and also digital design parts such as RTL / Gate. Among them, in the analog circuit, there are modules related to power-on, such as a bandgap reference voltage source BG, a reference voltage source BG, a bias current source lbias, a power-on monitoring module POR, etc.; and an oscillator with a relatively low operating frequency (such as 32kHz) that helps with deglitching; and a high-frequency oscillating OSC (such as 16MHz) that provides a high-speed clock, and a high-frequency PLL (such as 160MHz). The analog-digital hybrid SOC chip also includes various communication interfaces, such as general-purpose input / output ports (GPIO), I2C, SPI, and HDMI interface modules. This analog-digital hybrid SOC chip also covers various functional modules, such as impedance detection, analog-to-digital converter ADC, digital-to-analog converter DAC, programmable gain amplifier PGA (Programmable Gain Amplifier), trans-impedance amplifier TIA (Trans-Impedance Amplifier), power amplifier PA and other key functional modules; and modules related to Function Safety.

[0056] In the embodiments of the present application, multiple time nodes are set. The power-on related circuits (such as the reference voltage source BG, bias current source, power-on monitoring module, low-frequency oscillator, etc.) can be used as the functional modules to start simulation after the first time node; the high-frequency OSC (such as 16 MHz) and PLL loop can be used as the functional modules to start simulation after the second time node; the ADC module can be used as the functional modules to start simulation after the third time node; enabling important analog functional modules (such as impedance detection circuits) can be used as the functional modules to start simulation after the fourth time node, or different combinations of various configurations can also be implemented according to the user's selection as the functional modules to start simulation after the fourth time node; the other unexamined analog functional modules can be used as the functional modules to start simulation after the fifth time node.

[0057] In step 103, start the simulation and when the simulation process reaches a certain time node, dynamically adjust the netlist of the functional module according to the preset netlist configuration.

[0058] In the embodiments of the present application, the netlist configuration includes but is not limited to: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, Real Number Model (RNM), C model, simplified circuit diagram, Protocolmodel, critical part model.

[0059] In the embodiments of the present application, taking the simulation of a mixed-signal chip as an example, the reference voltage source BG, bias current source lbias, and power-on monitoring module POR use the.vams (Verilog-AMS) model, and at the same time, the 32 kHz low-frequency OSC uses the.v (Verilog) model; the modules related to high-frequency oscillation are changed to the digital domain, and the high-frequency OSC and ultra-high-frequency PLL use the.v model to ensure that all the circuits they are connected to are digital signals, no longer analog signals; for general GPIO / I2C / SPI / HDMI and other modules, according to the actual chip design requirements, they can use the.v model or.vams, or the RNM (Real number model) level model; the impedance detection module is replaced with the.vams model, the ADC module is changed from the transistor-level circuit to the.vams model, and the analog-related modules on the signal chain such as PGA and TIA are also replaced with the.vams model; finally, all the analog modules in the circuit are replaced with the.v (verilog) model.

[0060] Embodiment 2

[0061] In the embodiments of the present application, taking the mixed-signal SOC chip as an example, the simulation method for dynamically adjusting the netlist configuration based on time nodes of the present application is described in detail.

[0062] Figure 3 is a block diagram of a digital - analog hybrid SOC chip according to an embodiment of the present application. As Figure 3 shown, the digital - analog hybrid SOC chip of the present application includes an analog circuit part and also has digital circuit parts such as RTL / Gate. In the analog circuit, there are modules related to power - on, such as a band - gap reference voltage source BG, a reference voltage source BG, a bias current source Ibias, a power - on monitoring module POR, etc.; and an oscillator with a lower operating frequency (such as 32 kHz) that helps with de - glitch (pulse); and a high - frequency oscillator OSC (such as 160 MHz) that provides a high - speed clock, and a high - frequency phase - locked loop PLL (such as 160 MHz). The digital - analog hybrid SOC chip also includes various communication interfaces, such as general - purpose input / output ports (GPIO), I2C, SPI, and HDMI interface modules. The chip also covers various functional modules, such as a key functional module like an impedance detection module (impedance detection), an analog - to - digital converter ADC, a digital - to - analog converter DAC, a programmable gain amplifier PGA, a trans - impedance amplifier TIA, a power amplifier PA, etc.; and modules related to automotive reliability such as Function Safety.

[0063] In response to the need to improve simulation speed and to cope with a wide range of application scenarios and diverse simulation verification requirements, we propose a new block - based hierarchical structure system and a simulation method that realizes dynamic switching of netlist configurations at time nodes. This system gives users great flexibility. Users can, according to actual needs, flexibly select the most appropriate view (whichever view the different small blocks want to select) for each independent module (block) at the current node, and then realize the free combination of multiple configurations (config) to meet different simulation scenarios. By dynamically adjusting the netlist form of the selected module (dynamically changing the netlist form of the selected block), using the simulation method of dynamic switching of netlist configurations at time nodes, the adaptability and efficiency of the simulation can be significantly improved, ensuring that the simulation process is both efficient and accurate.

[0064] Figure 4 is a simulation flowchart of dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application. Next, we will refer to Figure 4 and describe in detail the simulation process of dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application.

[0065] 1. At time node T0, at the 0th moment: In the initial simulation stage of the circuit, the entire analog IC schematic circuit diagram is adopted; thus ensuring that all simulations are in the most realistic situation. Especially during the power-on stage, through the simulation of the real circuit, check for abnormal leakage, whether it can resist interference on the power supply line, whether the reference voltage source BG and the bias current source lbias can start normally, whether the power-on monitoring module POR and other modules can normally monitor the power supply voltage information, etc. Whether the low-frequency oscillator OSC can start normally and whether it can output a clock signal with the correct power level, etc.

[0066] 2. At time node T1, for example, at the 1000us moment: At this time, the circuit has completed the power-on monitoring and is shown to be able to power on normally. The reference voltage source BG and the bias current source lbias can respectively stably output the expected reference voltage and reference current values; at the same time, the low-frequency oscillator OSC can stably output a periodic square wave.

[0067] In the embodiment of the present application, at time node T1, the entire simulation system starts to change the netlist configuration related to power-on. The.vams (Verilog-AMS) model is used for the reference voltage source BG, the bias current source lbias, and the power-on monitoring module POR, and the.v (Verilog) model is used for the 32kHz low-frequency OSC. Thus, the simulation of the modules related to power-on is accelerated, the number of simulated transistors is reduced, and the simulation speed is increased.

[0068] In the simulation after changing the netlist configuration related to power-on in the embodiment of the present application, the key points are to check whether the high-frequency OSC (for example, 160MHz) starts to oscillate and whether the output is normal; and whether it can drive the high-frequency PLL (for example, 160MHz) to work normally, whether the PLL loop is stable, whether it can stably output a high-frequency signal, and whether the PLL can be locked, etc.

[0069] 3. At time node T2, for example, at the 1300us moment: At this time, the high-frequency OSC can already stably output the correct 160MHz signal, and the Lock signal of the PLL module has also been sent for several cycles, and the PLL outputs the expected 160MHz high-frequency clock. At the same time, the interface communication modules, such as GPIO, I2C, SPI, HDMI, etc., can all communicate normally, and in the simulation, it is found that their delays are the same as the simulation trend of the individual Block, and they can communicate normally with the digital logic control module through the control passing through the Buffer (buffer).

[0070] In the embodiments of the present application, at time node T2, the system continues to dynamically change the netlist, converts the modules related to high-frequency oscillation into the digital domain, uses the.v model for high-frequency OSC and ultra-high-frequency PLL, and ensures that all the circuits they are connected to are digital signals rather than analog signals; while for general GPIO / I2C / SPI / HDMI and other modules, according to the actual chip design requirements, the.v model or.vams, or models at the RNM (Real number model) level can be used. Since then, in all chips, the high-frequency signals that greatly affect the calculation of the analog simulator and thus slow down the entire mixed-signal simulation speed have had their netlist configurations changed, no longer using the transistor-level schematic view, but instead using different-level models such as.v and.vams, which speeds up the simulation.

[0071] After changing the netlist configuration, the circuit continues to operate. After waiting for several PLL cycles and the circuit stabilizes, some important analog function modules can be enabled, such as enabling the impedance detection circuit.

[0072] In the embodiments of the present application, a hierarchical structure based on different blocks can be constructed according to the simulation verification requirements. Different small blocks can select views according to the requirements, thereby realizing different combinations of various configurations (config).

[0073] 4. Time node T3, for example, at 1600 us: At this time, through the transistor-level circuit of the linear regulator LDO based on the circuit schematic diagram, and the transistor-level circuit of the impedance detection module that is turned on, combined with a suitable excitation source, the measurement of different configurations (such as accuracy and calibration, etc.) of the impedance detection circuit and different detection ranges has been completed. For example, noise has also been turned on / off in the middle, and the circuit performance of the impedance detection module under the influence of noise has been obtained; even in some chip designs, the module can be turned off functionally, so when it is disabled, the output may be in a stable or high-impedance state, which will not cause a large drag on the simulation speed; at this time, the functional performance simulation of the impedance detection circuit module has been completed.

[0074] In the embodiments of the present application, at time node T3, the impedance detection module is replaced with a.vams model and no longer uses the transistor level; further reducing the complexity of analog / mixed-signal simulation.

[0075] In the embodiments of the present application, after changing the netlist configuration of the impedance detection module, the circuit continues to operate. After waiting for several PLL cycles and the circuit stabilizes, the function of the ADC module can be started and checked.

[0076] 5. At time node T4, for example, at 1900 us: At this time, through the LDO transistor-level circuit based on the circuit schematic diagram, the turned-on ADC transistor-level circuit, and the cooperation of a suitable excitation source, different configurations and different calibration schemes of the ADC have been completed. At the same time, for different analog input signals, such as signals transmitted from modules such as a programmable gain amplifier (PGA) or a transimpedance amplifier (TIA), after passing through the ADC circuit module, the converted digital signal can be checked through simulation to see if it is correct and whether its functional performance meets the expectations. At this time, the relevant simulation of the ADC has been completed.

[0077] In the embodiment of the present application, at time node T4, the system continues to change the netlist, replaces the ADC module from the transistor-level circuit with a.vams model, and even replaces the analog-related modules on the signal chain such as the PGA and TIA with.vams models, no longer using the transistor level, further reducing the complexity of the analog / digital mixed simulation.

[0078] In the embodiment of the present application, after changing the netlist, the circuit continues to operate. After waiting for several PLL cycles and the circuit to stabilize, the functions of the remaining analog modules are started and checked.

[0079] 6. Time node T5, for example, at 2300 us: At this time, all the analog functional modules and the functional performances that need to be verified in the analog / digital mixed simulation have been verified. However, there are still a large number of complex functions in the pure digital part, such as automotive function verification (Function Safety), etc.

[0080] In the embodiment of the present application, at time node T5, for example, at 2300 us, all the analog functional modules in the circuit are replaced with.v (Verilog) models, thus completely changing the analog / digital mixed simulation into a pure digital simulation.

[0081] In the embodiment of the present application, after changing the netlist, the circuit continues to operate. After waiting for several PLL cycles and the circuit to stabilize, a pure digital simulation can be carried out in the case of pure digital and Boolean operations. Since there are no analog modules in the circuit, the speed will be very fast. The system verifies digital functions, such as key functions like automotive function safety, to ensure that the system meets the design requirements in terms of both function and safety. Since the digital netlist configuration at this time is obtained through the previous layer-by-layer simulation at the analog circuit level, it is very accurate, thus greatly reducing the risk of errors in manual configuration and enjoying the high-speed simulation under a pure digital simulator.

[0082] The simulation method for dynamically adjusting netlist configuration based on time nodes in this application controls the dynamic switching of the netlist through preset time nodes to meet the requirements of different simulation stages, thereby improving simulation efficiency and accuracy, and effectively avoiding the precision problems and version updates that may be brought about by directly using the Model.

[0083] The simulation method for dynamically adjusting netlist configuration based on time nodes in this application is also applicable to the dynamic simulation of general analog circuits, especially those circuit designs with large scale and complex structures (in this context, subsequent steps such as time node T5 can be omitted). In addition, for application scenarios such as large-capacity storage circuits, dynamically modifying the netlist configuration can also play an excellent role. Through this method, we can adjust the netlist in real time during the simulation process, thus greatly accelerating the simulation verification process, shortening the product R & D cycle, and effectively reducing the R & D cost.

[0084] The simulation method for dynamically adjusting netlist configuration based on time nodes in this application is also applicable to the dynamic simulation of multi-core heterogeneous chips. Multi-core heterogeneous chips integrate multiple different types of processor cores, which come from different processes, adopt different instruction set architectures (ISAs), and have different performance characteristics and power consumption requirements. Common heterogeneous multi-core chips include high-performance general-purpose processor cores and dedicated cores designed for specific tasks, such as graphics processing units (GPUs), digital signal processors (DSPs), or neural network processors (NPUs), etc.

[0085] For the simulation of processor cores of multiple cross-process platforms in a multi-core heterogeneous chip, such as a multi-core heterogeneous chip having N1, N2, N3... Nn processor cores, and each processor core coming from a different process, etc., during simulation, different configs can be used at different time nodes to change the netlist of the processor cores, so as to achieve dynamic replacement of the netlist during the simulation process, thereby accelerating or verifying different work contents for different stages.

[0086] Figure 5 Schematic diagram of the application types and scenarios of the simulation method for dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application, such as Figure 5 As shown, the simulation method for dynamically adjusting netlist configuration based on time nodes according to an embodiment of the present application is applicable to chip types and scenarios including general analog chips, mixed-signal chips, and multi-core heterogeneous / cross-process platform multi-chips (newly added), etc. For different simulation verification purposes, at the selected time nodes, config / model can be automatically switched. For example, VerilogAMS, RNM, etc. can be selected most of the time to simplify the simulation, or some important functional modules can be changed to post-simulation netlists and accurately simulated after power-on according to actual needs.

[0087] Example 3

[0088] In the embodiments of the present application, a dynamic simulation method for multi-core heterogeneous is also provided. For example, in the simulation across process platforms, there are N1, N2, N3... Nn chips, and each chip comes from a different process, etc. During the simulation, at the selected time nodes, different configs can be used to achieve dynamic replacement of the netlist during the simulation process, so as to accelerate or verify different work contents for different stages.

[0089] Example 4

[0090] In the embodiments of the present application, an electronic device is also provided. Figure 6 As shown in the schematic diagram of the electronic device structure according to the embodiments of the present application, Figure 6 the electronic device of the present application includes a processor 601 and a memory 602. Among them,

[0091] the memory 602 stores a computer program, and when the computer program is read and executed by the processor 601, it executes the steps in the above-mentioned embodiment of the simulation method for dynamically adjusting the netlist configuration based on time nodes.

[0092] Example 5

[0093] In the embodiments of the present application, a computer-readable storage medium is also provided. The computer program stored in the computer-readable storage medium is configured to execute the steps in the above-mentioned embodiment of the simulation method for dynamically adjusting the netlist configuration based on time nodes when running.

[0094] In this embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disc, etc., various media that can store computer programs.

[0095] Those of ordinary skill in the art can understand that the above are only the preferred embodiments of the present application and are not used to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A simulation method for dynamically adjusting netlist configuration based on time nodes, comprising the following steps: According to the chip type, multiple time nodes are preset in the simulation process; Based on the preset time nodes, determine the netlist configuration of the functional modules at each time node; When the simulation process reaches a certain time node, the netlist of the functional module is dynamically adjusted according to the preset netlist configuration.

2. The simulation method for dynamically adjusting netlist configuration based on time nodes according to claim 1, characterized in that: The chip types include: pan-analog chips, digital-analog hybrid chips, and multi-core heterogeneous chips.

3. The simulation method for dynamically adjusting netlist configuration based on time nodes according to claim 1, characterized in that: The step of determining the configuration of each time node functional module based on the preset time node also includes: receiving a user's selection and determining the netlist configuration of each preset time node functional module.

4. The simulation method for dynamically adjusting netlist configuration based on time nodes according to claim 1, characterized in that: The netlist configuration includes: schematic diagram, post-simulation netlist, VerilogA, VerilogAMS, SystemVerilog, RealNumber Model, C model, simplified circuit diagram, Protocolmodel, and critical part model.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor is used to execute the computer program stored in the memory to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on time nodes as described in any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which is loaded and executed by a processor to implement the steps of the simulation method for dynamically adjusting the netlist configuration based on time nodes as described in any one of claims 1 to 4.

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