A PCB circuit board pressing and forming simulation system and method

Abstract

The present invention relates to the technical field of circuit board pressing simulation, and specifically to a PCB circuit board pressing forming simulation system and method, comprising: a simulation design module, a member simulation module, a simulation maintenance module, a status monitoring module, and a simulation diagnosis module; in response to a circuit board pressing simulation request, obtaining position parameters of each pressing operation to form a morphological network of each layer; receiving the position size of each layer in the layer morphological network, and controlling the morphological change modulus and warpage height of each layer on a single running step when the circuit board is pressed; determining a preset change direction and displacement difference of each morphological change modulus based on the morphological change modulus and warpage height of each layer; performing a simulation check on the displacement difference in the preset change direction to generate a finite element simulation model of the displacement difference and each cavity; and comparing the displacement difference with the finite element simulation model of each cavity to determine the difference angle and type of each model when the difference occurs, thereby improving the precision and efficiency of circuit board production.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board pressing simulation, and in particular to a PCB circuit board pressing forming simulation system and method. Background Art

[0002] With the iterative upgrade of electronic products, consumer demand for devices is evolving towards lighter, thinner, shorter, and more powerful devices. Cavity cavities are customized grooves formed on PCB boards through laser etching or chemical processing. Their depth can be precisely controlled and does not penetrate all board layers. They can significantly reduce the physical space limitations of traditional surface mount technology and improve the utilization efficiency of electronic products. In the production of corresponding PCB circuit boards, multi-layer board lamination is generally used. This method is prone to the following problems when reserving corresponding cavities: When multi-layer boards are pressed together, due to the difference in thermal expansion coefficients between the resin material and the copper foil and the uneven distribution of materials between the layers, the board surface will warp and deform after pressing. At the same time, loose bonding between the layers will lead to insufficient mechanical strength or reduced signal transmission performance. Due to the uneven distribution of local materials in the cavities on the circuit board, stress concentration or displacement offsets are easily generated during pressing, resulting in cracking or delamination around the cavity.

[0003] For example, Chinese patent publication number CN117787208A discloses a method, apparatus, electronic device, and storage medium for simulating deformation of a printed circuit board. The method includes obtaining a first property parameter of a woven composite material; assigning the first property parameter and a second property parameter of a conductive material to the woven composite material and the conductive material in a first representative volume unit model of a stacked structure; obtaining a first finite element model of the stacked structure using the first representative volume unit model; obtaining a third property parameter of the stacked structure using the first representative volume unit model and the first finite element model; assigning the third property parameter to a second finite element model of the printed circuit board; and performing simulation using the second finite element model under a preset temperature field and preset boundary constraints to obtain deformation information of the printed circuit board.

[0004] For example, Chinese patent publication number CN117391036A discloses a printed circuit board simulation method, apparatus, device, and storage medium, which relates to the field of printed circuit board simulation technology. The method includes: in response to receiving a printed circuit board simulation request from a user, obtaining the current user's input parameters and the copper network to be inspected selected by the current user; drawing multiple virtual cutting lines according to the input parameters to cut each layer of the copper network to be inspected, and calculating the copper flow length of each virtual cutting line corresponding to each layer of the copper network to be inspected; calculating the total flow area of ​​each layer corresponding to each virtual cutting line according to the copper network to be inspected and the copper flow length of each layer corresponding to each virtual cutting line, and outputting the total flow area.

[0005] The existing technology respectively explains how to simulate the current circuit board production process by using the intersection of the displacement field and the cutting line stacked from the circuit board layer. It mainly explains that when the circuit board is warped and deformed, the relative displacement of its displacement field can be used to describe the situation of the entire board. However, it ignores the relative displacement difference between the layers of a single circuit board, and is prone to ignoring the alignment deviation of each layer of the circuit board due to the displacement difference, resulting in the problem of offset of the circuit board layer; at the same time, the cutting line identifies the direction of its copper foil and only explains the current direction corresponding to the circuit board. These processing methods all ignore the relative alignment of multiple layers of the circuit board, and whether the offset of the size of each layer will affect the cavity formed by it, thereby affecting the embedded installation of electronic components. Summary of the Invention

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a PCB circuit board pressing and forming simulation system, including: a simulation design module, which is used to respond to the circuit board pressing simulation request, obtain the position parameters of each pressing, and form a morphological network at each level.

[0007] The member simulation module is used to receive the position size of each layer in the layer morphology network and control the morphology change modulus and warpage height of each layer on a single running step when the circuit board is pressed.

[0008] The simulation maintenance module is used to verify the displacement direction of the circuit board at the boundary position based on the morphological change modulus and warpage height of each layer, and to determine the preset change direction and displacement difference of each morphological change modulus.

[0009] The status monitoring module is used to simulate and check the displacement difference in a preset change direction, record the simulation transfer data of the circuit board displacement, perform displacement excitation calculation based on the simulation transfer data, and generate a finite element simulation model of the displacement difference; and extract the morphological change modulus of each cavity on the circuit board to generate a finite element simulation model of each cavity.

[0010] The simulation diagnosis module is used to compare the displacement difference with the finite element simulation model of each cavity, determine the difference angle and type of each model when it is different, and obtain the press-fit diagnosis result of the circuit board.

[0011] A PCB circuit board pressing and forming simulation method includes: S1, responding to a circuit board pressing simulation request, obtaining various position parameters during each pressing, and forming a morphological network at each level.

[0012] S2 receives the position and size of each layer in the layer morphology network, and controls the morphology change modulus and warpage height of each layer in a single running step when the circuit board is pressed.

[0013] S3, based on the morphological change modulus and warpage height of each layer, verifies the displacement direction of the circuit board at the boundary position, and determines the preset change direction and displacement difference of each morphological change modulus.

[0014] S4, performing simulation inspection on the displacement difference in the preset change direction, and generating finite element simulation models of the displacement difference and each cavity based on the simulation transfer data.

[0015] S5, using the displacement difference and the finite element simulation model of each cavity to compare, determine the difference angle and type of each model when the difference occurs, and obtain the press-fit diagnosis result of the circuit board.

[0016] The beneficial effects of the present invention are: 1. The present invention obtains the position parameters of the circuit board when it is pressed, combines the current circuit board shape, and dynamically obtains multiple sets of space-related position parameters. At the same time, the obtained parameters are iteratively updated using the first design space and the second design space, so that the obtained position parameters are closer to the displacement and relative deformation generated when the current circuit board is pressed multiple times, which is convenient for quantifying the displacement difference between the layers when the circuit board is pressed, thereby improving the accuracy of circuit board design and production.

[0017] 2. The present invention uses the running step size as the interval to associate the position size and morphological relationship in the layer morphological network, quantify the morphological changes between the layers of the circuit board, and capture the scale of relatively small gradient changes at each layer when the circuit board is acquired. This part of the content is marked using the morphological change modulus and warping height; then the boundary position is identified, and the information such as the copper strips and copper foil etched on the circuit board is fitted to verify the direction of the displacement generated by each layer of the circuit board, and identify the main displacement changes of the circuit board to realize the prediction processing of the displacement at multiple levels and multiple boundaries.

[0018] 3. The present invention forms a mapping relationship between the position of each point on the circuit board and the layer morphology network by using the displacement difference and the finite element simulation model of each cavity; then the conditions of these nodes are judged and combined, which can identify the dimensions near the cavity when generating the corresponding cavity of the circuit board, and prevent the error in the cavity size due to displacement of each layer, which makes it impossible to install electronic components, so as to improve the accuracy of circuit board production and reduce circuit board production defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the accompanying drawings and examples.

[0020] Figure 1 It is a framework diagram of a PCB circuit board pressing and forming simulation system.

[0021] Figure 2 The present invention is a circuit board pressing diagram of a PCB circuit board pressing molding simulation system.

[0022] Figure 3 The present invention is a flow chart of a status monitoring module of a PCB circuit board pressing and forming simulation system.

[0023] Figure 4 The present invention is a flow chart of a simulation diagnosis module of a PCB circuit board pressing and forming simulation system.

[0024] Figure 5 The present invention is a flowchart of a PCB circuit board pressing and forming simulation method. DETAILED DESCRIPTION

[0025] The following embodiments of the present invention are described in detail. The embodiments described below are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. Where specific techniques or conditions are not specified in the embodiments, the techniques or conditions described in the literature in the art or in the product specifications shall be followed.

[0026] See Figure 1 A PCB circuit board pressing and forming simulation system includes: a simulation design module, a member simulation module, a simulation maintenance module, a status monitoring module and a simulation diagnosis module; wherein the output end of the simulation design module is connected to the member simulation module, the output end of the member simulation module is connected to the simulation maintenance module, the output end of the simulation maintenance module is connected to the status monitoring module, and the output end of the status monitoring module is connected to the simulation diagnosis module.

[0027] The simulation design module is used to respond to the circuit board pressing simulation request, obtain the position parameters of each pressing, and form the morphological network of each layer.

[0028] The member simulation module is used to receive the position size of each layer in the layer morphology network and control the morphology change modulus and warpage height of each layer on a single running step when the circuit board is pressed.

[0029] The simulation maintenance module is used to verify the displacement direction of the circuit board at the boundary position based on the morphological change modulus and warpage height of each layer, and to determine the preset change direction and displacement difference of each morphological change modulus.

[0030] The status monitoring module is used to simulate and check the displacement difference in a preset change direction, record the simulation transfer data of the circuit board displacement, perform displacement excitation calculation based on the simulation transfer data, and generate a finite element simulation model of the displacement difference; and extract the morphological change modulus of each cavity on the circuit board to generate a finite element simulation model of each cavity.

[0031] The simulation diagnosis module is used to compare the displacement difference with the finite element simulation model of each cavity, determine the difference angle and type of each model when it is different, and obtain the press-fit diagnosis result of the circuit board.

[0032] The circuit board pressing simulation request will describe the shape of the current circuit board that needs to be pressed, the corresponding dimensions of each shape, and the required dimensions and shapes at positions such as cavities. These dimensions and shapes are then converted into position parameters to illustrate how to handle the requirements of each position when the circuit board is pressed. When obtaining the parameters of each position, the dimensions on the circuit board after each pressing are mainly compared, and inspection is performed upon final completion to determine whether there are problems at some positions. These data can be obtained by using a camera to obtain images of the circuit board after pressing, and the images can be three-dimensionally mapped to form a layered morphology network.

[0033] In order to adapt to the shape of different chips, when pressing the circuit board, it is necessary to determine the curved surface or irregular shape of the circuit board, and to determine the scale and relative direction of each layer to prevent the thermal expansion modulus and warping of individual layers caused by pressing from affecting the subsequent embedded installation of electronic components when installing electronic components.

[0034] Preferably, Figure 2 As shown in the figure, when the PCB circuit board is pressed, the first pressing is performed by pressing the L2 to L5 layers, and then L1 is added for the second pressing. The pressed part is formed by UV laser to generate a cavity, and finally the L6 layer is pressed for the third time to form a cavity in which electronic components can be embedded.

[0035] Prioritize the requirement that the R angle of the circuit board after lamination is 0.2mm and the residual thickness is less than 0.1mm, which is convenient for the installation and assembly of embedded electronic components; at the same time, the Cavity cavity will be described later.

[0036] The simulation design module is implemented by initializing a list of position parameters, obtaining at least one set of position parameters based on the current circuit board shape, and each set of position parameters contains multiple design spaces. A design space is a set of parameters used to describe the lamination process.

[0037] Whenever the position parameters of the first design space are obtained; the first design space contains the dimensions of each layer after alignment and pressing to determine whether the position of the circuit board after pressing is accurate; the preset shape modulus of the circuit board at each corner is determined by the position parameters of the first design space; the layer morphology network of the current layer is set according to the distribution of the preset morphology modulus at each layer.

[0038] Whenever the position parameters of the second design space are obtained, the position parameters of the current pressing process are compared with the position parameters of the last pressing process, and the position parameters of the second design space are added to the end of the position parameters of the last pressing process.

[0039] When the position parameters corresponding to the morphological network at the current level do not exist in the design space, the position parameters will be retrieved and adjusted accordingly to the available design space.

[0040] The first design space represents the initial design space and is the baseline parameter set for the first lamination or lamination of new layers. It is used to establish the initial hierarchical morphological network and verify the positional accuracy after lamination. It mainly covers the layer alignment parameters, post-lamination dimensions, corner preset shape modulus, and layer morphological network.

[0041] The layer alignment parameters mainly indicate the deviation of the positioning hole coordinates and target position of each layer in the X and Y directions, indicating whether the layers can form an aligned relationship during lamination.

[0042] The dimensions after pressing describe the mapping relationship between the theoretical dimensions after pressing, length, width, thickness, etc. and the actual measured values.

[0043] The preset shape modulus of the corners defines the displacement direction limit of the board edge during the lamination process, such as the maximum warpage height on the Z axis. This represents the maximum shape that may occur. At this time, sampling inspection will be used to scan the laminated circuit board using laser ranging to see if there is warping or other shape changes.

[0044] The layer morphology network combines the coordinates of nodes in each layer to form a network of positions, such as cavity areas, and other positional coordinates that include alignment of each layer. During the lamination process, the circuit board is constructed by stacking multiple layers of materials, such as copper, substrate, and prepreg. The morphology and positional relationships of each layer form a network structure, namely the layer morphology network.

[0045] The second design space describes the set of parameters dynamically updated during multiple press iterations. It is used to record historical press data and optimize subsequent processes. It primarily records real-time process data such as the current press temperature, pressure curve, and press time, and examines whether these parameters change in size and shape at each location after production.

[0046] When comparing parameters in the second design space, the displacement difference and rotation angle deviation between the current layer and the previous laminated layer are mainly compared. If the rotation angle deviation is greater than 0.5 degrees or the displacement difference is greater than 0.5 mm, recalibration is performed. Otherwise, the valid second design space parameters are added to the end of the previous data to form a rolling update database to update the parameters of each layer in the laminated situation.

[0047] In one embodiment of the present invention, the member simulation module mainly receives the running step in the pressing simulation request to determine the morphological changes of each layer, and distinguishes the morphological change modulus generated by each layer according to the process of each pressing to determine whether the circuit board will produce excessive deformation and warping after multiple pressings.

[0048] That is, the implementation method of the member simulation module includes: correlating the position size and morphological relationship contained in the layer morphological network with the running step size as the interval, and determining the displacement of each layer during the pressing process.

[0049] Compare the displacement of each layer at each multiple running step, and set the displacement change rate of each layer as the morphological change modulus of each layer.

[0050] The warping height corresponding to the morphological change modulus is extracted, and height mapping is performed to determine the morphological change modulus at the corresponding position under the distribution of the warping height at each point.

[0051] When performing member simulation, if the circuit board that is being pressed or has been pressed is identified, a fixed time interval is used as the running step, for example, a time interval of 1 minute or 30 seconds, and then the part that is being pressed or cooled is captured by a laser or other image recognition device to identify whether there are multiple warped parts and displaced parts on each pressed layer to prevent alignment problems caused by the use of resin or expansion of other materials during pressing. The edges corresponding to each layer are identified to determine the displacement of each layer, and then the rate of change of the displacement is marked as the morphological change modulus of the circuit board after pressing. At the same time, the warped part on the circuit board is identified with the average height of the circuit board, and the height value of this part is combined with the displacement generated to obtain the output morphological change modulus.

[0052] In one embodiment of the present invention, when performing simulation maintenance, the main displacement is in the preset change direction, and the direction and relative angle of the displacement generated in this direction are used to judge the layer offset of the alignment of each layer and the different extension directions of each layer, so that after the cavity is dug out, the corresponding material will be displaced at the corresponding position, resulting in the cavity being unable to embed the corresponding electronic component.

[0053] That is, the implementation method of the preset change direction in the simulation maintenance module includes: obtaining at least one layer of the circuit board pressing process, scanning the pressing position of each layer during the pressing process, determining the pressing boundary of each layer, and setting the displacement difference of each pressing boundary based on the relative distance of each layer on the pressing boundary.

[0054] Taking each pressing boundary as the starting point, the direction of the copper foil on each layer of the circuit board is set as the initial direction, and the distribution order of the corresponding positions of the morphological change modulus and warpage height on each layer in the initial direction is compared.

[0055] The direction with the largest distribution order is taken as the displacement direction on the corresponding layer. After fitting the displacement directions of each layer according to its angle, the preset change direction is obtained. The displacement difference of each pressed boundary is projected onto the preset change direction as the displacement difference of each morphological change modulus.

[0056] When setting the initial orientation, the PCB plane is set as a three-dimensional coordinate system. On the horizontal plane, the X and Y axes correspond to the length and width of the PCB, and the Z axis corresponds to its height. The X axis is used as the starting point to select the initial orientation for each layer on the PCB. The resulting morphological change moduli are then compared, focusing on the portion of the PCB that can be directly observed after lamination, which is considered the lamination boundary. The relative distances between each layer are then calculated to determine whether the heights are normal. The morphological change moduli are then obtained according to the corresponding coordinates, and the warpage heights are identified. The morphological change moduli and warpage heights are then sorted from largest to smallest to indicate the order in which the morphological changes and warpage locations are identified. The angles and directions of the portions with the largest values ​​are then selected to combine the directions of possible expansion changes on each layer. Multiple angles can be combined using vector or angle fitting calculations to obtain a preset direction. This direction reflects the main trends in warpage or morphological change during PCB production, helping to identify whether the PCB meets the expected settings during lamination, preventing the failure of some defective products to be identified. The preset change direction represents the main trend of the overall morphological change of the circuit board during the lamination process. It can be used to guide subsequent process optimization, such as adjusting lamination parameters such as pressure and temperature to reduce warping or deformation. This direction can also help engineers design more reasonable copper foil wiring solutions to avoid signal integrity issues caused by deformation.

[0057] When fitting to obtain the preset change direction of each layer, the direction identified after each pressing process can also be fitted to describe the overall displacement trend that occurs when the circuit board is pressed during the finishing production process.

[0058] Each outputted preset change direction can represent the initial orientation fitting process, where the circuit board is divided into multiple regions based on the locations of the lamination boundaries. After fitting the initial orientations of these regions, the outputted multiple preset change directions can be generated. Alternatively, the outputted displacement differences under the angles of multiple preset change directions can be illustrated based on data from multiple sets of circuit board inspections.

[0059] In one embodiment of the present invention, when performing a simulation check, the status monitoring module determines that its simulation transfer data mainly identifies the transfer changes of the displacement, determines whether the displacement generated by the previous pressing will affect the subsequent displacement, and projects and accumulates these total displacements using all existing nodes on the layer morphology network, which can represent the comprehensive changes in the displacement in several directions.

[0060] like Figure 3 As shown, the implementation method of displacement excitation calculation includes: extracting the displacement difference generated in the preset change direction during each pressing to form a displacement difference matrix, setting it as the displacement state during simulation inspection, and establishing a mapping relationship between the displacement state and the layer morphology network.

[0061] The mapping relationship between the displacement state and the layer morphology network is used to verify the corresponding position of the displacement state in the layer morphology network, and the displacement transfer coefficient between each displacement state under clock offset and position offset is determined.

[0062] The validity of each displacement transfer coefficient is verified recursively. If the displacement transfer coefficient is valid, the credibility of the displacement transfer coefficient is used as the result of the displacement excitation calculation.

[0063] The simulation transfer data here refers to the calculation of the displacement transfer coefficient based on the displacement difference at the corresponding position of the layer morphology network. This process is the content of the simulation transfer data. The validity of the displacement transfer coefficient is determined by calculating the displacement between each layer using the displacement transfer coefficient. If the error between the estimated value and the actual value is greater than 0.95, the corresponding displacement transfer coefficient identification data is output as the result of the displacement excitation calculation at that time, and this data is used to combine into a finite element simulation model of the displacement difference.

[0064] The position of the displacement state in the layer morphology network is verified by compensating the error between the displacement states when the time step and the spatial coordinates are inconsistent, and then using the displacement transfer coefficient to compensate for this error.

[0065] For example, after each pressing, the displacement difference projected to the preset direction along the XYZ axis is extracted. , forming the displacement difference matrix , ; There are n elements in the displacement difference matrix.

[0066] Assuming that the displacement is transferred linearly between layers, a transfer matrix is ​​established at the corresponding layer in the layer morphology network according to the corresponding displacement difference, and the corresponding position of the displacement state in the layer morphology network is verified.

[0067] The displacement difference matrix is ​​mapped to the layer morphology network to generate the displacement vectors of all nodes in each layer after compression. , k represents the number of layers currently identified, and can also represent the number of displacement vectors, and its value range is 1 to K.

[0068] ;in, represents the displacement vector of the k+1th layer, represents the displacement transfer coefficient from the kth layer to the k+1th layer, represents the displacement vector of the kth layer, represents the error term of the kth layer.

[0069] ;in, 、 、 They represent the relationship coefficients between the current layer and the next layer affected by thermal expansion in the XYZ directions, 、 、 Respectively represent the relationship coefficients between the current level and the next level in terms of shear deformation in the XYZ directions, 、 、 Represents the relationship coefficients between the current layer and the next layer in the X, Y, and Z directions. The relationship coefficients set at this time will be set according to the displacement at the corresponding position during historical data analysis.

[0070] For example, solve each direction independently ; Where N represents the number of nodes contained in each layer, and the value of i ranges from 1 to N. represents the displacement vector of the i-th node in the k+1-th layer in the X direction, represents the displacement vector of the i-th node in the k-th layer in the X direction, represents the displacement vector of the i-th node in the k-th layer in the Y direction, Represents the displacement vector of the i-th node in the k-th layer in the Z direction; after comprehensive calculation of these contents, the corresponding one with the smallest error is required 、 、 After the output, the remaining unit parameters are calculated in the same way. The least squares method is used to calculate the displacement vector of each level to obtain the matrix value represented by the displacement transfer coefficient at that time.

[0071] Alternatively, you can use the matrix element settlement method to obtain the current displacement transfer coefficient, such as ;in, It means to perform a vector transposition operation on the displacement vector of the k-th layer to solve the current corresponding displacement transfer coefficient.

[0072] Finally, the displacement transfer coefficient is used to predict the value of the displacement vector, and the average value of the difference between the predicted value and the actual displacement vector value is used to set the credibility score; if 1 is added to the inverse of the average value of the difference, it is the credibility score used here to represent the result of the displacement excitation calculation.

[0073] The calculated credibility scores are applied to the layer morphology network to describe the boundary conditions and displacement distribution in the finite element simulation model of the displacement difference combination, so as to obtain the finite element simulation model of the displacement difference.

[0074] That is, the implementation method of generating a finite element simulation model of displacement difference also includes: using the displacement transfer coefficient and credibility score obtained at each level as boundary conditions, interpolating each node in the level morphology network, and combining the distribution of the interpolated displacement transfer coefficient and credibility score with the value of the displacement difference as the output finite element simulation model; this simulation model is mainly used to describe the distribution of its calculated displacement difference and the relationship between the displacement transfer coefficient representing the displacement transmission, so as to express the relative effects of the current circuit board after the compression treatment of its various boundaries during production.

[0075] In the finite element simulation model of displacement difference, the main output is the overall displacement distribution diagram of the circuit board, which shows the displacement of each node. The distribution of these displacement conditions is used to represent the relative problems existing in the current circuit board during production.

[0076] The finite element simulation model of each cavity is intended to demonstrate that the required cavity holes, when generated, have boundaries and dimensions that meet the mounting requirements of electronic components. This finite element model is designed with cavity edge constraints, material response, and concentrated displacement around the cavity as boundary conditions, and 3D geometry and pressing time as simulation conditions. The model describes the implementation process of each boundary position. It also explains the impact factors and troubleshooting results that ultimately represent changes in the 3D geometry.

[0077] Finite element simulation models for each cavity are generated using boundary conditions such as cavity edge constraints, material response, and concentrated displacements around the cavity, with three-dimensional geometry and pressing time as simulation conditions. Cavity edge constraints refer to the fixed or movable restrictions imposed on the area around the cavity during finite element analysis; material response includes material properties such as elastic modulus and Poisson's ratio, which determine the material's behavior under stress. Concentrated displacements around the cavity represent the average displacements around the cavity, indicating whether pressing during processing will cause dimensional deviations in the cavity.

[0078] Based on the state transition probabilities of each boundary condition and simulation condition in the layer morphology network, the distribution of each cavity is described, and the maximum state transition probability is used as the output of the finite element simulation model of each cavity. The state transition probability represents the conditional probability of at least one set of relevant data satisfying the boundary conditions and simulation conditions, and represents the probability of the corresponding data changing. This allows prediction of the displacement and morphological changes that occur during circuit board production under different conditions, preventing displacement deviations in the cavity that may cause problems in the subsequent installation of electronic components.

[0079] The selected state transition probability is based on the probability value of the selected boundary conditions and simulation conditions in the layer morphology network within a specific time period, that is, the selected boundary conditions and simulation conditions appearing in the current sampled data are determined based on the currently sampled data, and the values ​​of these conditions are combined with historical data to statistically calculate the state transition probability of the corresponding conditions.

[0080] Cavity edge constraints are conditions that determine whether coordinate points at the cavity edge are allowed to move. Generally, to prevent stress concentration effects on the cavity edge of a circuit board, it's necessary to verify the displacement of points at the cavity edge to prevent excessive displacement from causing deformation. Cavity edge constraints are expressed as the displacement values ​​allowed at multiple nodes at the cavity edge, which can be zero or extremely small. Verifying this condition involves using laser scanning to determine the displacement, and treating the displacement at the cavity edge as a cavity edge constraint.

[0081] The material response is expressed as Young's modulus, Poisson's ratio, yield strength, thermal expansion coefficient and nonlinear characteristics. These contents will mark the material properties of each layer of circuit boards superimposed around the cavity. These parameters can be obtained based on the materials used to prevent the inability to query the corresponding material when abnormal cavity generation occurs.

[0082] Young's modulus measures a material's ability to resist stretching or compression and determines its stiffness. Poisson's ratio represents the ratio of a material's transverse strain to its longitudinal strain, reflecting the material's degree of lateral contraction or expansion when subjected to stress. Yield strength indicates the stress level at which a material begins to permanently deform. The coefficient of thermal expansion describes the material's dimensional changes with temperature and is particularly important for applications involving temperature changes. Nonlinear characteristics indicate that certain materials exhibit nonlinear behavior under high stress, such as hardening or softening effects. These reactions will indicate the material properties of each layer of the circuit board during lamination, reflecting whether there are corresponding problems with the lamination of the circuit board. This means that the standard property values ​​of the corresponding materials are used as the boundary conditions for the material response at this time.

[0083] The concentrated displacement around the cavity is manifested as the significant displacement generated around the cavity, that is, some data are filtered according to the size of the displacement generated by the surrounding nodes. This part will obviously exceed the average value of the displacement around the cavity. These points are used as the boundary conditions corresponding to the concentrated displacement around the cavity.

[0084] The simulation conditions for three-dimensional geometric shapes and pressing time describe how long the circuit board takes to press together under the size requirements corresponding to the three-dimensional geometric shape, and then the simulation conditions appear. The value taken by the simulation condition and the conditional probability of the current simulation condition appear together are used to quantify the situations corresponding to different circuit boards under various production conditions.

[0085] In one embodiment of the present invention, Figure 4 As shown, the implementation method of the simulation diagnosis module includes: using the displacement difference and the finite element simulation model of each cavity to perform feature characterization, and randomly extracting multiple data as characterization features.

[0086] The characterization features are processed using a finite element simulation model of displacement difference, at least one difference node is queried, and the validity of the characterization features is determined based on the physical position of the difference node; wherein the difference node is used to represent the mapping relationship between the characterization features; the difference node represents the mapping relationship between the characterization features, indicating that the positions of the first characterization feature and the second characterization feature used subsequently are mapped to each other.

[0087] The difference angles are searched based on the validity of the characterization features, the difference angles corresponding to the characterization features are determined, and the types corresponding to the difference angles are marked; the data corresponding to the difference angles and types are output as the pressing diagnosis results.

[0088] Determining the validity of the characterization feature includes: if the current characterization feature is abnormally distributed in the finite element simulation model of the displacement difference, taking the characterization feature of the corresponding difference node as the first characterization feature, and obtaining the characterization feature of the finite element simulation model of each cavity as the second characterization feature, and comparing the priority of the first characterization feature and the second characterization feature; if the priority of the first characterization feature is greater than the priority of the second characterization feature, the first characterization feature is judged to be valid, otherwise the second characterization is deemed to be valid.

[0089] The implementation method of retrieving the difference angle based on the validity of the characterization feature includes: extracting the valid duration and update interval of the characterization feature, and using the update interval as an index to retrieve the difference angle where the difference occurs, and after associating the difference angle with the valid duration, marking the type corresponding to each difference angle.

[0090] Preferably, the data extracted by characterizing the features can be expressed as follows as shown in Table 1.

[0091] Table 1. Characterization feature example data

[0092]

[0093] Among them, the nodes represent the displacement difference and the data randomly obtained in the relevant finite element model of the cavity. They are identified as nodes, and then the values ​​of the displacement difference in the three directions of XYZ ΔX, ΔY and ΔZ are obtained. At the same time, the maximum stress value σ_max at the corresponding acquisition position is recorded. This stress value can be calculated from the stress generated by the temperature expansion of the material. The parameters R angle and residual thickness near the cavity represent the parameter dimensions measured at the cavity after multiple pressings. These contents represent whether the production of the current cavity meets the final standard.

[0094] The first characterization feature extracts data from the displacement difference finite element simulation model, including displacement in the X, Y, and Z directions, and then adds the maximum stress value and distance from the cavity edge to represent the location of the corresponding node. The second characterization feature obtains the maximum stress value, distance from the cavity edge, R angle, and residual thickness of the corresponding node.

[0095] When extracting difference nodes from the first characterization feature, selection is made based on the displacement difference and maximum stress value in the three directions. For example, based on the displacement difference and maximum stress value of the node in the X direction, when any one of the conditions ΔX>0.1mm or σ_max>40MPa is met, the node corresponding to the first characterization feature is regarded as a difference node. Alternatively, the average value of the displacement difference in the three directions of X, Y, and Z, as well as the average value of the maximum stress value in the historical data, are extracted. When the data corresponding to the first characterization feature is greater than the average value, the corresponding node is marked as a difference node. In this case, the nodes selected are the nodes where the corresponding layer of the circuit board has obvious changes after lamination. These nodes will reflect the overall deformation of the circuit board or the relevant data of the relative layer after lamination, preventing layer offset and other problems that lead to deviations in the production size of the circuit board.

[0096] When comparing the priority of the first characterization feature with the second characterization feature, the priority needs to be determined by comparing the residual thickness and the distance from the edge of the cavity. The purpose of judging the priority at this time is mainly to identify the point at the edge of the cavity to prevent problems with the corresponding size of the cavity formed after multiple pressings, resulting in the inability to directly fit the corresponding electronic components to the position when installing.

[0097] That is, the priority of comparing the first characterization feature and the second characterization feature is to extract the distance value from the cavity edge corresponding to the first characterization feature and the residual thickness value in the second characterization feature. If the distance value from the cavity edge and the residual thickness value do not meet any conditions in the preset rules, the first characterization feature is regarded as valid. When any condition in the preset rules is met, the second characterization feature is regarded as valid.

[0098] The preset rules are expressed as the two conditions of residual thickness <0.1mm and distance from the cavity edge <1.0mm. When the conditions corresponding to the residual thickness are not met, it means that the problems of the current circuit board may not be limited to the points at the edge of the cavity. It is necessary to conduct major verification of other positions to determine why its residual thickness does not meet the preset rules and identify the displacement difference generated during its production. That is, the data covered by the first characterization feature is mainly processed. When the condition of distance from the cavity edge is not met, it means that its position is far away from the cavity and there is no need to additionally judge the cavity-related data. That is, it can be judged based on the content displayed by the first characterization feature; when these two conditions are met, it means that the residual thickness production meets the standard, and it is necessary to judge other parameters around the cavity, that is, mainly based on the second characterization feature. After identifying whether its R angle is at 0.2mm, the parameters around the cavity are identified, and the identification and processing of the main problems of the current circuit board are completed in sequence.

[0099] Assume that all nodes described in Table 1 are regarded as difference nodes, and the data corresponding to these three nodes are used to illustrate the validity of the characterization feature; among them, node 1001, the residual thickness is 0.119mm, which is greater than 0.1mm, and the distance value from the edge of the cavity is 2.0mm, which is greater than 1mm. Both rules for priority comparison are not satisfied; this indicates that at this time, the data in the first characterization feature needs to be used as the main factor to identify the data difference generated at the current position.

[0100] At node 1002, the residual thickness is 0.095 mm, which is less than 0.1 mm, and the distance from the cavity edge is 1.2 mm, which is greater than 1 mm. This indicates that when the residual thickness of the cavity meets the conditions, since this node is far from the cavity edge, it is necessary to identify the displacement difference and maximum stress value in the corresponding direction to prevent the value at this position from being too large, which would affect the cavity size. That is, the relevant positions are identified based on the data of the first characterization feature.

[0101] At node 1003, the residual thickness is 0.091 mm, less than 0.1 mm, and the distance from the cavity edge is 0.5 mm, less than 1 mm. This indicates that all priority comparison rules are met. The data covered by the second characterization feature is primarily identified to determine whether the corresponding R angle is normal, thereby judging the current PCB production status.

[0102] Preferably, when identifying the size of its R angle, the R angle is required to be within 0.2 mm and not greater than the value of three times the standard deviation calculated during its production, that is, within the range of 0.2 mm plus three times the standard deviation, the R angle corresponding to the circuit board cavity is considered to be compliant.

[0103] For the difference angle used subsequently, its angle value is mainly based on the angle between the three-dimensional vector represented by the displacement difference generated by the node and the three-dimensional vector represented by the maximum displacement difference allowed at the corresponding position. This angle is used as the difference angle. The difference angle is used to search data in the database to identify the cause represented by the difference angle. As shown in Table 2, the corresponding possible causes and the type corresponding to the difference angle can be retrieved according to the range of the difference angle.

[0104] Table 2. Angle classification rules

[0105]

[0106] At this time, multiple data samples will be taken according to the number of pressing times and the cooling time of the circuit board after pressing. After the difference angle search is performed with the number of pressing times as an additional index, the type existing at this time is identified to determine whether there is a corresponding problem during the production of the current circuit board.

[0107] Then, the effective time length corresponding to the first characterization feature and the second characterization feature is determined. The effective time length represents the length of the time period when the first characterization feature and the second characterization feature are used to retrieve the difference angle respectively, and the types of the retrieved difference angles are sorted according to the difference between the two characterization features and the time interval between the retrieval time periods to output the pressing diagnosis result of the circuit board; the pressing diagnosis result of the circuit board will include the time period of the output difference angle during the retrieval, the retrieved type, and other retrieved data, as well as the extracted first characterization feature and the second characterization feature, and finally describe the relevant problems during the production of the circuit board in the corresponding time period to reduce the error of the corresponding size during the production of the circuit board.

[0108] Finally, the staff will adjust the production method of the circuit board based on the results of the pressing diagnosis. For example, if inter-layer misalignment is detected, it is recommended to check the pressure distribution of the pressing machine; if structural mismatch is detected, it is recommended to recalibrate the mold or adjust the material matching.

[0109] like Figure 5 As shown, the present invention also provides a PCB circuit board pressing and forming simulation method, including: S1, responding to a circuit board pressing simulation request, obtaining each position parameter during each pressing, and forming a morphological network at each level.

[0110] S2 receives the position and size of each layer in the layer morphology network, and controls the morphology change modulus and warpage height of each layer in a single running step when the circuit board is pressed.

[0111] S3, based on the morphological change modulus and warpage height of each layer, verifies the displacement direction of the circuit board at the boundary position, and determines the preset change direction and displacement difference of each morphological change modulus.

[0112] S4, performing simulation inspection on the displacement difference in the preset change direction, and generating finite element simulation models of the displacement difference and each cavity based on the simulation transfer data.

[0113] S5, using the displacement difference and the finite element simulation model of each cavity to compare, determine the difference angle and type of each model when the difference occurs, and obtain the press-fit diagnosis result of the circuit board.

[0114] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention, which are still covered by the scope of protection of the present invention.

Claims

1. A PCB circuit board pressing and forming simulation system, characterized in that: include: The simulation design module responds to the circuit board pressing simulation request, obtains the position parameters of each pressing, and forms the morphological network of each layer; The member simulation module receives the position and size of each layer in the layer morphology network and controls the morphology change modulus and warpage height of each layer in a single running step when the circuit board is pressed; The simulation maintenance module verifies the displacement direction of the circuit board at the boundary position based on the morphological change modulus and warpage height of each layer, and determines the preset change direction and displacement difference of each morphological change modulus; The status monitoring module simulates and checks the displacement difference in a preset change direction, records the simulated transfer data of the circuit board displacement, and performs displacement excitation calculation based on the simulated transfer data to generate a finite element simulation model of the displacement difference. It also extracts the morphological change modulus of each cavity on the circuit board and generates a finite element simulation model of each cavity. The simulation diagnosis module uses the displacement difference to compare with the finite element simulation model of each cavity, determines the difference angle and type of each model when it differs, and obtains the press-fit diagnosis result of the circuit board; The implementation of the simulation diagnosis module includes: Characterization is performed using displacement differences and finite element simulation models of each cavity, and multiple data are randomly extracted as characterization features; Processing the characterization feature using a finite element simulation model of the displacement difference, querying at least one difference node, and determining the validity of the characterization feature based on the physical location of the difference node; The difference angles are searched based on the validity of the characterization features, the difference angles corresponding to the characterization features are determined, and the types corresponding to the difference angles are marked; the data corresponding to the difference angles and types are output as the pressing diagnosis results; Determining the validity of characterization features includes: If the current characterization feature is abnormally distributed in the finite element simulation model with displacement difference, the characterization feature of the corresponding difference node is used as the first characterization feature, and the characterization feature of the finite element simulation model of each cavity is obtained as the second characterization feature, and the priority of the first characterization feature and the second characterization feature are compared; if the priority of the first characterization feature is greater than the priority of the second characterization feature, the first characterization feature is judged to be valid, otherwise the second characterization is considered to be valid; The implementation methods of searching for difference angles based on the effectiveness of characterizing features include: The effective duration and update interval of the characterization feature are extracted, and the update interval is used as an index to retrieve the difference angle where the difference occurs. After associating the difference angle with the effective duration, the type corresponding to each difference angle is marked.

2. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of the simulation design module include: Initialize each position parameter list, based on the shape of the current circuit board, and obtain at least one set of position parameters, each set of position parameters contains multiple design spaces; Whenever the position parameters of the first design space are obtained, the preset shape modulus of the circuit board at each corner is determined based on the position parameters of the first design space; the layer morphology network of the current layer is set based on the distribution of the preset shape modulus at each layer; the first design space represents the initial design space and is the benchmark parameter set for the first lamination or lamination of a new layer. It is used to establish the initial layer morphology network and verify the position accuracy after lamination; Whenever position parameters of the second design space are obtained, the position parameters of the current pressing process are compared with those of the previous pressing process, and the position parameters of the second design space are added to the end of the position parameters of the previous pressing process. The second design space is a set of parameters that are dynamically updated during multiple pressing iterations and is used to record historical pressing data and optimize subsequent processes. When the position parameters corresponding to the morphological network at the current level do not exist in the design space, the position parameters will be retrieved and adjusted accordingly to the available design space.

3. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The member simulation module is implemented by correlating the positional dimensions and morphological relationships contained in the layer morphological network at intervals of the running step length to determine the displacement of each layer during the pressing process; Compare the displacement of each layer at each multiple running step, and set the displacement change rate of each layer as the morphological change modulus of each layer; The warping height corresponding to the morphological change modulus is extracted, and height mapping is performed to determine the morphological change modulus at the corresponding position under the distribution of the warping height at each point.

4. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of preset change direction in the simulation maintenance module include: At least one layer of the circuit board to be pressed is obtained, and the pressed positions of each layer during the pressing process are scanned to determine the pressing boundaries of each layer, and the displacement difference of each pressing boundary is set according to the relative distance of each layer on the pressing boundary; Taking each lamination boundary as the starting point, the direction of the copper foil on each layer of the circuit board is set as the initial direction, and the distribution order of the corresponding positions of the morphological change modulus and warpage height on each layer in the initial direction is compared; The direction with the largest distribution order is taken as the displacement direction on the corresponding layer. After fitting the displacement directions of each layer according to its angle, the preset change direction is obtained. The displacement difference of each pressed boundary is projected onto the preset change direction as the displacement difference of each morphological change modulus.

5. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods for displacement excitation calculation include: The displacement difference generated in the preset change direction during each pressing is extracted to form a displacement difference matrix, which is set as the displacement state during simulation inspection. A mapping relationship is established between the displacement state and the layer morphology network. Using the mapping relationship between the displacement state and the layer morphology network, the corresponding position of the displacement state in the layer morphology network is verified, and the displacement transfer coefficient between each displacement state under clock offset and position offset is determined; The validity of each displacement transfer coefficient is verified recursively. If the displacement transfer coefficient is valid, the credibility of the displacement transfer coefficient is used as the result of the displacement excitation calculation.

6. A PCB circuit board pressing and forming simulation system according to claim 5, characterized in that: Methods for implementing a finite element simulation model for generating displacement differences also include: The displacement transfer coefficients and credibility scores obtained at each level are used as boundary conditions, and each node in the level morphology network is interpolated. The distribution of the interpolated displacement transfer coefficients and credibility scores is combined with the value of the displacement difference as the output of the finite element simulation model.

7. A PCB circuit board pressing and forming simulation system according to claim 5, characterized in that: The implementation methods for generating the finite element simulation model of each cavity include: The cavity edge constraint, material response and concentrated displacement around the cavity are used as boundary conditions, and the three-dimensional geometry and pressing time are used as simulation conditions; Based on the state transition probability of each boundary condition and simulation condition in the layer morphology network, the distribution of each cavity is described, and the maximum value of the state transition probability is used as the output of the finite element simulation model of each cavity.

8. A PCB circuit board pressing and forming simulation method, characterized in that: include: S1, in response to a circuit board pressing simulation request, obtains position parameters at each pressing time and forms a morphological network at each layer; S2, receives the position and size of each layer in the layer morphology network, and controls the morphology change modulus and warpage height of each layer in a single running step when the circuit board is pressed; S3, based on the morphological change modulus and warpage height of each layer, verify the displacement direction of the circuit board at the boundary position, and determine the preset change direction and displacement difference of each morphological change modulus; S4, performing simulation inspection on the displacement difference in the preset change direction, and generating a finite element simulation model of the displacement difference and each cavity based on the simulation transfer data; S5, comparing the displacement difference with the finite element simulation model of each cavity, determining the difference angle and type of each model when the difference occurs, and obtaining the press-fit diagnosis result of the circuit board; Characterization is performed using displacement differences and finite element simulation models of each cavity, and multiple data are randomly extracted as characterization features; Processing the characterization feature using a finite element simulation model of the displacement difference, querying at least one difference node, and determining the validity of the characterization feature based on the physical location of the difference node; Search the difference angles based on the validity of the characterization features, determine the difference angles corresponding to the characterization features, and mark the types corresponding to each difference angle; Output the data corresponding to the difference angle and type as the pressing diagnosis result; Determining the validity of characterization features includes: If the current characterization feature is abnormally distributed in the finite element simulation model with displacement difference, the characterization feature of the corresponding difference node is used as the first characterization feature, and the characterization feature of the finite element simulation model of each cavity is obtained as the second characterization feature, and the priority of the first characterization feature and the second characterization feature are compared; if the priority of the first characterization feature is greater than the priority of the second characterization feature, the first characterization feature is judged to be valid, otherwise the second characterization is considered to be valid; The implementation methods of searching for difference angles based on the effectiveness of characterizing features include: The effective duration and update interval of the characterization feature are extracted, and the update interval is used as an index to retrieve the difference angle where the difference occurs. After associating the difference angle with the effective duration, the type corresponding to each difference angle is marked.

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