Pulse-based data retention method and device, storage medium and computer equipment
By applying decapsulation pulses to its gate electrode after data erasing of the ferroelectric field effect transistor, the problem of poor data retention reliability in memory devices is solved, and higher data retention capabilities are achieved.
Patent Information
- Application Number
- CN202311743658.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-20
AI Technical Summary
In memory devices that use ferroelectric field effect transistors as memory cells, data maintenance reliability is poor, mainly because the charge captured by the interface trap is gradually released during the data maintenance process, resulting in threshold voltage drift.
After the ferroelectric field effect transistor performs a data erase operation, multiple decapture pulses are applied to its gate electrode. The direction of the decapture pulse is opposite to the data erase pulse, and the amplitude is smaller than the data erase pulse to eliminate charges in the interface trap.
By decapture pulses, the charge release phenomenon of ferroelectric field effect transistors during data retention is avoided, and the data retention reliability of memory devices is significantly improved.
Smart Images
Figure CN120183457A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics technology, and in particular, to a data retention method, device, storage medium, and computer device based on pulses. Background Art
[0002] With the development of semiconductor technology and microelectronics technology, especially the discovery of the excellent ferroelectricity of hafnium dioxide (HfO2) thin films at the nanoscale and the complete compatibility with complementary metal oxide semiconductor (CMOS), ferroelectric field-effect transistors (FeFETs) have received high attention in the application fields of memory (NVM) devices, single-transistor dynamic random access memories (1T-DRAMs), and neuromorphic synaptic devices. The reliability issues of FeFETs have been widely studied.
[0003] However, due to the poor retention performance of ferroelectric field-effect transistors, especially when using ferroelectric field-effect transistors as memory cells, during the programming and erasing operations of ferroelectric field-effect transistors, interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field-effect transistor, as well as interface state traps between the ferroelectric layer and the gate insulating layer, will capture charges. During the subsequent data retention process, the charges captured by the interface state traps will gradually be released, resulting in the drift of the threshold voltage of the ferroelectric field-effect transistor, which is not conducive to the reliability of the memory cell. Therefore, the data retention reliability of the memory array in current memory devices using ferroelectric field-effect transistors as memory cells is poor. Summary of the Invention
[0004] In view of this, the present application provides a data retention method, device, storage medium, and computer device based on pulses, mainly aiming to solve the technical problem of poor data retention reliability of the memory array in memory devices using ferroelectric field-effect transistors as memory cells.
[0005] According to a first aspect of the present invention, a data retention method based on pulses is provided, which is applied to a memory device. The memory device uses a ferroelectric field-effect transistor as a memory cell. The method includes:
[0006] Monitoring whether the ferroelectric field-effect transistor has performed a data erasing or writing operation;
[0007] After the ferroelectric field-effect transistor has performed the data erasing or writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor to improve the data retention ability of the memory cell during the data retention process.
[0008] Among them, the pulse direction of the de-trapping pulse is opposite to that of the data erasing and writing pulse. The data erasing and writing pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor to perform the data erasing and writing operation on the ferroelectric field effect transistor. The amplitude of the de-trapping pulse is smaller than that of the data erasing and writing pulse.
[0009] Optionally, the data erasing and writing operation includes a programming operation; the de-trapping pulse includes a first de-trapping pulse; the monitoring of whether the ferroelectric field effect transistor has performed a data erasing and writing operation includes: determining in real time whether the ferroelectric field effect transistor has performed a programming operation; after the ferroelectric field effect transistor has performed the data erasing and writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor to improve the data retention ability of the storage cell during the data retention process, including: after the ferroelectric field effect transistor has performed the programming operation, applying multiple first de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor, where the pulse direction of the first de-trapping pulse is opposite to that of the programming pulse, and the programming pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor after performing the programming operation on the ferroelectric field effect transistor.
[0010] Optionally, among the multiple first de-trapping pulses, according to the time sequence applied to the gate electrode metal, the amplitude of the first de-trapping pulse increases successively.
[0011] Optionally, the time interval between two adjacent first de-trapping pulses applied to the gate electrode metal is less than or equal to a first preset time interval.
[0012] Optionally, the data erasing and writing operation includes an erasing operation; the de-trapping pulse further includes a second de-trapping pulse; the monitoring of whether the ferroelectric field effect transistor has performed a data erasing and writing operation includes:
[0013] determining in real time whether the ferroelectric field effect transistor has performed an erasing operation; after the ferroelectric field effect transistor has performed the data erasing and writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor to improve the data retention ability of the storage cell during the data retention process, including: after the ferroelectric field effect transistor has performed the erasing operation, applying multiple second de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor, where the pulse direction of the second de-trapping pulse is opposite to that of the erasing pulse, and the erasing pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor after performing the erasing operation on the ferroelectric field effect transistor.
[0014] Optionally, among the multiple second de-trapping pulses, according to the time sequence of application on the gate electrode metal, the amplitude of the second de-trapping pulse increases successively.
[0015] Optionally, the time interval between two adjacent second de-trapping pulses applied on the gate electrode metal is less than or equal to a second preset time interval.
[0016] According to a second aspect of the present invention, there is provided a pulse-based data retention device, the device comprising:
[0017] An operation monitoring module, configured to monitor whether the ferroelectric field effect transistor has performed a data erasing and writing operation;
[0018] A pulse execution module, configured to apply multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor after the ferroelectric field effect transistor has performed the data erasing and writing operation, so as to improve the data retention ability of the storage unit during the data retention process,
[0019] Wherein, the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing and writing pulse, the data erasing and writing pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor to perform the data erasing and writing operation on the ferroelectric field effect transistor, and the amplitude of the de-trapping pulse is less than the amplitude of the data erasing and writing pulse.
[0020] According to a third aspect of the present invention, there is provided a storage medium, on which a computer program is stored, and when the program is executed by a processor, the above-mentioned pulse-based data retention method is implemented.
[0021] According to a fourth aspect of the present invention, there is provided a computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the above-mentioned pulse-based data retention method is implemented.
[0022] A data retention method, device, storage medium, and computer device based on pulses provided by the present invention. First, it determines in real time the data erasing and writing operations performed on the ferroelectric field-effect transistor. Then, after the ferroelectric field-effect transistor has completed the data erasing and writing operations, multiple de-trapping pulses are applied to the gate electrode metal of the ferroelectric field-effect transistor, that is, multiple de-trapping pulse waveforms are applied to the gate electrode metal of the ferroelectric field-effect transistor. Among them, the de-trapping pulses can be applied to the gate electrode metal by sending de-trapping pulses to the gate electrode. Here, the pulse direction of the de-trapping pulse is opposite to the direction of the pulse applied to the gate electrode of the ferroelectric field-effect transistor when the storage device performs data erasing and writing operations on the ferroelectric field-effect transistor, so as to eliminate the charge trapped in the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field-effect transistor and the interface state traps between the ferroelectric layer and the gate insulating layer during the operation. The technical solution of the present application quickly eliminates the charge in the interface state traps through the de-trapping pulse, can effectively avoid the charge release phenomenon of the ferroelectric field-effect transistor during subsequent data retention, and greatly enhances the data retention reliability of the storage array in the storage device based on the ferroelectric field-effect transistor.
[0023] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically given below. Brief Description of the Drawings
[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:
[0025] Figure 1 A schematic flowchart of a data retention method based on pulses provided by an embodiment of the present invention is shown;
[0026] Figure 2 A schematic diagram of multiple first de-trapping pulses implemented after performing a programming operation on a ferroelectric field-effect transistor provided by an embodiment of the present invention is shown;
[0027] Figure 3 A schematic diagram of multiple second de-trapping pulses implemented after performing an erasing operation on a ferroelectric field-effect transistor provided by an embodiment of the present invention is shown;
[0028] Figure 4 A schematic diagram of the principle of quickly eliminating the charge in the interface state trap through a de-trapping pulse provided by an embodiment of the present invention is shown;
[0029] Figure 5 The figure shows a schematic structural diagram of a pulse-based data retention device provided by an embodiment of the present invention. Detailed implementation manners
[0030] In the following, the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0031] Currently, because the retention performance of ferroelectric field effect transistors is poor, especially when ferroelectric field effect transistors are used as memory cells, during the programming and erasing operations of ferroelectric field effect transistors, interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistors, as well as the interface between the ferroelectric layer and the gate insulating layer, will capture charges. And during the subsequent data retention process, the charges captured by the interface state traps will be gradually released, resulting in the threshold voltage drift of the ferroelectric field effect transistors, which is not conducive to the reliability of the memory cells. Therefore, the data retention reliability of the memory array in the current memory device using ferroelectric field effect transistors as memory cells is poor.
[0032] In view of the above problems, in one embodiment, as Figure 1 shown, a pulse-based data retention method is provided. Taking the application of this method to a memory device as an example for description, wherein the memory device uses ferroelectric field effect transistors as memory cells, and the method includes the following steps:
[0033] 101. Monitor whether the ferroelectric field effect transistor has performed a data erase / write operation.
[0034] Among them, a ferroelectric field effect transistor (FeFET) is a field effect transistor with ferroelectric properties. It utilizes the non-volatile memory property of ferroelectric materials, implants field effects and charge accumulation therein, and realizes a long-term stable memory effect, which is one of the very promising memory schemes. Further, the data erase / write operation can be a programming operation or an erasing operation performed on the field effect transistor with ferroelectric properties.
[0035] Specifically, it can be determined in real time whether the ferroelectric field effect transistor has been subjected to a data erase / write operation. Here, the data erase / write operation performed on the ferroelectric field effect transistor can be determined based on a computer program.
[0036] 102. After the ferroelectric field effect transistor has performed the data erase / write operation, apply multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor to improve the data retention ability of the memory cell during the data retention process.
[0037] Among them, the de-trapping pulse can be a charge de-trapping pulse, the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing and writing pulse, the data erasing and writing pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor to perform the data erasing and writing operation on the ferroelectric field effect transistor, and the amplitude of the de-trapping pulse is less than the amplitude of the data erasing and writing pulse.
[0038] The pulse-based data retention method provided in this embodiment first determines in real time the data erasing and writing operation performed on the ferroelectric field effect transistor, and then, after the ferroelectric field effect transistor has completed the data erasing and writing operation, applies multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor, that is, applies multiple de-trapping pulse waveforms to the gate electrode metal of the ferroelectric field effect transistor to improve the subsequent data retention characteristics of the storage unit. Here, the pulse direction of the de-trapping pulse is opposite to the direction of the pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor when performing the data erasing and writing operation on the ferroelectric field effect transistor, so as to eliminate the charges trapped by the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the interface state traps between the ferroelectric layer and the gate insulating layer during the data erasing and writing process. The technical solution of this application quickly eliminates the charges in the interface state traps through the de-trapping pulse, can effectively avoid the charge release phenomenon of the ferroelectric field effect transistor during the subsequent data retention process, avoid the threshold voltage drift, and greatly enhance the data retention reliability of the storage array in the storage device based on the ferroelectric field effect transistor.
[0039] In one embodiment, the data erasing and writing operation includes a programming operation, and the de-trapping pulse includes a first de-trapping pulse; when monitoring whether the ferroelectric field effect transistor has performed a data erasing and writing operation, it can be determined in real time whether the ferroelectric field effect transistor has performed a programming operation; further, the implementation manner of step 102 can be: after the ferroelectric field effect transistor has performed the programming operation, apply multiple first de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor. Among them, the pulse direction of the first de-trapping pulse is opposite to the pulse direction of the programming pulse, and the programming pulse is a pulse applied by the storage device to the gate electrode of the ferroelectric field effect transistor after performing the programming operation on the ferroelectric field effect transistor.
[0040] Here, applying the first de-trapping pulse to the gate electrode metal of the ferroelectric field effect transistor that has performed the programming operation can effectively eliminate the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the charges trapped by the interface between the ferroelectric layer and the gate insulating layer, prevent the charges in the interface from being released during the subsequent data retention process of the ferroelectric field effect transistor, and cause the threshold voltage of the ferroelectric field effect transistor to drift, and significantly improve the stability of the storage unit.
[0041] Specifically, after the ferroelectric field effect transistor is subjected to a programming operation, a plurality of first de-trapping pulses are applied to the gate electrode metal of the ferroelectric field effect transistor to release the interface state traps located between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the charges captured at the interface between the ferroelectric layer and the gate insulating layer during the programming process. The charges in the interface are quickly eliminated by the first de-trapping pulses. Among them, the number of times the first de-trapping pulses are applied, the interval time between two adjacent first de-trapping pulses, and the duration of each first de-trapping pulse can be determined according to the actual situation. In the embodiment provided by the present application, the pulse duration of applying a plurality of pulses to the gate electrode metal of the ferroelectric field effect transistor that has undergone the programming operation is relatively short. Compared with the method of applying a single first de-trapping pulse with a relatively long pulse duration to the gate electrode metal, it can avoid having too much impact on the semiconductor surface potential of the ferroelectric field effect transistor. At the same time, since the amplitudes of the plurality of first de-trapping pulses applied to the gate electrode metal of the ferroelectric field effect transistor gradually increase, the polarization of the ferroelectric layer can be kept unchanged to the greatest extent, so that the stored data does not change, and the reliability of the storage unit is improved.
[0042] In one embodiment, among the plurality of first de-trapping pulses, according to the time sequence of being applied to the gate electrode metal, the amplitude of the first de-trapping pulse increases successively. As Figure 2 shown, after the ferroelectric field effect transistor is subjected to the programming operation, that is, after a programming pulse is applied to the gate electrode of the ferroelectric field effect transistor, a plurality of first de-trapping pulses are applied to the gate electrode metal of the ferroelectric field effect transistor. The number of times the first de-trapping pulses are applied shown in the figure is three. In the actual working process, the number of times the first de-trapping pulses are applied can be determined according to the actual situation, and it is also applicable to this embodiment. As shown in the figure, the amplitude of each first de-trapping pulse applied to the gate electrode metal is different. A stepped charge de-trapping pulse is used as the first de-trapping pulse. As the number of times the first de-trapping pulse applied to the gate electrode metal increases, the amplitude of the first de-trapping pulse gradually increases.
[0043] Specifically, in every two consecutive first de-trapping pulses applied to the gate electrode metal, the amplitude of the later-applied first de-trapping pulse can be greater than that of the previously-applied first de-trapping pulse. Here, if the amplitudes of multiple first de-trapping pulses are the same, the effect of charge de-trapping will be weakened due to the enhanced electric field in the gate insulating layer. Therefore, the amplitude of the first de-trapping pulse can be increased step by step to avoid the problem of weakened charge de-trapping effect, so that the ferroelectric field effect transistor can avoid data loss during data retention and provide more complete stored data in subsequent read operations. In the embodiments provided in this application, a stepped charge de-trapping pulse is adopted. As the number of pulses increases, the amplitude of the charge de-trapping pulse gradually increases, which can effectively reduce the charge trapped by the interface state traps while keeping the original threshold voltage of the FeFET basically unchanged, thereby improving the data retention characteristics of the FeFET.
[0044] In one embodiment, the time interval between two adjacent first de-trapping pulses applied to the gate electrode metal is less than or equal to a first preset time interval. Here, the time length of the first preset time interval can be determined according to the actual situation. Further, the amplitude of the first de-trapping pulse is less than the amplitude of the programming pulse. Among them, the programming operation means applying a positive pulse to the gate electrode of the ferroelectric field effect transistor. Under the action of this pulse, the polarization direction of the ferroelectric layer of the transistor will point to the channel direction, and at this time the channel is in a low-resistance state, and the programming is completed. While the programming pulse realizes the programming operation, it will cause the electrons in the channel to be trapped by the interface layer. The role of the first de-trapping pulse is to eliminate these electrons. Therefore, the pulse directions of the programming pulse and the first de-trapping pulse are opposite. The first de-trapping pulse needs to eliminate the excess electrons in the interface without changing the polarization direction of the ferroelectric layer after programming, so the amplitude of the first de-trapping pulse is less than the amplitude of the programming pulse. The embodiments provided in this application can more stably eliminate the interface state traps located between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the charge trapped at the interface between the ferroelectric layer and the gate insulating layer, effectively improving the data retention reliability of the memory array in the memory device based on the ferroelectric field effect transistor.
[0045] In one embodiment, the data erase-write operation includes an erase operation; the de-trapping pulse further includes a second de-trapping pulse; the process of monitoring whether the ferroelectric field effect transistor has performed a data erase-write operation can be to determine in real time whether the ferroelectric field effect transistor has performed an erase operation; further, the implementation manner of step 102 can be: First, after the ferroelectric field effect transistor has performed the erase operation, apply multiple second de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor.
[0046] Among them, the pulse direction of the second de-trapping pulse is opposite to that of the erasing pulse, and the erasing pulse is a pulse applied by the memory device to the gate electrode of the ferroelectric field effect transistor after performing an erasing operation on the ferroelectric field effect transistor.
[0047] Here, applying a second de-trapping pulse to the gate electrode metal of the ferroelectric field effect transistor that has undergone an erasing operation can effectively remove the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the charges trapped at the interface between the ferroelectric layer and the gate insulating layer, preventing the threshold voltage of the ferroelectric field effect transistor from drifting due to the release of charges in the interface during subsequent data retention, and significantly improving the stability of the memory cell. Further, in this embodiment, the duration of applying multiple pulses to the gate electrode metal of the ferroelectric field effect transistor that has undergone an erasing operation is relatively short. Compared with the method of applying a single pulse with a relatively long duration to the gate electrode metal as the second de-trapping pulse, it can avoid having too much impact on the semiconductor surface potential of the ferroelectric field effect transistor and prevent data loss caused by the polarization of the ferroelectric layer (FE) of the ferroelectric field effect transistor.
[0048] Specifically, after the ferroelectric field effect transistor has undergone an erasing operation, multiple second de-trapping pulses are applied to the gate electrode metal of the ferroelectric field effect transistor to eliminate the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field effect transistor and the charges trapped at the interface between the ferroelectric layer and the gate insulating layer during the erasing process. The charges in the interface are quickly eliminated by the second de-trapping pulses. Among them, the number of times of applying the second de-trapping pulse, the interval time between two adjacent second de-trapping pulses, and the duration of each second de-trapping pulse can be determined according to the actual situation.
[0049] In one embodiment, among the multiple second de-trapping pulses, according to the time sequence of being applied to the gate electrode metal, the amplitude of the second de-trapping pulse increases successively. As Figure 3 shown, after performing the erasing operation on the ferroelectric field effect transistor, that is, after applying an erasing pulse to the gate electrode of the ferroelectric field effect transistor, multiple second de-trapping pulses are applied to the gate electrode metal of the ferroelectric field effect transistor. The number of times of applying the second de-trapping pulse shown in the figure is three. In the actual working process, the number of times of applying the second de-trapping pulse can be determined according to the actual situation and is also applicable to this embodiment. As shown in the figure, the amplitude of each second de-trapping pulse applied to the gate electrode metal is different. A stepped charge de-trapping pulse is adopted. As the number of times of applying the second de-trapping pulse to the gate electrode metal increases, the amplitude of the second de-trapping pulse gradually increases.
[0050] Specifically, in every two consecutive second de-trapping pulses applied to the gate electrode metal, the amplitude of the later-applied second de-trapping pulse can be made greater than that of the previously-applied second de-trapping pulse. Here, if the amplitudes of multiple second de-trapping pulses are the same, the effect of charge de-trapping will be weakened due to the enhanced electric field in the gate insulating layer. Therefore, the amplitude of the second de-trapping pulse can be increased step by step to avoid the problem of weakened charge de-trapping effect, so that the ferroelectric field-effect transistor can avoid data loss during data retention and provide more complete stored data in subsequent read operations. In the embodiments provided in this application, stepwise charge de-trapping pulses are used. As the number of pulses increases, the amplitude of the charge de-trapping pulse gradually increases, which can effectively reduce the charge trapped by interface state traps while keeping the original threshold voltage of the FeFET basically unchanged, thereby improving the data retention characteristics of the FeFET.
[0051] In one embodiment, the time interval between two adjacent second de-trapping pulses applied to the gate electrode metal is less than or equal to a second preset time interval. Here, the time length of the second preset time interval can be determined according to actual situations. Further, the amplitude of the second de-trapping pulse is less than the amplitude of the erase pulse. The embodiments provided in this application can more stably eliminate the charge trapped by the interface state traps between the gate insulating layer and the semiconductor channel of the ferroelectric field-effect transistor and the interface between the ferroelectric layer and the gate insulating layer, significantly improving the data retention reliability of the memory array in the memory device based on the ferroelectric field-effect transistor.
[0052] Further, based on Figure 4 , taking the ferroelectric field-effect transistor after a programming operation as an example, the principle of quickly eliminating the charge in the interface state traps through de-trapping pulses to effectively avoid the phenomenon of charge release in the subsequent data retention process of the ferroelectric field-effect transistor is illustrated; as shown in the figure, after a programming operation, the interface charge between the ferroelectric layer and the insulating layer of the ferroelectric field-effect transistor, as well as the interface charge between the insulating layer and the semiconductor, will capture charges; when a first de-trapping pulse is applied to the gate electrode metal of the ferroelectric field-effect transistor once, the charge trapped by the interface state traps will be partially eliminated. As the de-trapping pulses are gradually applied, the electric field in the gate insulating layer will be enhanced. If the amplitude of the de-trapping pulse remains unchanged, the charge de-trapping effect will be weakened. Therefore, stepwise charge de-trapping pulses are used. As the number of pulses increases, the amplitude of the charge de-trapping pulse gradually increases, which can effectively reduce the trapped charge while keeping the original threshold voltage of the ferroelectric field-effect transistor basically unchanged, thereby improving the data retention characteristics of the ferroelectric field-effect transistor.
[0053] The data retention method based on pulses provided in this embodiment first determines in real time the programming operation or erasing operation performed on the ferroelectric field-effect transistor. Then, after the ferroelectric field-effect transistor has completed the programming operation or erasing operation, multiple de-trapping pulses are applied to the gate electrode metal of the ferroelectric field-effect transistor. Among them, the amplitude of each de-trapping pulse is different, and the amplitude of the de-trapping pulse is increased step by step, so as to effectively reduce the charge trapped by the interface state traps on the basis of ensuring that the original threshold voltage of the FeFET remains basically unchanged, prevent the charge release phenomenon from occurring in the ferroelectric field-effect transistor during subsequent data retention, and greatly enhance the data retention reliability of the memory array in the memory device based on the ferroelectric field-effect transistor.
[0054] Further, as Figure 1 a specific implementation of the method shown, this embodiment provides a data retention device based on pulses, as Figure 5 shown. The device includes: an operation monitoring module 51 and a pulse execution module 52.
[0055] The operation monitoring module 51 can be used to monitor whether the ferroelectric field-effect transistor has performed a data erasing or writing operation.
[0056] The pulse execution module 52 can be used to apply multiple de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor after the ferroelectric field-effect transistor has performed the data erasing or writing operation, so as to improve the data retention ability of the storage unit during the data retention process. Among them, the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing or writing pulse, the data erasing or writing pulse is the pulse applied to the gate electrode of the ferroelectric field-effect transistor by the memory device when performing the data erasing or writing operation on the ferroelectric field-effect transistor, and the amplitude of the de-trapping pulse is smaller than the amplitude of the data erasing or writing pulse.
[0057] In a specific application scenario, the operation monitoring module 51 can specifically be used to determine in real time whether the ferroelectric field-effect transistor has performed a programming operation.
[0058] In a specific application scenario, the operation monitoring module 51 can specifically be used to determine in real time whether the ferroelectric field-effect transistor has performed an erasing operation.
[0059] In a specific application scenario, the pulse execution module 52 can specifically be used to apply multiple first de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor after the ferroelectric field-effect transistor has performed the programming operation. Among them, the pulse direction of the first de-trapping pulse is opposite to the pulse direction of the programming pulse, and the programming pulse is the pulse applied to the gate electrode of the ferroelectric field-effect transistor by the memory device after performing the programming operation on the ferroelectric field-effect transistor.
[0060] In a specific application scenario, the pulse execution module 52 can be specifically used to apply multiple second de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor after the ferroelectric field effect transistor has performed the erasing operation, where the pulse direction of the second de-trapping pulse is opposite to the pulse direction of the erasing pulse, and the erasing pulse is the pulse applied to the gate electrode of the ferroelectric field effect transistor by the storage device after performing the erasing operation on the ferroelectric field effect transistor.
[0061] It should be noted that for other corresponding descriptions of the various functional units involved in the pulse-based data retention device provided in this embodiment, reference can be made to Figure 1 the corresponding descriptions therein, which will not be elaborated here.
[0062] Based on the above method as Figure 1 shown, correspondingly, this embodiment also provides a storage medium on which a computer program is stored, and when the program is executed by a processor, it implements the pulse-based data retention method as Figure 1 shown above.
[0063] Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, and the software product to be recognized can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), including several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in various implementation scenarios of the present application.
[0064] Based on the above method as Figure 1 shown, and Figure 5 the embodiment of the pulse-based data retention device shown, in order to achieve the above object, this embodiment also provides an entity device for pulse-based data retention, which can specifically be a personal computer, server, smart phone, tablet computer, smart watch, or other network device, etc. The entity device includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to implement the method as Figure 1 shown above.
[0065] Optionally, the entity device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, sensors, an audio circuit, a WI-FI module, etc. The user interface may include a display screen (Display), an input unit such as a keyboard (Keyboard), etc. Optionally, the user interface may further include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc.
[0066] Those skilled in the art can understand that the physical device structure for pulse-based data retention provided in this embodiment does not limit the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.
[0067] The storage medium may further include an operating system and a network communication module. The operating system is a program for managing the hardware of the above physical device and software resources to be recognized, and supports the operation of information processing programs and other software and / or programs to be recognized. The network communication module is used to implement communication between components inside the storage medium, as well as communication between other hardware and software in the information processing physical device.
[0068] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus a necessary general hardware platform, or can also be implemented by hardware. By applying the technical solution of this application, first, monitor whether the ferroelectric field effect transistor has performed a data erasing and writing operation; then, after the ferroelectric field effect transistor has performed the data erasing and writing operation, apply multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor to improve the data retention ability of the storage unit during the data retention process, where the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing and writing pulse, the data erasing and writing pulse is the pulse applied to the gate electrode of the ferroelectric field effect transistor when the storage device performs the data erasing and writing operation on the ferroelectric field effect transistor, and the amplitude of the de-trapping pulse is less than the amplitude of the data erasing and writing pulse. Compared with the prior art, it can significantly enhance the data retention reliability of the storage array in the storage device.
[0069] Those skilled in the art can understand that the drawings are only schematic diagrams of a preferred embodiment scenario, and the modules or processes in the drawings are not necessarily essential for implementing this application. Those skilled in the art can understand that the modules in the device in the embodiment scenario can be distributed in the device in the embodiment scenario according to the description of the embodiment scenario, or can be correspondingly changed and located in one or more devices different from this embodiment scenario. The modules in the above embodiment scenario can be combined into one module, or can be further split into multiple sub-modules.
[0070] The above serial numbers of this application are only for description and do not represent the advantages or disadvantages of the embodiment scenario. The above disclosure is only several specific embodiment scenarios of this application. However, this application is not limited thereto, and any change that can be thought of by those skilled in the art should fall within the protection scope of this application.
Claims
1. A pulse-based data retention method, applied to a storage device, wherein, The storage device uses ferroelectric field-effect transistors as memory cells, and is characterized in that the method includes: Monitoring whether the ferroelectric field-effect transistor has performed a data erasing and writing operation; After the ferroelectric field-effect transistor has performed the data erasing and writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor to improve the data retention ability of the memory cell during the data retention process, wherein the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing and writing pulse, the data erasing and writing pulse is a pulse applied to the gate electrode of the ferroelectric field-effect transistor by the storage device when performing the data erasing and writing operation on the ferroelectric field-effect transistor, and the amplitude of the de-trapping pulse is less than the amplitude of the data erasing and writing pulse.
2. The method according to claim 1, characterized in that, The data erasing and writing operation includes a programming operation; the de-trapping pulse includes a first de-trapping pulse; and the monitoring of whether the ferroelectric field-effect transistor has performed a data erasing and writing operation includes: Determining in real time whether the ferroelectric field-effect transistor has performed a programming operation; The step of, after the ferroelectric field-effect transistor has performed the data erasing and writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor to improve the data retention ability of the memory cell during the data retention process includes: After the ferroelectric field-effect transistor has performed the programming operation, applying multiple first de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor, wherein the pulse direction of the first de-trapping pulse is opposite to the pulse direction of the programming pulse, and the programming pulse is a pulse applied to the gate electrode of the ferroelectric field-effect transistor by the storage device after performing a programming operation on the ferroelectric field-effect transistor.
3. The method according to claim 2, characterized in that, Among the multiple first de-trapping pulses, according to the time sequence applied to the gate electrode metal, the amplitude of the first de-trapping pulse increases successively.
4. The method according to claim 3, characterized in that, The time interval between two adjacent first de-trapping pulses applied to the gate electrode metal is less than or equal to a first preset time interval.
5. The method according to claim 1, characterized in that, The data erasing and writing operation includes an erasing operation; the de-trapping pulse further includes a second de-trapping pulse; and the monitoring of whether the ferroelectric field-effect transistor has performed a data erasing and writing operation includes: Determining in real time whether the ferroelectric field-effect transistor has performed an erasing operation; The step of, after the ferroelectric field-effect transistor has performed the data erasing and writing operation, applying multiple de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor to improve the data retention ability of the memory cell during the data retention process includes: After the ferroelectric field-effect transistor has performed the erasing operation, applying multiple second de-trapping pulses to the gate electrode metal of the ferroelectric field-effect transistor, wherein the pulse direction of the second de-trapping pulse is opposite to the pulse direction of the erasing pulse, and the erasing pulse is a pulse applied to the gate electrode of the ferroelectric field-effect transistor by the storage device after performing an erasing operation on the ferroelectric field-effect transistor.
6. The method according to claim 5, characterized in that, Among the multiple second de-trapping pulses, according to the time sequence of being applied to the gate electrode metal, the amplitudes of the second de-trapping pulses increase successively.
7. The method according to claim 6, characterized in that, The time interval between two adjacent second de-trapping pulses applied to the gate electrode metal is less than or equal to a second preset time interval.
8. A pulse-based data retention device, characterized in that, The device includes: An operation monitoring module, configured to monitor whether the ferroelectric field effect transistor has performed a data erasing and writing operation; A pulse execution module, configured to apply multiple de-trapping pulses to the gate electrode metal of the ferroelectric field effect transistor after the ferroelectric field effect transistor has performed the data erasing and writing operation, so as to improve the data retention ability of the storage unit during the data retention process. Wherein, the pulse direction of the de-trapping pulse is opposite to the pulse direction of the data erasing and writing pulse, the data erasing and writing pulse is a pulse applied to the gate electrode of the ferroelectric field effect transistor when the storage device performs the data erasing and writing operation on the ferroelectric field effect transistor, and the amplitude of the de-trapping pulse is less than the amplitude of the data erasing and writing pulse.
9. A storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.
10. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.