Method for controlling etching and related product

Abstract

The invention discloses a method for controlling etching and a related product, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: detecting the width of a back etching mark of an etched wafer; and according to the width of the back etching mark, adjusting the distance between a component for controlling the etching of the wafer in the etching machine and the wafer. According to the method, the etching area error in the edge etching process can be accurately identified by detecting the width of the etching mark on the back surface of the wafer; after the distance between the wafer and the component for controlling the etching of the wafer in the etching machine is adjusted according to the width of the back etching mark, the wafer etching process can be controlled to recover to the standard process. Furthermore, according to the method, after the edge etching of the wafer is completed, the width of the etching mark on the back surface of the wafer can be detected in real time, and the distance between a component for controlling the etching of the wafer in the etching machine and the wafer can be adjusted in real time, so that the precision of the edge etching process and the yield of semiconductor products can be improved through a real-time feedback mechanism.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing technology. More specifically, the present invention relates to a method for controlling etching and related products. Background Art

[0002] With the progress of semiconductor technology, the size of semiconductors has been continuously reduced. At the same time, the complexity of semiconductor processes and the defect rate of semiconductor products have been increasing. Semiconductor products are usually produced in the central area of a wafer through processes such as lithography, deposition, and etching; in a wafer, the area outside the central area is the edge area. During the processes for the central area, some residual particles and films may fall on the front and back of the edge area of the wafer, resulting in wafer edge defects such as peeling, delamination, particle contamination, arcing, and micromasking; wafer edge defects are an important reason for the increase in the defect rate of semiconductor products. Reducing wafer edge defects through bevel etch process is an important method to improve the yield of semiconductor products.

[0003] In the existing bevel etch process, due to the lack of an anomaly detection mechanism, when the distance between the top plate and the wafer becomes abnormal, the etching machine is not stopped for adjustment until the etching rate of the semiconductor product is too low or too high, resulting in poor bevel etch quality for multiple batches of wafers.

[0004] In view of this, there is an urgent need to provide a bevel etch solution to timely identify the distance error between the top plate and the wafer, thereby immediately adjusting the etching area and reducing the number of defective semiconductor products. Summary of the Invention

[0005] In order to solve at least one or more of the technical problems described in the above background art section, the present invention proposes the following technical solutions and multiple embodiments thereof.

[0006] In a first aspect, the present invention discloses a method for controlling etching, including: detecting the width of the back etching marks of an etched wafer; and adjusting the distance between the components in the etching machine that control the etching of the wafer according to the width of the back etching marks.

[0007] In a second aspect, the present invention discloses a device for controlling etching, including a processor configured to execute program instructions; and a memory configured to store program instructions, which, when loaded and executed by the processor, cause the device to execute the method according to the first aspect.

[0008] In a third aspect, the present invention discloses a computer-readable storage medium storing program instructions adapted to be loaded and executed by a processor to perform the method according to the first aspect.

[0009] In a fourth aspect, the present invention discloses an etching system, comprising: an etching mark detection device configured to detect the width of an etching mark on the back surface of an etched wafer; an etching machine configured to etch the wafer; and to adjust the distance between the components in the etching machine that control the etching of the wafer and the wafer according to the width of the back surface etching mark detected by the etching mark detection device.

[0010] Compared with the prior art, the unexpected technical effect of the present application is that: by the proposed method, device, computer-readable storage medium and etching system for controlling etching, after the etching machine completes the edge etching operation on the previous wafer, the etching area for the subsequent wafer is accurately adjusted according to the width of the etching mark on the back surface of the previous wafer, thereby helping to improve the manufacturing precision and yield of semiconductor products. Further, after completing the edge etching operation on a small number of wafers, that is, detecting the width of the etching mark on the back surface of the wafer after edge etching and adjusting the etching machine by the automatic process controller of the etching machine, an immediate adjustment of the edge etching process can be achieved, reducing the number of defective semiconductor products. Description of the Drawings

[0011] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the drawings, several embodiments of the present invention are shown by way of example and not limitation, and identical or corresponding reference numerals denote identical or corresponding parts, wherein: Figure 1 An exemplary schematic diagram of the edge region of a wafer in some embodiments of the present invention is shown.

[0012] Figure 2 An exemplary schematic diagram of the wafer edge etching process in some embodiments of the present invention is shown.

[0013] Figure 3 An exemplary schematic diagram of the relationship between the distance between the top plate and the wafer and the etching area in some embodiments of the present invention is shown.

[0014] Figure 4 An exemplary flowchart of the method for controlling etching in some embodiments of the present invention is shown.

[0015] Figure 5 An exemplary schematic diagram of the etching mark on the back surface of a wafer in some embodiments of the present invention is shown.

[0016] Figure 6Shows an exemplary schematic diagram of the structure of an etching machine in some embodiments of the present invention.

[0017] Figure 7 Shows Figure 6 A partial enlarged view of the area A corresponding to the dashed box.

[0018] Figure 8 Shows an exemplary schematic diagram of a method for controlling etching in some embodiments of the present invention.

[0019] Figure 9 Shows a block diagram of the hardware configuration of a device that can implement the embodiments of the present invention. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] It should be understood that the terms "including" and "comprising" used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0022] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification and claims of the present invention, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0023] As used in this specification and the claims, the term "if" can be interpreted as "when...", "once", "in response to determining", or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detecting [the described condition or event]" can be interpreted as meaning "once determined", "in response to determining", "once detecting [the described condition or event]", or "in response to detecting [the described condition or event]" depending on the context.

[0024] Next, the detailed implementation manners of the present invention will be described in detail in conjunction with the accompanying drawings.

[0025] With the progress of semiconductor technology, the size of semiconductors has been continuously shrinking. At the same time, the complexity of semiconductor processes and the defect rate of semiconductor products have been increasing. Semiconductor products such as chips and memory devices are usually produced in the central region of a wafer through processes such as lithography, deposition, and etching; in a wafer, the region outside the central region is the edge region. Figure 1 An exemplary schematic diagram of the edge region of a wafer in some embodiments of the present invention is shown. In some embodiments, the edge region of the wafer is an annular region with a width of 2 - 3 mm from the wafer edge to the wafer center. As Figure 1 shown, there are 5 important regions in the edge region of the wafer: the front straight edge and the front bevel edge on the front side of the wafer, the back straight edge and the back bevel edge on the back side of the wafer, and the vertex connecting the front and back sides of the wafer. During the production process, some residual particles and films may fall on the front and back sides of the edge region of the wafer, resulting in wafer edge defects. Wafer edge defects such as peeling, delamination, particle contamination, arc, and micro-masking are an important reason for the increase in the defect rate of semiconductor products.

[0026] The wafer edge etching process can remove any type of film and residual particles in the edge region of the wafer, thereby overcoming wafer edge defects, which is an important method to improve the yield of wafers. Figure 2 An exemplary schematic diagram of the wafer edge etching process in some embodiments of the present invention is shown. As Figure 2 shown, the wafer is placed on the bottom plate in the etching machine, and the central region of its front side is covered by the top plate in the etching machine. There is a small gap between the top plate in the etching machine and the front side of the wafer, and inert gases such as nitrogen (N2), argon (Ar), and helium (He) are diffused in the gap to prevent plasma gas from entering the central region of the front side of the wafer. It can be understood that except for the central region blocked by the top plate and the bottom plate, only the edge region of the wafer is exposed to the plasma gas, so that the front side, back side, and vertex of the edge region are etched by the plasma gas to remove the film, residual particles, and other impurities in the edge region of the wafer; in some embodiments, the plasma gas is obtained by ionizing chlorine (Cl2), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), hydrogen bromide (HBr), or fluorine gas (F2).

[0027] It can be understood that the distance between the top plate and the wafer (which can be the distance from any plane on the upper or lower surface of the top plate to the front or back side of the wafer) affects the wafer region that the plasma gas can etch. Figure 3 An exemplary schematic diagram of the relationship between the distance between the top plate and the wafer and the etching region in some embodiments of the present invention is shown. As Figure 3 shown in subfigure (a) of, in the standard process, the distance between the top plate and the wafer is the standard distance D std, at this time, the plasma gas is used to etch the entire wafer edge region, that is, the edge region on the front side of the wafer, the edge region on the back side, and the vertices in the edge region. As Figure 3 shown in sub - figure (b) of Figure 3 , when the distance between the top plate and the wafer is greater than the standard distance, at this time, the plasma gas can diffuse from the wafer edge to the wafer center region, thereby etching more front - side regions; since more plasma gas is used to etch the front side of the wafer, it causes over - etching of the front side of the wafer, damaging the center region of the wafer; at the same time, the plasma gas used to etch the back side of the wafer decreases, resulting in under - etching of the back side of the wafer. As

[0028] shown in sub - figure (c) of

[0029] Figure 4 It can be understood that, in the wafer edge etching process, whether it is the front side or the back side of the wafer, once over - etching or under - etching occurs, it will lead to a decrease in the yield of semiconductor products; therefore, the distance between the top plate and the wafer affects the precision of the edge etching process and the yield of semiconductor products. In the prior art, in the edge etching process, the distance from the top plate to the wafer of the etching machine is usually set to the standard height, and then the wafer is edge - etched; however, due to the lack of an abnormal detection mechanism, it is only possible to determine whether the etching machine is abnormal by monitoring the etching rate of the crystal plane, and the average monitoring time of the crystal plane etching rate is about 2 - 7 days. When the distance between the top plate and the wafer in the etching machine is abnormal, there will be problems with poor edge etching quality for multiple batches of wafers. In view of this, the present invention discloses a method for controlling etching to facilitate timely identification of the distance error between the top plate and the wafer in the edge etching process and improve the yield of semiconductor products. Figure 4 shown in

[0030] It can be understood that the etching described in step 401 includes edge etching of the wafer edge region; after using the etching machine to perform edge etching on the wafer, the back - side etching marks can be observed from the back side of the wafer, and the back - side etching marks show the etching region of the edge etching process on the back side. In some embodiments, the width of the back - side etching marks under the standard process is defined as the width standard value W std , that is, when the width of the back - side etching marks is W stdWhen the distance between the upper electrode assembly of the etching machine and the wafer (the distance between the upper electrode assembly and the wafer can be defined as the shortest distance between the two) is the standard distance D std ; in this case, during the edge etching process, the plasma gas can only etch the complete wafer edge region. After the edge etching of the wafer is completed, if it is detected that the width of the back etching mark on the wafer is not equal to W std , the distance between the upper electrode assembly and the wafer can be adjusted to D std , so as to restore the edge etching process to the standard process, that is, to accurately etch the complete wafer edge region.

[0031] Regarding the "component for controlling the etching of the wafer in the etching machine", it can be, as Figure 2 shown, the top plate disposed above the wafer in the edge etching process; as will be described later, in some embodiments, the top plate is the upper electrode assembly of the etching machine, which can be moved by the etching machine to adjust the distance between the upper electrode assembly and the wafer.

[0032] Generally speaking, the semiconductor manufacturing process can include eight steps: wafer processing, oxidation treatment, lithography, etching, thin film deposition, interconnection (that is, connecting each transistor and circuit element through metal wiring), testing, and packaging. Edge etching is a process in the etching step, which can remove residual particles, thin films and other impurities introduced to the wafer edge by the steps before etching (including etching). Step 401 in the embodiment of the present invention can include: immediately detecting the width of the back etching mark on the wafer after the edge etching of a wafer is completed; or, detecting the width of the back etching mark on the wafer after the thin film deposition or interconnection of a wafer is completed; or, detecting the width of the back etching mark on a wafer during the testing stage. It can be understood that since the edge etching process etches both the front and back of the wafer at the same time, after the edge etching of a wafer is completed, there will be etching marks on both the front and back of its edge region; therefore, if the detection is carried out after the edge etching of a wafer is completed, not only can the etching area targeted by the edge etching process be identified by detecting the width of the back etching mark on the wafer, but also the etching area targeted by the edge etching process can be identified by detecting the width of the front etching mark on the wafer edge region; and since the thin film deposition and interconnection steps will cover the front etching marks in the wafer edge region, then, if the detection is carried out after the thin film deposition or interconnection of a wafer is completed, or during the testing stage, the etching area targeted by the edge etching process can only be identified by detecting the width of the back etching mark. In the present invention, preferably, the width of the back etching mark on the wafer is detected during the testing stage, so as to introduce the method for controlling etching proposed by the present invention with relatively small changes to the semiconductor manufacturing process, and at the same time, the back etching marks on the wafer are easier to observe, thereby improving the accuracy of the etching area detection result.

[0033] It can be understood that the method for controlling etching disclosed in the present invention can accurately identify the etching area error in the edge etching process by detecting the width of the backside etching mark of the wafer; after adjusting the distance between the component for controlling the etching of the wafer in the etching machine and the wafer according to the width of the backside etching mark, the wafer etching process can be controlled to return to the standard process. Further, this method can immediately detect the width of the backside etching mark of the wafer after completing the edge etching operation on a small number of wafers, and the automatic process controller of the etching machine can adjust the distance between the component for controlling the etching of the wafer in the etching machine and the wafer, thereby improving the precision of the edge etching process and the yield of semiconductor products with an immediate feedback mechanism.

[0034] In some embodiments, detecting the width of the backside etching mark of the etched wafer includes: detecting the extension length of the backside etching mark from the wafer edge towards the wafer center; using the extension length as the width of the backside etching mark.

[0035] Figure 5 An exemplary schematic diagram of the backside etching mark of the wafer in some embodiments of the present invention is shown. As Figure 5 shown, after edge etching of the wafer, an annular backside etching mark can be observed from the backside of the wafer. The outer circumference of the etching mark ring is the outer edge of the wafer, and the inner circumference of the etching mark ring is the boundary of the backside etching mark. In an ideal situation, the area inside the boundary of the backside etching mark is the center area of the wafer. The extension length of the backside etching mark from the wafer edge towards the wafer center, that is, the ring width of this ring, is the width of the backside etching mark.

[0036] In some embodiments, adjusting the distance between the component for controlling the etching of the wafer in the etching machine and the wafer according to the width of the backside etching mark includes: in response to the width of the backside etching mark being greater than the width threshold, increasing the distance between the component and the wafer; in response to the width of the backside etching mark being less than the width threshold, decreasing the distance between the component and the wafer.

[0037] In these embodiments, the width threshold can be set to the width standard value W described above std , when the width of the backside etching mark is W std , the height of the height adjustment component corresponding to the top plate in the etching machine is the standard height H std , during the edge etching process, the plasma gas can only etch the complete wafer edge area. Combining the explanation of Figure 3 above, it can be understood that when the width of the backside etching mark is greater than W std , it means that the height of the height adjustment component is less than H std , at this time, the height adjustment component needs to be raised to H std ; when the width of the backside etching mark is less than W stdWhen it indicates that the height of the height adjustment component is greater than H std , at this time, it is necessary to lower the height adjustment component to H std .

[0038] In some embodiments, the method for controlling etching further includes: the component for controlling the etching of the wafer in the etching machine includes an upper electrode assembly for defining an etching area.

[0039] Figure 6 The exemplary schematic diagram of the structure of the etching machine in some embodiments of the present invention is shown. It can be understood that the etching machine usually has an axisymmetric shape. For the sake of simplicity, Figure 6 only half of the structure of the etching machine is shown; in addition, in Figure 6 the shown etching machine, only the constituent elements related to this embodiment are shown. It is obvious to those of ordinary skill in the art that: the etching machine may further include common constituent elements different from those shown in the figure, including but not limited to an etching machine gate, an etching machine support, an actuator, a radio frequency power source, an etching machine controller, etc. As Figure 6 shown, the etching machine mainly consists of an upper electrode assembly and a lower electrode assembly. The wafer is placed between the upper and lower electrode assemblies; the upper electrode assembly includes an upper electrode, an upper Plasma-Exclusion-Zone (PEZ) ring, and a central ceramic dielectric plate; the lower electrode assembly includes a lower electrode, a lower isolation ring, a lower PEZ, and a lower electrode plate. In some embodiments, the upper electrode assembly is connected to the support of the etching machine, and the support is connected to an actuator, so that the upper electrode assembly can be driven to move, and further the height of the upper electrode assembly can be adjusted.

[0040] Figure 7 shows Figure 6 the partial enlarged view of the area A corresponding to the dashed box. As Figure 7 shown, the reaction gas is injected into the area between the upper electrode and the lower electrode through the gap between the upper electrode and the upper PEZ ring. When the upper electrode and the lower electrode are provided with radio frequency power by a radio frequency power source and the radio frequency power is applied to the reaction gas, the reaction gas is ionized to form a plasma gas. The upper PEZ ring and the lower PEZ ring are used to prevent the plasma gas from etching the central area of the wafer; in some embodiments, pores for releasing inert gas are provided in the central ceramic dielectric plate, so as to further prevent the plasma gas from etching the central area of the wafer. It can be understood that Figure 6 the upper electrode assembly in Figure 2 is equivalent to the top plate in Figure 6 and the lower electrode assembly in Figure 2 is equivalent to the bottom plate in

[0041] In some embodiments, the upper PEZ and the central ceramic dielectric plate form a first integral body, and the first integral body can be controlled to move by an etching machine. By adjusting the height of the first integral body, the distance between the upper electrode assembly of the etching machine and the wafer can be adjusted; in these embodiments, the first integral body is the "component for controlling the etching of the wafer in the etching machine" described in step 402. In some other embodiments, the upper electrode assembly can be controlled to move by the etching machine. By adjusting the height of the upper electrode assembly, the distance between the upper electrode assembly of the etching machine and the wafer can be adjusted; in these embodiments, the upper electrode assembly is the "component for controlling the etching of the wafer in the etching machine" described in step 402.

[0042] It can be understood that the distance between the upper electrode assembly and the wafer can be achieved by raising the upper electrode assembly or the lower electrode assembly. In some embodiments, increasing the distance between the component and the wafer includes: raising the upper electrode assembly; decreasing the distance between the component and the wafer includes: lowering the upper electrode assembly.

[0043] In some embodiments, the method for controlling etching further includes: setting a width threshold according to the target etching area.

[0044] Generally speaking, the target etching area in the edge etching process refers to the edge area of the wafer. It can be understood that in order to overcome the wafer edge defects, it is necessary to achieve a covering etching of the wafer edge area, that is, to complete the etching of the front, back and vertices of the wafer, while ensuring that the central area of the wafer is not etched; in some embodiments, the etching mark width on the back of the wafer when the covering etching of the edge area is completed can be observed, and the etching mark width at this time is used as the width threshold. In some embodiments, the width threshold is set to mm.

[0045] With the development of other semiconductor-related industries such as the automotive electronics industry, the communication industry, the artificial intelligence and big data industries, the demand for semiconductor products is continuously increasing, and it is becoming more and more important to increase the production volume of semiconductor products on a single wafer. Expanding the central area of the wafer and shrinking the edge area of the wafer are important ways to increase the production volume of semiconductor products on a single wafer. Therefore, the wafer edge area will also change with the development of semiconductor-related industries. According to the embodiments of the present invention, the width threshold can be adaptively adjusted according to the size of the wafer edge area, and the target etching area of the edge etching process can be controlled, thereby helping semiconductor manufacturers to flexibly respond to changing production demands.

[0046] In some embodiments, adjusting the distance between the component for controlling the etching of the wafer in the etching machine and the wafer according to the width of the back etching mark includes: by Calculate the distance adjustment amount; adjust the distance between the component and the wafer according to the distance adjustment amount; where y is the distance adjustment amount; A is the adjustment coefficient. When the unit of y is meter (m) and the unit of x is millimeter (mm), A can take the value of 0.001; when the units of both x and y are millimeter or both are meter, A can take the value of 1; x is the detected width of the backside etch mark; z is a constant; in some embodiments, z represents the width threshold of the backside etch mark. For example: when z = mm and A = 1, if x = 2mm, then y = 0, that is, there is no need to adjust the distance between the component that controls the etching of the wafer in the etching machine and the wafer.

[0047] In these embodiments, a dedicated control program can be set in the Auto Process Control (APC) unit of the etching machine. This program takes the width of the backside etch mark detected on the wafer after edge etching as the input. When the program detects that the width of the backside etch mark is too small, it controls to reduce the distance between the component that controls the etching of the wafer in the etching machine and the wafer, and the value of the reduced distance is calculated according to the above formula Calculate; conversely, when the program detects that the width of the backside etch mark is too large, it controls to increase the distance between the component that controls the etching of the wafer in the etching machine and the wafer, and the value of the increased distance is calculated according to the above formula Calculate.

[0048] In some other embodiments, the associated data between the preset distance adjustment amount (i.e., the aforementioned y) and the width of the backside etch mark (i.e., the aforementioned x) (the associated data can take the form of a table, dictionary, or array) is stored in the automatic process controller of the etcher. After obtaining the actual detected width of the backside etch mark on the wafer that has completed edge etching, the distance adjustment amount corresponding to the actual detected width is queried in the associated data, and thus the distance between the component in the etcher that controls the etching of the wafer and the wafer is adjusted according to the queried distance adjustment amount. Table 1 shows the associated data between the distance adjustment amount and the backside etch mark in some embodiments of the present invention. When the distance adjustment amount is negative, it means that the distance between the component in the etcher that controls the etching of the wafer and the wafer needs to be reduced by this distance adjustment amount; when the distance adjustment amount is positive, it means that the distance between the component in the etcher that controls the etching of the wafer and the wafer needs to be increased by this distance adjustment amount. It can be understood that Table 1 exemplarily gives the detected widths of some backside etch marks and their corresponding distance adjustment amount values. As the table is continuously expanded, more detected widths of backside etch marks can be covered; in actual use, first, the detected width value of the backside etch mark closest to the actual detected width of the backside etch mark (denoted as x1) can be queried from the table, and the distance between the component in the etcher that controls the etching of the wafer and the wafer is adjusted according to the distance adjustment amount corresponding to x1.

[0049] Table 1

[0050] Figure 8 shows an exemplary schematic diagram of a method for controlling etching in some embodiments of the present invention, as Figure 8 shown. In these embodiments, after detecting the backside etch mark on the wafer, the adjustment method for the distance between the component in the etcher that controls the etching of the wafer and the wafer can be fed back to the etcher stage according to the set calculation formula or associated data in the APC. After adjusting the etcher stage, continue to produce products, thereby forming a closed loop of real-time monitoring and real-time adjustment, improving the precision of the wafer edge etching process and the yield of semiconductor products.

[0051] Furthermore, the present invention discloses a device for controlling etching, including: a processor configured to execute program instructions; and a memory configured to store program instructions. When the program instructions are loaded and executed by the processor, the device executes the methods described in the foregoing embodiments of the present invention.

[0052] Figure 9 shows a block diagram of the hardware configuration of a device 900 that can implement the embodiments of the present invention. As Figure 9As shown, the apparatus 900 may include a processor 901 and a memory 902. The processor is configured to execute program instructions, and the memory is configured to store program instructions. When the program instructions are loaded and executed by the processor, the apparatus is caused to execute the method for controlling etching described in any of the foregoing embodiments. In Figure 9 the apparatus 900, only the constituent elements relevant to this embodiment are shown. Therefore, it is obvious to those of ordinary skill in the art that: the apparatus 900 may further include common constituent elements different from those Figure 9 shown. The specific functions implemented by the memory 902 and the processor 901 of the apparatus 900 provided in the embodiments of this specification may be interpreted in contrast to the foregoing embodiments in this specification and can achieve the technical effects of the foregoing embodiments, which will not be elaborated here.

[0053] The apparatus 900 may correspond to a computing device having various processing functions. For example, the apparatus 900 may be implemented as various types of devices, such as a personal computer (PC), a server device, a mobile device, etc.

[0054] The processor 901 may control the operation of the apparatus 900. For example, the processor 901 may be implemented by a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an artificial intelligence processor chip (IPU), etc. provided in the apparatus 900. However, the present invention is not limited thereto. In this embodiment, the processor 901 may be implemented in any suitable manner. For example, the processor 901 may take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and a form of an embedded microcontroller, etc.

[0055] The memory 902 can be used to store various data and instructions processed in the device 900. For example, the memory 902 can store the processed data and the data to be processed in the device 900. The memory 902 can store the data that has been processed or is to be processed by the processor 901, such as the width data of the etch marks on the back side of the detected wafer. In addition, the memory 902 can store the applications, drivers, etc. to be driven by the device 900. For example, the memory 902 can store various programs related to the method for controlling etching to be executed by the processor 901. The memory 902 can be a DRAM, but the present invention is not limited thereto. The memory 902 can include at least one of volatile memory or non-volatile memory. The non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The volatile memory can include dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, ferroelectric RAM (FeRAM), etc. In some embodiments, the memory 902 can include at least one of a hard disk drive (HDD), a solid state drive (SSD), a high density flash (CF) card, a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, caches, or a memory stick.

[0056] Furthermore, the present invention discloses a computer-readable storage medium storing program instructions adapted to be loaded and executed by a processor to perform the methods described in the foregoing embodiments of the present invention.

[0057] Furthermore, the present invention discloses an etching system, including: an etch mark detection device configured to detect the width of the etch marks on the back side of an etched wafer; an etching machine configured to etch the wafer; and adjust the distance between the components in the etching machine that control the etching of the wafer and the wafer according to the width of the etch marks on the back side detected by the etch mark detection device.

[0058] In summary, the specific functions implemented by the device for controlling etching, the computer-readable storage medium, and the etching system provided in the embodiments of this specification can be interpreted in contrast to the foregoing embodiments in this specification and can achieve the technical effects of the foregoing embodiments, which will not be elaborated herein.

[0059] It should be noted that, for the purpose of simplicity, some methods and their embodiments of the present invention are expressed as a series of actions and their combinations. However, those skilled in the art can understand that the solutions of the present invention are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of the present invention, those skilled in the art can understand that some of the steps can be executed in other orders or simultaneously. Further, those skilled in the art can understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved are not necessarily required for the implementation of certain solutions of the present invention. In addition, according to different solutions, the present invention also focuses on the descriptions of some embodiments. In view of this, those skilled in the art can understand that for the parts not detailed in a certain embodiment of the present invention, they can also refer to the relevant descriptions of other embodiments.

Claims

1. A method for controlling etching, characterized in that, Comprising: Detecting the width of the backside etch marks of an etched wafer; Adjusting the distance between a component in an etching machine that controls the etching of the wafer and the wafer according to the width of the backside etch marks.

2. The method according to claim 1, characterized in that, Detecting the width of the backside etch marks of an etched wafer comprises: Detecting the extension length of the backside etch marks from the wafer edge towards the wafer center; Taking the extension length as the width of the backside etch marks.

3. The method according to claim 1, characterized in that, Adjusting the distance between a component in an etching machine that controls the etching of the wafer and the wafer according to the width of the backside etch marks comprises: In response to the width of the backside etch marks being greater than a width threshold, increasing the distance between the component and the wafer; In response to the width of the backside etch marks being less than the width threshold, decreasing the distance between the component and the wafer.

4. The method according to claim 3, characterized in that, The component in the etching machine that controls the etching of the wafer comprises an upper electrode assembly for defining an etching area.

5. The method according to claim 4, characterized in that, Increasing the distance between the component and the wafer comprises: raising the upper electrode assembly; Decreasing the distance between the component and the wafer comprises: lowering the upper electrode assembly.

6. The method according to claim 3, characterized in that, Further comprising: Setting the width threshold according to a target etching area.

7. The method according to claim 1, characterized in that, Adjusting the distance between a component in an etching machine that controls the etching of the wafer and the wafer according to the width of the backside etch marks comprises: By calculating a distance adjustment amount; Adjusting the distance between the component and the wafer according to the distance adjustment amount; wherein, y is the distance adjustment amount; A is an adjustment coefficient; x is the detected width of the backside etch marks; z is a constant.

8. An apparatus for controlling etching, characterized in that, Comprising: A processor configured to execute program instructions; and A memory configured to store the program instructions, which when loaded and executed by the processor, cause the device to execute the method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, Stored with program instructions adapted to be loaded and executed by a processor to execute the method according to any one of claims 1-7.

10. An etching system, characterized in that, Comprising: An etch mark detection device configured to: detect the width of the backside etch marks of an etched wafer; An etching machine configured to: Etch the wafer; and Adjust the distance between a component in the etching machine that controls the etching of the wafer and the wafer according to the width of the backside etch marks detected by the etch mark detection device.

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