Circuit and system for driving integrated semiconductor laser

Abstract

The application claims a charging unit for driving an integrated semiconductor laser. The charging unit may include a first input terminal for receiving input driving energy, a second input terminal for being configured to enable or disable the charging unit, a third input terminal for being configured to receive a charge control PWM signal, and a plurality of output terminals. The charging unit may be configured to switch on / off the plurality of output terminals in a predetermined pattern according to a charge control PWM signal.

Description

[0001] Related References

[0002] This application claims the priority and benefit of U.S. Patent Application No. 63 / 612,172, filed on December 19, 2023, and incorporates herein by reference the entire content of the foregoing patent application. Technical Field

[0003] This application relates to an electronic circuit, and more particularly but not limited to circuits and systems for driving integrated semiconductor lasers. Background Art

[0004] Today, lidar is widely used in advanced driver assistance systems (ADAS) in automotive applications. One challenge lies in how to drive highly integrated semiconductor laser devices, such as vertical-cavity surface-emitting lasers ("VCSEL") semiconductor lasers that integrate a laser unit array in solid-state lidar, in order to individually control each VCSEL unit in the array. The semiconductor laser emission units of the semiconductor lasers need to receive pulsed current provided by a laser driving device. Existing semiconductor laser driving solutions are based on discrete gallium nitride field-effect transistors (hereinafter simply referred to as "gallium nitride-based discrete solutions"), and such driving solutions do not meet the reliability requirements of automotive original equipment manufacturers ("OEMs"), and their sizes are too large to be used in limited installation spaces. In addition, first-tier suppliers ("Tier1") believe that gallium nitride-based discrete solutions are too costly. For example, driving a semiconductor laser may require more than 10 discrete drivers to correspondingly drive more than 10 discrete gallium nitride field-effect transistors. Summary of the Invention

[0005] This application provides a charging unit for driving an integrated semiconductor laser. The charging unit includes a first input terminal, a second input terminal, a third input terminal, and a second plurality of output terminals. The first input terminal is configured to receive input driving energy. The second input terminal is configured to enable or disable the charging unit. The third input terminal is configured to receive a charging control PWM signal. Wherein the charging unit is configured to turn on or off the second plurality of output terminals in a predetermined pattern according to the charging control PWM signal PWM_C. Brief Description of the Drawings

[0006] Figure 1 Shows a schematic diagram of a driving system 100 according to an embodiment of the present disclosure.

[0007] Figure 2 Shows for implementing according to the present disclosure Figure 1 A schematic diagram of the charging unit 200 of the charging unit 102 of the driving system 100 in

[0008] Figure 3A Illustrates an illustrative waveform diagram 300 according to an exemplary embodiment of the present disclosure, which depicts Figure 1 the operating waveforms of several signals in the drive system 100.

[0009] Figure 3B Illustrates an illustrative waveform diagram 300B according to another exemplary embodiment of the present disclosure, which depicts Figure 1 the operating waveforms of several signals in the drive system 100.

[0010] Figure 4 Illustrates a schematic diagram of a charging unit 400 according to the present disclosure for implementing the Figure 1 charging unit 102 in the drive system 100.

[0011] Figure 5A Illustrates an illustrative waveform diagram 500 according to an exemplary embodiment of the present disclosure, which depicts Figure 1 the operating waveforms of several signals in the drive system 100, wherein the charging unit 102 employs the charging unit 400 as shown in Figure 4 .

[0012] Figure 5B Illustrates an illustrative waveform diagram 500B according to an exemplary embodiment of the present disclosure, which depicts Figure 1 the operating waveforms of several signals in the drive system 100, wherein the charging unit 102 employs the charging unit 400 as shown in Figure 4 .

[0013] Figure 6 Illustrates an illustrative waveform diagram 600 according to an exemplary embodiment of the present disclosure, which depicts Figure 1 the operating waveforms of several signals in the drive system 100, wherein the charging unit 102 employs the charging unit 400 as shown in Figure 4 .

[0014] Figure 7 Illustrates a schematic diagram of a discharge unit 700 according to an exemplary embodiment of the present disclosure, which can be used to implement the Figure 1 discharge unit 106 in.

[0015] Figure 8 Illustrates a package 800 encapsulating a charging unit 102, which is integrated within an integrated circuit die or chip.

[0016] Fig. 9 Illustrates a package 900 encapsulating a discharge unit 106, which is integrated within an integrated circuit die or chip.

[0017] Fig.10 Shows a package 950 encapsulating a discharge unit 700 according to an embodiment of the present disclosure, the discharge unit 700 being integrated within an integrated circuit die or chip.

[0018] Fig.11 Shows a schematic diagram of a drive system 150 according to an embodiment of the present disclosure.

[0019] Fig.12 Shows a schematic diagram of a charging unit 250 according to an embodiment of the present disclosure, the charging unit 250 being Fig.11 an alternative implementation of the charging unit 102 in

[0020] Fig.13 Shows an illustrative waveform diagram 350 according to an exemplary embodiment of the present disclosure, the diagram showing Fig.11 the operating waveforms of several signals of the drive system 150 in

[0021] Fig.14 Shows a schematic diagram of a charging unit 450 according to an embodiment of the present disclosure.

[0022] Fig.15 Shows an illustrative waveform diagram 550 according to an exemplary embodiment of the present disclosure, the diagram showing Fig.11 the operating waveforms of several signals of the drive system 150 in

[0023] Fig.16 Shows an illustrative waveform diagram 650 according to an exemplary embodiment of the present disclosure, the diagram showing Fig.11 the operating waveforms of several signals of the drive system 150 in

[0024] Fig.17 Shows a package 850 of an integrated circuit die or wafer encapsulating a charging unit 102 according to an embodiment of the present disclosure, the package providing another alternative implementation.

[0025] Fig.18 Shows an application board-level layout diagram according to an embodiment of the present disclosure related to the drive system 100 in Figure 1 or related to the drive system 150 in Fig.11

[0026] 18A to 18F Shows an embodiment related to an application board-level layout diagram according to an embodiment of the present disclosure related to the drive system 100 in Figure 1 or related to the drive system 150 in Fig.11 each layer of the application board-level layout diagram. ​

[0027] Figure 18G Shows a top - plan view of the top surface of the first board - level 180(1) according to another embodiment of the present disclosure.

[0028] Fig.18H Shows a bottom - plan view of the multilayer circuit board 1800 according to another embodiment of the present disclosure.

[0029] Fig.19 Shows a schematic diagram of the drive system 1000 according to an embodiment of the present disclosure.

[0030] Fig. 20 Shows a schematic diagram of the drive system 1500 according to an embodiment of the present disclosure.

[0031] Fig.21A Shows according to an embodiment of the present disclosure and Fig.19 in the drive system 1000 or with Fig. 20 in the drive system 1500 - related application board - level layout diagram.

[0032] FIG. 21B to FIG. 21G Shows according to an embodiment of the present disclosure and Fig.19 in the drive system 1000 or with Fig. 20 in the drive system 1500 - related multi - layer application board - level layout diagram.

[0033] Fig. 22 Shows a schematic diagram of the drive system 2000 according to an embodiment of the present disclosure.

[0034] Fig.23 Shows an illustrative waveform diagram 2300 according to an exemplary embodiment of the present disclosure, which shows Fig.11 the working waveforms of several signals when the drive system 150 in Detailed Description of the Invention

[0035] In the following description, some specific details are included for a comprehensive understanding of the embodiments, such as schematic diagrams of circuits and circuit components. However, those of ordinary skill in the art should understand that the present disclosure can be implemented without one or more of the specific details, or using other methods, components, materials, etc. In other cases, well - known structures, materials, processes, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0036] Throughout the specification and claims, if terms such as "left", "right", "inner", "outer", "front", "rear", "upper", "lower", "top", "above", "bottom", "cover", "under", "over", "below" are used, these terms are for descriptive purposes only and do not necessarily describe permanent relative positions. It is to be understood that these terms are interchangeable where appropriate so that embodiments of the technology described herein can operate in other orientations different from those shown or described herein. As used in this disclosure, "connected" or "coupled" is defined as connecting directly or indirectly in an electrical or non-electrical manner. When an element is described as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be one or more intervening elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements. Throughout the specification, references to "an embodiment", "embodiments", "an example" or "examples" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present disclosure. Thus, the phrases "in an embodiment", "in embodiments", "an example" or "examples" appearing throughout the specification do not necessarily all refer to the same embodiment or example, although they may. Additionally, these features, structures, or characteristics may be combined in one or more embodiments or examples. The term "or" as used herein is equivalent to the term "and / or" unless the context clearly dictates otherwise. Where a field effect transistor ("FET") or a bipolar junction transistor ("BJT") can be used as a transistor in an embodiment, the terms "gate", "drain", and "source" respectively include "base", "collector", and "emitter", and vice versa. The term "based on" is not exclusive and allows for other factors not described unless the context clearly dictates otherwise. The term "circuit" means at least one single component or multiple components, whether active and / or passive, that are connected together to provide the desired functionality. The term "signal" means at least one current, voltage, charge, temperature, data, or other signal. Those of ordinary skill in the art should understand that the meanings of the above terms do not necessarily limit these terms, but merely provide illustrative examples for these terms.

[0037] The terms "comprising", "including", "having" and any variations thereof are intended to cover non-exclusive inclusion, i.e., when a process, method or apparatus includes a series of elements listed explicitly, it is not necessarily limited to only those explicitly listed elements, but may include other elements not explicitly listed or elements inherent to the process, method or apparatus.

[0038] Figure 1Shows a schematic diagram of a drive system 100 according to an embodiment of the present application. The drive system 100 is adapted to be configured to drive an integrated semiconductor laser 101, such as an integrated vertical cavity surface emitting laser (“VCSEL”) unit. The integrated semiconductor laser (e.g., semiconductor laser) 101 may include a series (e.g., represented by an integer variable N) of laser units (e.g., VCSEL units) 101(1), 101(2), …, 101(N) arranged in an array or matrix form. Hereinafter, this series of (e.g., N) laser units (e.g., VCSEL units) 101(1), 101(2), …, 101(N) may be referred to or represented as {101(i), i = 1, 2, …, N}. Wherein, N is an integer variable not less than 1, representing the total number of laser units {101(i), i = 1, 2, …, N} included in the integrated semiconductor laser 101, and this total number can be set or determined by the customer / user in actual applications according to actual application requirements. That is to say, the variable i traverses the integers from 1 to N. Each of the first plurality (e.g., N) of laser units {101(i), i = 1, 2, ..., N} may have a first terminal (e.g., anode) and a second terminal (e.g., cathode). In one example, the integrated semiconductor laser 101 may include 28 laser units {101(i), i = 1, 2, …, 28}, and in this example N = 28. Those of ordinary skill in the art should understand that this is only for providing an example and is not restrictive. The total number of laser units {101(i), i = 1, 2, …, N} included in the integrated semiconductor laser 101 is not limited to 28 and can be any other number according to actual application requirements. In this disclosure, the integer variable N is used to describe or represent the total number of laser units {101(i), i = 1, 2, …, N} included in the integrated semiconductor laser 101 for ease of reference and understanding.

[0039] The drive system 100 may include a drive energy input terminal IN for receiving input drive energy. In one example, the input drive energy is represented in the form of a supply voltage VIN. However, this is only for providing an example and is not intended to be limiting. Those of ordinary skill in the art should understand that the input drive energy may be other forms suitable for being used or processed by the drive system 100, such as supply current or supply power, etc. As Figure 1 shown, in one example, the input drive energy represented in the form of a supply voltage VIN may be provided by upstream power circuits, and these upstream power circuits may obtain energy from a power source PS such as an automotive battery pack. As Figure 1As shown, in one example, the upstream power supply circuit may include a front-end voltage regulator 10 and a buck voltage regulator 20. As an example, the front-end voltage regulator 10 and the buck voltage regulator 20 may include the MPQ5850 and MPQ4323 of Monolithic Power Systems, Inc., respectively. However, those of ordinary skill in the art should understand that this is only for providing an example and is not intended to be limiting. The upstream power supply circuit may be implemented using other power devices or may include other circuit elements.

[0040] According to an exemplary embodiment, the drive system 100 may further include a charging unit 102. The charging unit 102 has a first input terminal, for example, a power terminal IN1 connected to the drive energy input terminal IN. The charging unit 102 may include a series (e.g., represented by an integer variable M) of output terminals OUT(1), OUT(2), …, OUT(M). Hereinafter, the series (e.g., M) of output terminals OUT(1), OUT(2), …, OUT(M) may be referred to or represented as {OUT(j), j = 1, 2, …, M}. Wherein, M is an integer variable representing the total number of output terminals {OUT(j), j = 1, 2, …, M} included in the charging unit 102. That is, the variable j traverses integers from 1 to M. According to an exemplary embodiment, M is not less than N, i.e., M ≥ N. For example, the charging unit 102 may include 32 output terminals {OUT(j), j = 1, 2, …, 32}, in which case M = 32. Those of ordinary skill in the art should understand that this is only for providing an example and is not intended to be limiting. The total number of output terminals {OUT(j), j = 1, 2, …, M} included in the charging unit 102 is not limited to 32 and may be set to any other number according to actual application requirements. In this disclosure, the integer variable M is used to describe or represent the total number of output terminals {OUT(j), j = 1, 2, …, M} of the charging unit 102 for ease of reference and understanding.

[0041] According to an exemplary embodiment, the charging unit 102 may further include a second input terminal, for example, an enable terminal EN configured to receive an enable signal EN_C. The charging unit 102 may be configured to be enabled or disabled in response to the enable signal EN_C received by the enable terminal EN. In one example, when the charging unit 102 is enabled, it means that the charging unit 102 (including all sub - circuits or sub - elements of the charging unit 102) is operable, that is, capable of processing signals or completing a predetermined function. When the charging unit 102 is disabled, it may mean that the charging unit 102 is inoperable or turned off. In one example, the charging unit 102 may be configured to be enabled when the enable signal EN_C received by the enable terminal EN is in a first logic state (e.g., logic high) or when the enable signal EN_C reaches or is higher than an enable threshold, and may be further configured to be disabled when the enable signal EN_C is in a second logic state (e.g., logic low) or when the enable signal EN_C is lower than the enable threshold.

[0042] According to an exemplary embodiment, the charging unit 102 may further include a third input terminal, for example, a pulse - width modulation ("PWM") terminal PWM1 configured to receive a charging control PWM signal PWM_C. The charging unit 102 may further be configured to switch the M output terminals {OUT(j), j = 1, 2, …, M} between on and off states according to the charging control PWM signal PWM_C in a predetermined pattern (which may be a customer - or user - programmable predetermined pattern). In an exemplary embodiment, for each of the M output terminals {OUT(j), j = 1, 2, …, M}, for example, the j - th output terminal OUT(j), it may be configured to provide energy in the form of voltage or current when switched to the on state, and configured to stop providing energy when switched to the off state. In an exemplary embodiment, for each of the M output terminals {OUT(j), j = 1, 2, …, M}, for example, the j - th output terminal OUT(j), when it is switched to the on state, the duration or time window of the on state may be referred to as the j - th charging time window T cg (j) for the sake of description and understanding hereinafter.

[0043] According to an exemplary embodiment, the M output terminals {OUT(j), j = 1, 2, …, M} may be sequentially switched to the on state (i.e., turned on in the order from OUT(1) to OUT(M)) according to a plurality of successive charging pulses of the charging control PWM signal PWM_C. For example, for each j from 1 to M, the j - th output terminal OUT(j) is in the j - th charging time window T according to the j - th charging pulse of the charging control PWM signal PWM_C cg(j) is switched to the on state during this period. However, those skilled in the art should understand that this is only for providing an example and is not intended to be limiting. In other exemplary embodiments, the predetermined pattern for switching the on / off state of the M output terminals {OUT(j), j = 1, 2, …, M} can be flexibly controlled or programmed, for example, by a customer or user, and does not necessarily need to be switched to the on state sequentially according to the multiple successive charging pulses of the charging control PWM signal PWM_C (i.e., turned on in the order from OUT(1) to OUT(M)). In other words, for each j from 1 to M, the jth charging time window T cg for the jth output terminal OUT(j) to be switched to the on state does not necessarily correspond to the jth charging pulse of the charging control PWM signal PWM_C.

[0044] In addition, those skilled in the art should understand that the first charging pulse of the charging control PWM signal PWM_C may not be the actual initial pulse or the first pulse of PWM_C. Instead, the first charging pulse may refer to a pulse that appears or is generated after a predetermined time T ready after the power-on of the drive system 100 or the charging unit 102. During the predetermined time T ready the drive system 100 or the charging unit 102 prepares for normal and stable operation. In an exemplary embodiment, the first charging pulse, the second charging pulse, …, the jth charging pulse, etc. of the charging control PWM signal PWM_C refer to a series of consecutive pulses of the charging control PWM signal PWM_C. Those skilled in the art should understand that this is only for providing an example and is not intended to be limiting. In other exemplary embodiments, the first charging pulse, the second charging pulse, …, the jth charging pulse, etc. of the charging control PWM signal PWM_C refer to every two or three adjacent and consecutively generated pulses in the charging control PWM signal PWM_C.

[0045] According to an exemplary embodiment, the charging unit 102 may further include a reference ground terminal GND1. The charging unit 102 and all sub-circuits or sub-elements of the charging unit 102 may be configured to use the reference ground potential at the reference ground terminal GND1 as the ground potential of the charging unit 102. In an example, the reference ground terminal GND1 of the charging unit 102 may be coupled to the reference ground terminal GND of the drive system 100.

[0046] According to an exemplary embodiment, the charging unit 102 may be coupled to the integrated semiconductor laser 101 and supply energy to the N laser units {101(i), i = 1, 2, …, N} through the M output terminals {OUT(j), j = 1, 2, …, M} in a predetermined pattern determined by the charging control PWM signal PWM_C. For example, in an exemplary embodiment, a first set (e.g., N) of output terminals corresponding to the N laser units {101(i), i = 1, 2, …, N} may be selected from the M output terminals {OUT(j), j = 1, 2, …, M}, and the first set (e.g., N) of output terminals may be coupled to the N laser units {101(i), i = 1, 2, …, N} in a one-to-one correspondence. In other words, the corresponding first set (e.g., N) of output terminals selected from the M output terminals {OUT(j), j = 1, 2, …, M} is at least matched in number with the N laser units {101(i), i = 1, 2, …, N}. Hereinafter, the first set (e.g., N) of output terminals selected from the M output terminals {OUT(j), j = 1, 2, …, M} and coupled to the N laser units {101(i), i = 1, 2, …, N} is referred to as the first set (e.g., N) of selected output terminals and denoted as {OUT(i), j = 1, 2, …, N} for reference, description, and understanding in the remaining description of this disclosure.

[0047] Here is an example, such as Figure 1 As shown, the first consecutive N output terminals {OUT(j), j = 1, 2, …, N} selected from the M output terminals {OUT(j), j = 1, 2, …, M} are configured to be respectively coupled to the N laser units {101(i), i = 1, 2, …, N}. However, this is only for providing an example and is not intended to be limiting.

[0048] Those of ordinary skill in the art should understand that since the total number M of output terminals of the charging unit 102 is not less than the total number N of laser units, any N output terminals can be randomly selected from the M output terminals {OUT(j), j = 1, 2, …, M} of the charging unit 102 to drive the N laser units {101(i), i = 1, 2, …, N}. That is to say, each output terminal in the first group of selected output terminals selected from the M output terminals {OUT(j), j = 1, 2, …, M} of the charging unit 102 can be coupled to a corresponding laser unit among the N laser units {101(i), i = 1, 2, …, N}. Hereinafter, among the first group of selected output terminals selected from, for example, the M output terminals {OUT(j), j = 1, 2, …, M} of the charging unit 102, the output terminal coupled to the i-th laser unit 101(i) among the N laser units {101(i), i = 1, 2, …, N} can be referred to as the selected i-th output terminal and labeled or renumbered as OUT(i) for the convenience of reference, description, and understanding in the remaining description of this disclosure. The selected i-th output terminal OUT(i) can be connected to the first terminal of the corresponding first i-th laser unit 101(i). Those of ordinary skill in the art should understand that in an exemplary embodiment, the first consecutive N output terminals {OUT(j), j = 1, 2, …, N} selected from the M output terminals {OUT(j), j = 1, 2, …, M} are respectively coupled to the N laser units {101(i), i = 1, 2, …, N}. In this example, the first plurality of consecutively numbered output terminals {OUT(j), j = 1, 2, …, N} selected from the second plurality of output terminals {OUT(i), i = 1, 2, …, M} and the first plurality of selected output terminals {OUT(i), i = 1, 2, …, N} have the same meaning. For each i traversing from 1 to N, i = j, that is, the j-th output terminal OUT(j), the i-th output terminal OUT(i), and the selected i-th output terminal OUT(i) refer to the same output terminal. However, it is also obvious to those of ordinary skill in the art that the first plurality (for example, N) of selected output terminals {OUT(i), i = 1, 2,..., N} are not necessarily always equal to the first plurality of consecutively numbered N output terminals {OUT(j), j = 1, 2,..., N} among the second plurality (for example, M) of output terminals {OUT(j), j = 1, 2,..., N}, but the first plurality (for example, N) of selected output terminals {OUT(i), i = 1, 2,... N} are renumbered according to the corresponding first plurality of laser units {101(i), i = 1, 2,... N}.

[0049] According to an exemplary embodiment, the first set of selected output terminals {OUT(i), i = 1, 2, …, N} may be sequentially switched to the on state according to a plurality of consecutive charging pulses of the charging control PWM signal PWM_C (i.e., turned on in the order from OUT(1) to OUT(M)). For example, for each i traversing from 1 to N, the selected i-th output terminal coupled to the i-th laser unit 101(i) among the N laser units {101(i), i = 1, 2, …, N} may be referred to herein as the i-th charging time window T cg (i) and is switched to the on state during this period. In an exemplary embodiment, for each i traversing from 1 to N, the i-th charging time window T cg (i) may occur after the i-th charging pulse of the charging control PWM signal PWM_C. For example, in one embodiment, for each i traversing from 1 to N, the i-th charging time window T cg (i) may occur between the i-th charging pulse and the (i + 1)-th charging pulse of the charging control PWM signal PWM_C. That is to say, in this example, for each i traversing from 1 to N, the switching mode or order of turning on / off of the selected i-th output terminal is determined by the i-th charging pulse of the charging control PWM signal PWM_C. However, those of ordinary skill in the art should understand that this is only for providing an example and is not intended to be limiting. In other exemplary embodiments, for each i traversing from 1 to N, the switching mode or order of turning on / off of the selected i-th output terminal, that is, the occurrence position of the i-th charging time window T cg (i), can be flexibly controlled or programmed and is not necessarily the i-th charging pulse of the charging control PWM signal PWM_C. Those of ordinary skill in the art should understand that in the exemplary embodiment, the first consecutive N output terminals {OUT(j), j = 1, 2, …, N} selected from the M output terminals {OUT(j), j = 1, 2, …, M} are respectively coupled to the N laser units {101(i), i = 1, 2, …, N}. In this example, for each i traversing from 1 to N, i = j, and the j-th charging time window T cg (j) related to the j-th output terminal OUT(j) and the i-th charging time window T cg (i) related to the selected i-th output terminal refer to the same charging time window.

[0050] According to an exemplary embodiment, the charging unit 102 may further include at least one controllable power switch 103, which may be configured to perform on / off switching when the charging unit 102 is enabled. In an exemplary embodiment, when the charging unit 102 is enabled, the at least one controllable power switch 103 may be configured to perform on / off switching in response to a charging control PWM signal PWM_C received at a third input terminal (e.g., PWM terminal PWM1) of the charging unit 102. For example, during each period T of the charging control PWM signal PWM_C PWMC the at least one controllable power switch 103 is switched to the on state in response to the first transition edge (e.g., rising edge) of the charging control PWM signal PWM_C, at which time the charging control PWM signal PWM_C changes from a first voltage level or logic level (e.g., logic low) to a second voltage level or logic level (e.g., logic high), and is switched to the off state in response to the second transition edge (e.g., falling edge) of the charging control PWM signal PWM_C, at which time the charging control PWM signal PWM_C changes from the second voltage level or logic level (e.g., logic high) to the first voltage level or logic level (e.g., logic low). However, this is only provided as an example and is not intended to be limiting. In other embodiments, the at least one controllable power switch 103 may not perform on / off switching during each operating cycle or period T of the charging control PWM signal PWM_C PWMC For example, the at least one controllable power switch 103 may be turned on in response to the first transition edge (e.g., rising edge) of each charging pulse of the charging control PWM signal PWM_C, at which edge the charging control PWM signal PWM_C changes from a first voltage level or logic level (e.g., logic low) to a second voltage level or logic level (e.g., logic high), and may be turned on in response to the second transition edge (e.g., rising edge) of each charging pulse of the charging control PWM signal PWM_C. When the charging control PWM signal PWM_C changes from the second voltage level or logic level (e.g., logic high) to the first voltage level or logic level (e.g., logic low), the second transition edge (e.g., falling edge) of each charging pulse of the charging control PWM signal PWM_C may be turned off.

[0051] Ideally, the at least one controllable power switch 103 allows current to flow when turned on and cuts off current flow when turned off. For example, the at least one controllable power switch 103 may include a field effect transistor ("FET"), such as a metal oxide semiconductor field effect transistor ("MOSFET"), a double-diffused metal oxide semiconductor field effect transistor ("DMOS"), a gallium nitride field effect transistor ("GaN FET"), a silicon carbide field effect transistor ("SiC FET"), or a junction field effect transistor ("JFET"), etc. Those of ordinary skill in the art should understand that the at least one controllable power switch 103 can be implemented using other controllable switching devices, such as a bipolar junction transistor ("BJT") or an insulated gate bipolar transistor ("IGBT"), etc. Alternatively, in other examples, the at least one controllable power switch 103 may include a combination of one or more of the above transistors. The at least one controllable power switch 103 can be used to control or regulate the amount of energy transferred from the drive energy input terminal IN to the charging unit 102. For example, in one embodiment, the at least one controllable power switch 103 can be used to control or regulate the amount of energy transferred from the drive energy input terminal IN to the power output terminal BSTO of the charging unit 102. Thus, the charging unit 102 can be configured to convert the supply voltage VIN into a regulated output voltage Vo provided at the power output terminal BSTO.

[0052] According to an exemplary embodiment, the charging unit 102 may further include a switch terminal SW, which can be configured to provide, for example, a switching signal. When the inductive energy storage element L is coupled to the switch terminal SW of the charging unit 102, the charging unit 102 can be configured to operate as part of a power conversion device. For example, as Figure 1 shown, the at least one controllable power switch 103 may be coupled between the switch terminal SW and the power output terminal BSTO. The inductive energy storage element L may be coupled between the first input terminal (e.g., the power terminal IN1) of the charging unit 102 and the switch terminal SW. The power conversion device may further include a second power switch 105, as Figure 1In the example shown, it can be coupled between the switch terminal SW and the power output terminal BSTO. In one example, the second power switch 105 can be a diode. In another example, the second power switch 105 can include a controllable transistor, such as a MOSFET, DMOS, GaN FET, SiC FET, BJT, or IGBT, etc. The second power switch 105 can be a discrete device disposed outside the charging unit 102 or an integrated device disposed inside the charging unit 102. In an exemplary embodiment, the second power switch 105 can be configured to perform on / off switching in a complementary manner with at least one controllable power switch 103. That is, when the at least one controllable power switch 103 is switched to the on state, the second power switch 105 is in the off state, and when the at least one controllable power switch 103 is switched to the off state, the second power switch 105 is in the on state. In Figure 1 In the example shown, the charging unit 102 is exemplarily configured to operate as part of a power conversion device having a boost converter topology. Those of ordinary skill in the art should understand that this is only provided as an example and is not intended to be limiting. In other embodiments, the charging unit 102 can be configured to operate as part of a power conversion device having other topologies, and the other topologies can be a buck converter topology, a buck-boost converter topology, a flyback converter topology, etc.

[0053] According to an exemplary embodiment, the charging unit 102 may further include M charging path control circuits 104(1), 104(2), …, 104(M) corresponding to the M output terminals {OUT(j), j = 1, 2, …, M}. Hereinafter, the M charging path control circuits 104(1), 104(2), …, 104(M) may be referred to or represented as {104(j), j = 1, 2, …, M}. In other words, the M charging path control circuits {104(j), j = 1, 2, …, M} are at least equal in number to the M output terminals {OUT(j), j = 1, 2, …, M}. In one embodiment, the M charging path control circuits {104(j), j = 1, 2, …, M} may be coupled to the M output terminals {OUT(j), j = 1, 2, …, M} in a one-to-one correspondence. That is to say, each of the M charging path control circuits in the M charging path control circuits {104(j), j = 1, 2, …, M} may be coupled to a corresponding one of the M output terminals {OUT(j), j = 1, 2, …, M}. Or, in other words, for each j ranging from 1 to M, any one of the M charging path control circuits in the M charging path control circuits {104(j), j = 1, 2, …, M}, for example, the j-th charging path control circuit 104(j), may be coupled to a corresponding one of the output terminals, for example, the j-th output terminal OUT(j) among the M output terminals {OUT(j), j = 1, 2, …, M}. Here, the integer variable M is also used to describe or represent the total number of the charging path control circuits {104(j), j = 1, 2, …, M} included in the charging unit 102. In other words, the total number of the charging path control circuits {104(j), j = 1, 2, …, M} included in the charging unit 102 should match or be the same as the total number of the output terminals {OUT(j), j = 1, 2, …, M} included in the charging unit 102. In an example where the charging unit 102 has 32 output terminals {OUT(j), j = 1, 2, …, 32}, the charging unit 102 may include 32 charging path control circuits {104(j), j = 1, 2, …, 32}, which correspond to the 32 output terminals {OUT(j), j = 1, 2, …, 32} and are respectively coupled to the 32 output terminals {OUT(j), j = 1, 2, …, 32}.

[0054] According to an exemplary embodiment, for each j traversing from 1 to M, each of the M charging path control circuits {104(j), j = 1, 2, …, M}, i.e., the j-th charging path control circuit 104(j), can be switched to an on or off state in response to the charging control PWM signal PWM_C received by the third input terminal (e.g., PWM terminal PWM1) of the charging unit 102. For each j traversing from 1 to M, each of the M charging path control circuits {104(j), j = 1, 2, …, M} (i.e., the j-th charging path control circuit 104(j)) can be configured to, when switched to the on state, enable the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding one of the M output terminals {OUT(j), j = 1, 2, …, M} (i.e., the j-th output terminal OUT(j)), and can be further configured to, when switched to the off state, disable or cut off the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding one of the output terminals, e.g., the j-th output terminal OUT(j). That is to say, for each j traversing from 1 to M, the j-th charging path control circuit 104(j) can be configured to enable the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j) when switched to the on state, and can be further configured to disable or cut off the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j) when switched to the off state. Those of ordinary skill in the art should understand that for each j traversing from 1 to M, when the j-th charging path control circuit 104(j) enables the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j), the enabled energy transfer / conduction path is ready or suitable for transferring energy from the output terminal BSTO to the corresponding j-th output terminal OUT(j). In other words, for each j traversing from 1 to M, once the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j) is enabled, it does not mean that this enabled energy transfer / conduction path will immediately start energy transfer, although this may be possible. Enabling means that this enabled energy transfer / conduction path is in a state of being ready or suitable for transferring energy (e.g., is conductive).For example, in one embodiment, for each j traversing from 1 to M, when the j-th charge path control circuit 104(j) is switched to the ON state and enables the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j), the charging unit 102 may wait for other conditions to be satisfied before starting to transfer / conduct energy from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j) through the enabled energy transfer / conduction path. The energy transfer / conduction can be in the form of voltage, current, charge, etc. Conversely, for each j traversing from 1 to M, when the j-th charge path control circuit 104(j) is switched to the OFF state to disable or cut off the energy transfer / conduction path from the power supply output terminal BSTO to the corresponding j-th output terminal OUT(j), the disabled energy transfer / conduction path may no longer be applicable for transferring energy from the output terminal BSTO to the corresponding j-th output terminal OUT(j), which means the disabled energy transfer / conduction path is in a state that blocks energy transfer (e.g., non-conductive or disconnecting the connection between the power supply output terminal BSTO and the corresponding j-th output terminal OUT(j)).

[0055] According to an exemplary embodiment, for each j traversing from 1 to M, each of the M charge path control circuits {104(j), j = 1, 2, …, M}, i.e., the j-th charge path control circuit 104(j), may have a first terminal n1, a second terminal n2, and a control terminal n3. In an exemplary embodiment, the multiple first terminals n1 of the charge path control circuits {104(j), j = 1, 2, …, M} may be coupled together to the power supply output terminal BSTO. The second terminal n2 of each of the M charge path control circuits {104(j), j = 1, 2, …, M} (i.e., the second terminal n2 of the j-th charge path control circuit 104(j)) may be correspondingly coupled to the j-th output terminal OUT(j) among the M output terminals {OUT(j), j = 1, 2, …, M}. The respective control terminals n3 of the charge path control circuits {104(j), j = 1, 2, …, M} may be controlled according to the pulses of the charging control PWM signal PWM_C, so as to perform ON / OFF switching on the charge path control circuits {104(j), j = 1, 2, …, M} in a predetermined pattern or sequence, and this pattern or sequence can be programmable by the customer or user.

[0056] According to an exemplary embodiment, for each i traversing from 1 to N, the charging unit 102 may be configured to switch the charging path control circuit coupled to the i-th output terminal to the on state during a selected i-th conduction time window Ton(i), where the i-th output terminal is one of the first selected N output terminals selected from M output terminals {OUT(j), j = 1, 2, …, M}, and the i-th conduction time window Ton(i) is associated with the charging path control circuit of the i-th output terminal OUT(i). The charging unit 102 may be configured to switch the charging path control circuit coupled to the i-th output terminal to the off state during a period outside the selected i-th conduction time window Ton(i). The charging unit 102 may also be configured to control the selected i-th conduction time window Ton(i) associated with the charging path control circuit coupled to the i-th output terminal OUT(i) according to the pulse of the charging control PWM signal PWM_C, for example, based on the charging pulse of the charging control PWM signal PWM_C.

[0057] According to an exemplary embodiment, for each i traversing from 1 to N, the charging unit 102 may be configured to switch the charging path control circuit coupled to the i-th output terminal to the on state at a certain moment within the time period when the controllable power switch 103 remains on. In one example, it may be switched to the on state in response to the i-th charging pulse of the PWM signal PWM_C. That is to say, the moment when the charging path control circuit coupled to the selected i-th output terminal OUT(i) is switched to the on state is not earlier than the moment when the controllable power switch 103 is switched to the on state in response to the i-th charging pulse of the charging control PWM signal PWM_C, and is not later than the moment when the controllable power switch 103 is switched to the off state in response to the i-th charging pulse of the charging control PWM signal PWM_C. Those of ordinary skill in the art should understand that the moment when the controllable power switch 103 is switched to the off state in response to the i-th charging pulse of the charging control PWM signal PWM_C is also the moment when the i-th charging time window T cg (i) starts, so that the i-th output terminal OUT(i) is switched to the on state to start charging the corresponding capacitive energy storage device CR(i) coupled to the i-th output terminal OUT(i).

[0058] For each i traversing from 1 to N, the charging unit 102 can be further configured to switch the charging path control circuit coupled to the i-th output terminal OUT(i) to the off state no later than the moment when the controllable power switch 103 is switched to the off state in response to the (i + 1)-th charging pulse of the charging control PWM signal PWM_C. The moment when the controllable power switch 103 is switched to the off state in response to the (i + 1)-th charging pulse of the charging control PWM signal PWM_C is also the moment when the s-th charging time window T cg (s) starts, where the s-th output terminal OUT(s) is the next selected output terminal after the i-th output terminal OUT(i), and s represents the number or serial number of the selected output terminal OUT(s). The output terminal OUT(s) will be switched to the on state after the i-th output terminal OUT(i). Here, s can be selected from 1 to N. In one example, the next selected output terminal OUT(s) switched to the on state after the i-th output terminal OUT(i) can be the (i + 1)-th output terminal OUT(i + 1). For this embodiment, the first group (e.g., N) of output terminals {OUT(i), i = 1, 2,..., N} will be continuously and sequentially switched to the on state, that is, switched to the on state in the order from OUT(1) to OUT(N). In another example, the next output terminal OUT(s) to be switched to the on state after the i-th output terminal OUT(i) does not necessarily have to be the (i + 1)-th output terminal OUT(i + 1). For this embodiment, the first group (e.g., N) of output terminals {OUT(i), i = 1, 2,..., N} will not be continuously and sequentially switched to the on state.

[0059] In other words, the charging unit 102 can be configured to control the i-th on-time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) such that it starts at a certain moment within the time period when the controllable power switch 103 remains in the on state. In one example, the controllable power switch 103 can be switched to the on state in response to the i-th charging pulse of the PWM signal PWM_C. And the charging unit 102 can also be configured to control the i-th on-time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) such that it terminates no later than the moment when the controllable power switch 103 is switched to the off state in response to the (i + 1)-th charging pulse. In this way, the charging unit 102 can be configured to flexibly adjust the i-th on-time window Ton(i) to ensure that the charging path control circuit coupled to the i-th output terminal OUT(i) is within the i-th charging time window T cg(i) is switched to ON before starting to enable the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i); and ensure that the charging path control circuit coupled to the i-th output terminal OUT(i) is within the charging time window T associated with the next selected output terminal OUT(s) (the output terminal OUT(s) will be switched to ON after the i-th output terminal OUT(i)). cg (s) is switched to OFF before starting to disable the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i).

[0060] According to an exemplary embodiment, for each i traversing from 1 to N, the charging unit 102 may be configured to, during the i-th charging time window T cg (i) between the i-th charging pulse and the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, turn on the charging path control circuit coupled to the i-th output terminal, where the i-th output terminal is one of the first group (e.g., N) of selected output terminals selected from the M output terminals {OUT(j), j = 1, 2,..., M}. Those of ordinary skill in the art should understand that this is only for providing an example and is not intended to be limiting. The charging unit 102 may be configured to keep the charging path control circuit coupled to the i-th output terminal ON in various other alternative ways, which cannot be elaborated here in detail, but as long as it does not deviate from the spirit and scope of the various embodiments of the present disclosure and can control the i-th conduction time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) as described above, it is acceptable.

[0061] As Figure 1 shown, according to an exemplary embodiment, for each of the M charging path control circuits {104(j), j = 1, 2,..., M}, that is, the j-th charging path control circuit 104(j), may include at least one switch. Figure 2 FIG. shows the charging unit 200, which is a schematic diagram for implementing an exemplary embodiment of the charging unit 102. As Figure 2 shown, at least one switch in each charging path control circuit, that is, at least one switch in the j-th charging path control circuit 104(j), may include a controllable transistor, such as a MOSFET or a DMOS or a GaNFET, or a SiC FET, or a BJT, or an IGBT, etc.

[0062] According to an exemplary embodiment of the present application, Figure 3A FIG. shows an illustrative waveform diagram 300A, which depicts Figure 1Operating waveforms of several signals of the middle drive system 100. Figure 3B An illustrative waveform diagram 300B is shown, which depicts another exemplary embodiment of the drive system 100 according to Figure 1 . As can be seen from Figure 3A and Figure 3B , in this example, for each i traversing from 1 to N, the selected i-th output terminal OUT(i) coupled to the corresponding i-th laser unit 101(i) among the N laser units {101(i), i = 1, 2,..., N} can be switched to the on state during the i-th charging time window T cg (i) between the i-th charging pulse and the (i + 1)-th charging pulse of the charging control PWM signal PWM_C.

[0063] In Figure 3A and Figure 3B In the illustrative waveform diagrams shown, the graph labeled 103_G can represent an illustrative waveform of a control signal (also simply referred to as 103_G for simplicity and ease of understanding) for controlling at least one controllable power switch 103. In some examples, at least one controllable power switch 103 includes a field effect transistor ("FET"), and this control signal 103_G can be applied or provided to the gate of at least one controllable power switch 103. Those of ordinary skill in the art should understand that for the examples shown in Figure 3A and Figure 3B , the logic high level in the waveform diagram of the control signal 103_G can represent that at least one controllable power switch 103 is switched to the on state, the inductor current iL flowing through the inductive energy storage element L may gradually increase, and energy is stored in the inductive energy storage element L, and the power output terminal BSTO is charged. The logic low level in the waveform diagram of the control signal 103_G represents that at least one controllable power switch 103 is switched to the off state, and the inductor current iL flowing through the inductive energy storage device L gradually decreases.

[0064] The control signal 103_G can be provided or generated based on the charging control PWM signal PWM_C. For example, in an exemplary embodiment such as Figure 3A , the control signal 103_G can be synchronized and in phase with the charging control PWM signal PWM_C. At least one controllable power switch 103 can be switched to the on state in response to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C, and switched to the off state in response to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C.

[0065] In other embodiments, for example, in an embodiment such as Figure 3BIn an exemplary embodiment, the control signal 103_G may be asynchronous with the charging control PWM signal PWM_C, i.e., out of phase. Because in physical implementation, the actual integrated circuit takes some time to respond. Therefore, in each period T of the charging control PWM signal PWM_C PWMC a first delay time T is introduced between each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and the corresponding first transition edge (e.g., rising edge) of the control signal 103_G d1 and a second delay time T is introduced between each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and the corresponding second transition edge (e.g., falling edge) of the control signal 103_G d2 For this case, it can be understood that at least one controllable power switch 103 responds to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and is switched to the on state after experiencing the first delay time T d1 and responds to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and is switched to the off state after experiencing the second delay time T d2 Those of ordinary skill in the art should understand that "after responding to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and experiencing the first delay time T d1 " means "after each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C, and responding when the first delay time T d1 ends". Similarly, "after responding to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and experiencing the second delay time T d2 " means "after each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C, and responding when the second delay time T d2 ends".

[0066] In another example, the control signal 103_G may not need to respond to each pulse, or in other words, to each first transition edge (e.g., each rising edge) and each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C. Instead, for any i ranging from 1 to N, the control signal 103_G may be configured to respond to the i-th charging pulse of the charging control PWM signal PWM_C. For example, for any i ranging from 1 to N, it may respond to the first transition edge (e.g., each rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experience the first delay time T d1subsequently generate a corresponding first transition edge (e.g., rising edge) of the control signal 103_G, and in response to a second transition edge (e.g., falling edge) of the i-th charging pulse of the charge control PWM signal PWM_C and after experiencing a second delay time T d2 subsequently generate a corresponding second transition edge (e.g., falling edge) of the control signal 103_G. This can also be referred to Figure 3B for understanding, Figure 3B Exemplarily shows a series of consecutive pulses of the charge control PWM signal PWM_C. In this case, it can be understood that at least one controllable power switch 103 can respond to a first transition edge (e.g., rising edge) of the i-th charging pulse of the charge control PWM signal PWM_C and after experiencing a first delay time T d1 and then be switched to the on state, and can respond to a second transition edge (e.g., falling edge) of the i-th charging pulse of the charge control PWM signal PWM_C and after experiencing a second delay time T d2 and then be switched to the off state. Those skilled in the art should understand that "in response to a first transition edge (e.g., rising edge) of the i-th charging pulse of the charge control PWM signal PWM_C and after experiencing a first delay time T d1 later" means "after the first transition edge (e.g., rising edge) of the i-th charging pulse of the charge control PWM signal PWM_C, and respond when the first delay time T d1 ends", and similarly "in response to a second transition edge (e.g., falling edge) of the i-th charging pulse of the charge control PWM signal PWM_C and after experiencing a second delay time T d2 later" means "after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charge control PWM signal PWM_C, and respond when the second delay time T d2 ends".

[0067] In Figure 3A and Figure 3B In the illustrative waveform diagrams shown, for each i traversing from 1 to N, the graph labeled 104(i)_G represents an illustrative waveform of a control signal (this control signal is also simply referred to as 104(i)_G for simplicity and ease of understanding) for controlling the i-th charge path control circuit 104(i) among the M charge path control circuits {104(j), j = 1, 2,..., M}. The control signal 104(i)_G can be provided to the control terminal n3 of the i-th charge path control circuit 104(i), where the i-th charge path control circuit 104(i) is coupled to the selected i-th output terminal OUT(i). Those skilled in the art should understand that in Figure 3A and Figure 3BIn the example shown, for each i ranging from 1 to N, the logical high level in the waveform of the control signal 104(i)_G may indicate that the i-th charge path control circuit 104(i) is switched to the on state to enable the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i); while the logical low level in the waveform of the control signal 104(i)_G indicates that the i-th charge path control circuit 104(i) is switched to the off state to disable the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i). The control signal 104(i)_G can be provided or generated based on the charge control PWM signal PWM_C.

[0068] For example, in an exemplary embodiment such as Figure 3A , for each i ranging from 1 to N, the control signal 104(i)_G may respond to the first transition edge (e.g., rising edge) of the i-th charge pulse of the charge control PWM signal PWM_C, and after a predetermined on-delay time T don1 , change from the first control voltage level or the first control logic level (e.g., logical low) to the second control voltage level or the second control logic level (e.g., logical high), that is, generate the first transition edge (e.g., rising edge) of the control signal 104(i)_G to switch the i-th charge path control circuit 104(i) to the on state, thereby enabling the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i). Similarly, the control signal 104(i)_G may respond to the second transition edge (e.g., falling edge) of the i-th charge pulse of the charge control PWM signal PWM_C, and after a predetermined off-delay time T doff1 , change from the second control voltage level or the second control logic level (e.g., logical high) to the first control voltage level or the first control logic level (e.g., logical low), that is, generate the second transition edge (e.g., falling edge) of the control signal 104(i)_G to switch the i-th charge path control circuit 104(i) to the off state, thereby disabling the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i). In this way, the i-th on-time window Ton(i) of the i-th charge path control circuit 104(i) can be adaptively adjusted and flexibly controlled according to the charge control PWM signal PWM_C. Those of ordinary skill in the art should understand that "responding to the first transition edge (e.g., rising edge) of the i-th charge pulse of the charge control PWM signal PWM_C, and after a predetermined on-delay time T don1"refers to "after the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C, when a predetermined turn-on delay time T don1 ends to make a response". Similarly, "in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-off delay time T doff1 "refers to "after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, when the predetermined turn-off delay time T doff1 ends to make a response".

[0069] Next, still referring to Figure 3A , in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-on delay time T don1 (i.e., after the first transition edge (e.g., rising edge) of the first charging pulse, when the predetermined turn-on delay time T don1 ends), the control signal 104(1)_G for controlling the first charge path control circuit 104(1) coupled to the first output terminal OUT(1) can transition from the first control logic level (e.g., logic low) to the second control logic level (e.g., logic high) to switch the first charge path control circuit 104(1) to the on state and enable the energy transfer path from the power output terminal BSTO to the selected first output terminal OUT(1), where the first output terminal OUT(1) is adapted to be coupled to the first laser unit 101(1). In response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-off delay time Tdoff1 (i.e., after the second transition edge (e.g., falling edge) of the first charging pulse, when the predetermined turn-off delay time Tdoff1 ends), the control signal 104(1)_G for controlling the first charge path control circuit 104(1) coupled to the first output terminal OUT(1) can transition from the second control logic level (e.g., logic high) to the first control logic level (e.g., logic low) to switch the first charge path control circuit 104(1) to the off state to disable the energy transfer path from the power output terminal BSTO to the selected first output terminal OUT(1). It is obvious to those of ordinary skill in the art that the above description of the control signal 104(1)_G equally applies to the control signals 104(2)_G,..., 104(N)_G, which will not be repeated here.

[0070] In another embodiment, as shown in the appendix Figure 3BAs shown, for any i traversing from 1 to N, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after a predetermined on-delay time T don2 , the control signal 104(i)_G can transition from a first control voltage level or a first control logic level (e.g., logic low) to a second control voltage level or a second control logic level (e.g., logic high). In other words, this response process generates a first transition edge (e.g., rising edge) of the control signal 104(i)_G to switch the i-th charge path control circuit 104(i) to the on state and enable the energy transfer path from the power output terminal BSTO to the selected i-th output terminal OUT(i). In response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the first transition edge of the (i + 1)-th charging pulse, and after a predetermined off-delay time T doff2 , the control signal 104(i)_G can change from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low). In other words, this response process generates a second transition edge (e.g., falling edge) of the control signal 104(i)_G to switch the i-th charge path control circuit 104(i) to the off state and disable the energy transfer path from the power output terminal BSTO to the selected i-th output terminal OUT(i). Those skilled in the art with ordinary knowledge should understand that "in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after a predetermined on-delay time T don2 " means "responding at the moment when the predetermined on-delay time T don2 ends after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C". "In response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the first transition edge of the (i + 1)-th charging pulse, and after a predetermined off-delay time T doff2 " means "responding at the moment when the predetermined off-delay time T doff2 ends after the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C or the first transition edge of the (i + 1)-th charging pulse".

[0071] Those skilled in the art with ordinary skills should understand that as Figure 3A and Figure 3BAs shown, in response to the charging pulse of the charging control PWM signal PWM_C, the control voltage level or control logic level of the control signal 104(i)_G is changed. In this way, the charging unit 102 is configured to provide the control signal 104(i)_G according to the charging control PWM signal PWM_C to control the implementation of the i-th charging path control circuit 104(i). This is only exemplary and not intended to be limiting. The charging unit 102 can be configured to change the control voltage level or control logic level of the control signal 104(i)_G in response to changes in the charging control PWM signal PWM_C in various other ways to provide the control signal 104(i)_G. These ways cannot be elaborated one by one here, as long as they do not deviate from the spirit and scope of this disclosure, they are acceptable. As long as the i-th on-time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) can be controlled to start at a moment within the period when the controllable power switch 103 remains on (e.g., in response to the i-th charging pulse of the charging control PWM signal PWM_C) and end no later than the moment when the controllable power switch 103 is switched to off in response to the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, such ways are in line with the spirit and scope of this application.

[0072] Figure 4 An exemplary schematic diagram of a charging unit 400 is shown, and this charging unit 400 is an exemplary embodiment for implementing Figure 1 the charging unit 102 in Figure 4 In the example of Figure 5A An illustrative waveform diagram 500A is shown, which depicts Figure 1 the working waveforms of several signals of the drive system 100 in Figure 4 where the charging unit 102 employs the charging unit 400 shown in Figure 5B shows another illustrative waveform diagram 500B, which depicts Figure 1 the working waveforms of several signals of the drive system 100 in Figure 4 , where the charging unit 102 also employs the Figure 5A and Figure 5B As can be seen from cg , in these examples, for each i traversing from 1 to N, the selected i-th output terminal OUT(i) correspondingly coupled to the i-th laser unit 101(i) among the N laser units {101(i), i = 1, 2, …, N} can be switched to the on state during the i-th charging time window T cg (i) between the i-th charging pulse and the (i + 1)-th charging pulse of the charging control PWM signal PWM_C.

[0073] Similar to Figure 3A and Figure 3B , in the Figure 5A and Figure 5B illustrative waveform diagrams shown, the graph labeled 103_G can represent an illustrative waveform of a control signal (for simplicity and ease of understanding, this control signal is also referred to as 103_G) for controlling at least one controllable power switch 103. In some examples, at least one controllable power switch 103 includes a field effect transistor ("FET"), and this control signal 103_G can be applied or provided to the gate of at least one controllable power switch 103. Those of ordinary skill in the art should understand that the detailed description related to the control signal 103_G with reference to Figure 3A and Figure 3B also applies to the examples of Figure 5A and Figure 5B , and for simplicity, it will not be repeated here.

[0074] In Figure 5A and Figure 5BIn the illustrative waveform diagram shown, for each i ranging from 1 to N, the graph labeled 104(i)_GH may represent an illustrative waveform of a high-side control signal (for simplicity and ease of understanding, this high-side control signal is also simply referred to as 104(i)_GH) for controlling the high-side switch MH within the i-th charge path control circuit 104(i) among the M charge path control circuits {104(j), j = 1, 2, …, M}. And the high-side control signal 104(i)_GH can be applied or provided to the control terminal n3 of the high-side switch MH of the i-th charge path control circuit 104(i), where the i-th charge path control circuit 104(i) is coupled to the selected i-th output terminal OUT(i). Those of ordinary skill in the art should understand that in this example, for each i ranging from 1 to N, the logical high level in the waveform diagram of the high-side control signal 104(i)_GH may indicate that the high-side switch MH in the i-th charge path control circuit 104(i) is switched to the on state, thereby enabling the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i). The logical low level in the waveform diagram of the high-side control signal 104(i)_GH may indicate that the high-side switch MH in the i-th charge path control circuit 104(i) is switched to the off state, thereby disabling the energy transfer / conduction path from the power supply output terminal BSTO to the selected i-th output terminal OUT(i). The high-side control signal 104(i)_GH can be provided or generated based on the charge control PWM signal PWM_C.

[0075] Those of ordinary skill in the art should understand that the above reference Figure 3A and Figure 3B The detailed description of the control signal 104(i)_G changing its control voltage level or control logic level in response to the charge control PWM signal PWM_C also applies to Figure 5A and Figure 5B the high-side control signal 104(i)_GH in the example. For simplicity, it will not be repeated here. For each i ranging from 1 to N, when the high-side switch MH of the i-th charge path control circuit 104(i) is switched to the on state, the i-th charge path control circuit 104(i) can be considered to have been switched to the on state. When the high-side switch MH of the i-th charge path control circuit 104(i) is switched to the off state, the i-th charge path control circuit 104(i) can be considered to have been switched to the off state. In this way, for each i ranging from 1 to N, the conduction time window Ton(i) of the i-th charge path control circuit 104(i) can be adaptively adjusted and flexibly controlled according to the charge control PWM signal PWM_C.

[0076] Continuing to refer to Figure 5A and Figure 5B In the illustrative waveform diagram shown, for each i ranging from 1 to N, the graph labeled 104(i)_GL can represent an illustrative waveform of the low-side control signal (for simplicity and ease of understanding, this low-side control signal is also simply referred to as 104(i)_GL) for controlling the low-side switch ML of the i-th charging path control circuit 104(i) among the M charging path control circuits {104(j), j = 1, 2, …, M}. This low-side control signal 104(i)_GL can be applied or provided to the control terminal of the low-side switch ML of the i-th charging path control circuit 104(i), where the i-th charging path control circuit 104(i) is correspondingly coupled to the selected i-th output terminal OUT(i). Those of ordinary skill in the art should understand that in Figure 5A and Figure 5B In the example shown, for each i ranging from 1 to N, the logical high level in the waveform diagram of the low-side control signal 104(i)_GL can represent that the low-side switch ML in the i-th charging path control circuit 104(i) is switched to the on state to discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. The logical low level in the waveform diagram of the low-side control signal 104(i)_GL can represent that the low-side switch ML in the i-th charging path control circuit 104(i) is switched to the off state to cut off the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. The low-side control signal 104(i)_GL can be provided or generated based on the charging control PWM signal PWM_C.

[0077] For example, in Figure 5AIn an exemplary embodiment, for each i traversing from 1 to N, the low-side control signal 104(i)_GL can change from a third control voltage level or a third control logic level (e.g., logic high) to a fourth control voltage level or a fourth control logic level (e.g., logic low) in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C, that is, generate the first transition edge (e.g., falling edge) of the low-side control signal 104(i)_GL to switch the low-side switch ML of the i-th charge path control circuit 104(i) to the off state, thereby preventing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. And the low-side control signal 104(i)_GL can change from a fourth control voltage level or a fourth control logic level (e.g., logic low) to a third control voltage level or a third control logic level (e.g., logic high) in response to the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, that is, generate the second transition edge (e.g., rising edge) of the low-side control signal 104(i)_GL to switch the low-side switch ML of the i-th charge path control circuit 104(i) to the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. This helps to discharge the residual energy / electricity on the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400 before the i-th charge path control circuit 104(i) is switched to the on state, or before the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled. This also ensures that the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled during the period from the occurrence of the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C to the occurrence of the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse. The predetermined on-delay time T don1 can help reduce any risk of damage caused by the high-side switch MH and the low-side switch ML in the i-th charge path control circuit 104(i) being simultaneously switched to the on state. The predetermined off-delay time T doff1 can help reduce any risk of damage that may be caused by the high-side switch MH and the low-side switch ML in the i-th charge path control circuit 104(i) being simultaneously switched to the on state.

[0078] Continue to refer to Figure 5A, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(1)_GL for controlling the low-side switch ML of the first charging path control circuit 104(1) changes from the third control logic level (e.g., logic high) to the fourth control logic level (e.g., logic low) to turn off the low-side switch ML of the first charging path control circuit 104(1), thereby terminating the discharge from the first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. Wherein, the first charging path control circuit 104(1) is coupled to the first output terminal OUT(1), and the output terminal OUT(1) is adapted to be coupled to the first laser unit 101(1). In response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(1)_GL changes from the fourth control logic level (e.g., logic low) to the third control logic level (e.g., logic high) to turn on the low-side switch ML in the first charging path control circuit 104(1) and allow the discharge from the first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. It is obvious to those of ordinary skill in the art that the description of the low-side control signal 104(1)_GL here also applies to the low-side control signals 104(2)_GL,..., 104(N)_GL. Therefore, for the sake of simplicity, it will not be repeated here.

[0079] In another example, as Figure 5BAs shown, for any i traversing from 1 to N, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(i)_GL changes from the third control voltage level or the third control logic level (e.g., logic high) to the fourth control voltage level or the fourth control logic level (e.g., logic low). That is, this response process generates the first transition edge (e.g., falling edge) of the low-side control signal 104(i)_GL to turn off the low-side switch ML of the i-th charge path control circuit 104(i) and disable the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. And, in response to the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(i)_GL changes from the fourth control voltage level or the fourth control logic level (e.g., logic low) to the third control voltage level or the third control logic level (e.g., logic high). That is, this response process generates the second transition edge (e.g., rising edge) of the low-side control signal 104(i)_GL to turn on the low-side switch ML of the i-th charge path control circuit 104(i) and allow the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. This helps to release the remaining energy / charge on the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400 before the i-th charge path control circuit 104(i) is turned on or before the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i) is enabled, and at the same time ensures that the discharge path from the i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled at least from the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C until the arrival of the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse. The predetermined turn-on delay time T don2 Helps to reduce the risk of damage caused by the simultaneous turn-on of the high-side switch MH and the low-side switch ML in the i-th charge path control circuit 104(i). The predetermined turn-off delay time T doff2 Helps to reduce the risk of damage caused by the simultaneous turn-on of the high-side switch MH and the low-side switch ML in the i-th charge path control circuit 104(i).

[0080] Continue to refer to Figure 5B, in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the second transition edge (e.g., falling edge)), the low-side control signal 104(1)_GL for controlling the low-side switch ML in the first charging path control circuit 104(1) changes from the third control voltage level or the third control logic level (e.g., logic high) to the fourth control voltage level or the fourth control logic level (e.g., logic low) to turn off the low-side switch ML of the first charging path control circuit 104(1) and disable the discharge from the selected first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. Among them, the first charging path control circuit 104(1) is coupled to the selected first output terminal OUT(1), and this output terminal OUT(1) is suitable for being coupled to the first laser unit 101(1). In response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge)), the low-side control signal 104(1)_GL changes from the fourth control voltage level or the fourth control logic level (e.g., logic low) to the third control voltage level or the third control logic level (e.g., logic high) to turn on the low-side switch ML of the first charging path control circuit 104(1) and allow the discharge from the selected first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. It is obvious to those of ordinary skill in the art that the description of the low-side control signal 104(1)_GL here also applies to the low-side control signals 104(2)_GL,..., 104(N)_GL. Therefore, for the sake of simplicity, it will not be repeated here.

[0081] Those of ordinary skill in the art should understand that the above reference Figure 5A and Figure 5BThe detailed description of the low-side control signal 104(i)_GL for controlling the low-side switch ML in the i-th charging path control circuit 104(i) to change its control voltage level or control logic level in response to the charging control PWM signal PWM_C is only an example and is not intended to be limiting. The charging unit 400 can be configured to change the control voltage level or control logic level of the low-side control signal 104(i)_GL in response to changes in the charging control PWM signal PWM_C to provide the low-side control signal 104(i)_GL in a variety of other ways. These ways cannot be described in detail here one by one, as long as these ways do not deviate from the spirit and scope of the present disclosure. As long as the low-side control signal 104(i)_GL can at least be turned on from the moment when the high-side switch MH of the i-th charging path control circuit 104(i) is turned on to the moment when the first switching edge (e.g., rising edge) of the (i+1)th charging pulse of the charging control PWM signal PWM_C arrives during the period T off(i) During the period T, the low-side switch ML of the i-th charging path control circuit 104 (i) is kept in the off state to ensure that off(i) The discharge path from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled, and the low-side control signal 104(i)_GL can be at least T off(i) The low-side switch ML of the i-th charging path control circuit 104 (i) is turned on within a predetermined time window outside the period to release the remaining energy / charge on the i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400, which is consistent with the spirit and scope of the present application.

[0082] To provide another exemplary embodiment, Figure 6 An illustrative waveform diagram is shown, depicting Figure 1 The working waveforms of several signals of the driving system 100, wherein the charging unit 102 adopts Figure 4 The charging unit 400 is shown. Figure 6 The exemplary embodiment shown is Figure 5A and Figure 5B The difference of the exemplary embodiment shown is that the control logic of the low-side control signal 104 (i) _GL has changed. Figure 6In the example, for each i traversing from 1 to N, the low-side control signal 104(i)_GL can be configured to provide a predetermined pre-discharge time window Tpre in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C. During this pre-discharge time window Tpre, the low-side control signal 104(i)_GL can have a third control logic level (e.g., logic high) to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. In one embodiment, for each i traversing from 1 to N, the low-side control signal 104(i)_GL can be configured to generate a pre-discharge pulse having a pre-discharge pulse width Tpre to define the pre-discharge time window Tpre. For each i traversing from 1 to N, the low-side control signal 104(i)_GL can be configured to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the off state outside the pre-discharge time window Tpre. In this way, before the high-side switch MH in the i-th charge path control circuit 104(i) is switched to the on state, or before the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled, the residual energy / charge on the selected i-th output terminal OUT(i) can be discharged, which helps to improve the control accuracy of the charging unit 400. The pre-discharge time window Tpre is shorter than a predetermined turn-on delay time T don1 short.

[0083] Still referring to Figure 6, in one embodiment, for each i traversing from 1 to N, the low-side control signal 104(i)_GL is set to provide a predetermined post-discharge time window Tpost in response to the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse of the charging control PWM signal PWM_C. During this post-discharge time window Tpost, the low-side control signal 104(i)_GL may have a third control logic level (e.g., logic high) and is configured to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. In one embodiment, for each i traversing from 1 to N, the low-side control signal 104(i)_GL may be configured to generate a post-discharge pulse having a predetermined post-discharge pulse width Tpost to define the predetermined post-discharge time window Tpost. For each i traversing from 1 to N, the low-side control signal 104(i)_GL may be configured to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the off state outside the predetermined post-discharge time window Tpost. This will help to further release the remaining energy / charge on the selected i-th output terminal OUT(i) before the high-side switch MH in the i-th charge path control circuit 104(i) is switched to the on state again, or before the energy transfer / transmission path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled again, which will help to improve the control accuracy of the charging unit 400. The predetermined post-discharge time window Tpost may be shorter than the predetermined turn-on delay time T don1 Short.

[0084] In one embodiment, for each i traversing from 1 to N, the low-side control signal 104(i)_GL can be configured to respond to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse respectively, and provide a predetermined pre-discharge time window Tpre and a predetermined post-discharge time window Tpost respectively. For each i traversing from 1 to N, during the predetermined pre-discharge time window Tpre and the predetermined post-discharge time window Tpost, the low-side control signal 104(i)_GL can be configured to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. For each i traversing from 1 to N, the low-side control signal 104(i)_GL can also be configured to control the low-side switch ML in the i-th charge path control circuit 104(i) to be in the off state outside the predetermined pre-discharge time window Tpre and the predetermined post-discharge time window Tpost.

[0085] Those of ordinary skill in the art should understand that the embodiments of the charging unit 102 are not limited to those examples mentioned in the above description related to Figures 1 to 6 the examples.

[0086] According to an exemplary embodiment, the charging unit 102 may further include a logic control circuit and a drive circuit block. The logic control circuit and the drive circuit block can be jointly configured to control at least one controllable power switch 103 and the M charge path control circuits {104(j), j = 1, 2,..., M} based on the charging control PWM signal PWM_C. In Figure 4 the example of, the logic control circuit 401 and the drive circuit block 402 are exemplarily shown.

[0087] According to an exemplary embodiment, the charging unit 102 may further include a fourth input terminal (e.g., chip select terminal) OS. In one example, the fourth input terminal OS may be configured to receive a chip select signal OS_C. The charging unit 102 may be configured to activate or deactivate operations of at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M} in response to the chip select signal OS_C received at the fourth input terminal OS. In one example, when the charging unit 102 performs the operation of activating the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M}, it means that the at least one controllable power switch 103 and the charging path control circuits {104(j), j = 1, 2, …, M} are operable or capable of processing signals or performing their respective functions. When the charging unit 102 performs the operation of deactivating the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M}, it means that the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M} are inoperable or disabled when the charging unit 102 performs the deactivation operation. In one example, when the chip select signal OS_C received at the fourth input terminal OS is in a first logic state (e.g., logic high) or when the chip select signal OS_C reaches or exceeds an activation threshold, the charging unit 102 may be configured to perform the operation of activating the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M}, and when the chip select signal OS_C received at the fourth input terminal OS is in a second logic state (e.g., logic low) or when the chip select signal OS_C is lower than the activation threshold, the charging unit 102 may be further configured to perform the operation of deactivating the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M}. Hereinafter, when the charging unit 102 is enabled to an operable state and the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M} are activated to an operable state, the charging unit 102 is considered to be in an on state. When the charging unit 102 is disabled and in an inoperable state, or when the at least one controllable power switch 103 and the M charging path control circuits {104(j), j = 1, 2, …, M} are deactivated and in an inoperable state, the charging unit 102 is considered to be in an off state.

[0088] According to one embodiment, the operability of the charging unit 102, the at least one controllable power switch 103, and the M charging path control circuits {104(j), j = 1, 2, …, M} in relation to the logic states of the enable signal EN_C and the chip select signal OS_C can be as shown in the following table.

[0089]

[0090] Table 1

[0091] Back to Figure 1, according to an exemplary embodiment, the drive system 100 may further include N capacitive energy storage devices CR(1), CR(2), …, CR(N) corresponding to the N laser units {101(i), i = 1, 2, …, N}. Hereinafter, the corresponding N capacitive energy storage devices CR(1), CR(2), …, CR(N) may be referred to or denoted as {CR(i), i = 1, 2, …, N}. In other words, at least in terms of quantity, the corresponding N capacitive energy storage devices {CR(i), i = 1, 2, …, N} match the N laser units {101(i), i = 1, 2, …, N}. In one example, the N capacitive energy storage devices {CR(i), i = 1, 2, …, N} may include capacitors, such as 0402NP0 capacitors or other capacitors compatible with the application requirements and meeting the requirements. In one embodiment, the N capacitive energy storage devices {CR(i), i = 1, 2, …, N} may be connected to the N laser units {101(i), i = 1, 2, …, N} in a one-to-one correspondence. That is, each of the N capacitive energy storage devices {CR(i), i = 1, 2, …, N} can be connected to a corresponding one of the N laser units {101(i), i = 1, 2, …, N} (for example, a VCSEL unit). In other words, for each i ranging from 1 to N, each of the N capacitive energy storage devices {CR(i), i = 1, 2, …, N}, that is, the i-th capacitive energy storage device CR(i), can be connected to a corresponding one of the N laser units {101(i), i = 1, 2, …, N}, that is, the i-th laser unit 101(i). For each i ranging from 1 to N, the first end of the i-th capacitive energy storage device CR(i) can be coupled to the first end (e.g., anode) of the corresponding i-th laser unit 101(i), while the second end of the i-th capacitive energy storage device CR(i) can be connected to the reference ground GND of the drive system 100. Here, the integer variable N is also used to describe or represent the total number of capacitive energy storage devices of the N capacitive energy storage devices {CR(i), i = 1, 2, …, N} included in the drive system 100 in this disclosure. In other words, the total number of capacitive energy storage devices of the N capacitive energy storage devices {CR(i), i = 1, 2, …, N} that the drive system 100 may include should match or be the same as the total number of laser units {101(i), i = 1, 2, …, N} that the integrated semiconductor laser 101 may include.For example, in an example where the integrated semiconductor laser 101 includes 28 laser units {101(i), i = 1, 2, …, 28}, the drive system 100 may include 28 capacitive energy storage devices {CR(i), i = 1, 2, …, 28}, which correspond to the 28 laser units {101(i), i = 1, 2, …, 28} and are respectively connected to the 28 laser units {101(i), i = 1, 2, …, 28}.

[0092] According to an exemplary embodiment, the drive system 100 may further include a discharge unit 106. The discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND of the drive system 100. In an exemplary embodiment, the discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND in a predetermined pattern in response to a discharge control PWM signal PWM_D, and the PWM signal PWM_D may be customer or user programmable.

[0093] According to an exemplary embodiment, for each N ranging from 1 to N, the discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND during a discharge time window (i.e., the i-th discharge time window T cg (i)) after the end of the i-th charging time window T dg (i). That is to say, the drive system 100 or the discharge unit 106 may be configured to perform corresponding operations corresponding to a first set (e.g., N) of discharge time windows, and the first set (e.g., N) of discharge time windows corresponds to the N laser units {101(i), i = 1, 2, …, N} or the N capacitive energy storage devices {CR(i), i = 1, 2, …, N}. Hereinafter, the first set (e.g., N) of discharge time windows T dg (1), T dg (2), …, T dg (N) may be referred to or represented as {T dg (i), i = 1, 2, …, N}. Here, N is an integer variable not less than 1 and may be set or determined by the customer / user according to actual application requirements. For example, for each N ranging from 1 to N, the discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND during the i-th discharge time window T cg (i) between the i-th charging time window T cg (i) and the (i + 1)-th charging time window T dg (i + 1). In another example, for each N ranging from 1 to N, the discharge unit 106 may be configured to be located during the i-th charging time window Tcg (i) the i-th discharge time window T between the (i + 1)-th charging pulse of the charging control PWM signal PWM_C dg (i), energy is released from the integrated semiconductor laser 101 to the reference ground terminal GND. According to an exemplary embodiment, the discharge control PWM signal PWM_D may have multiple pulses, and these pulses are configured to control the first set (e.g., N) of discharge time windows {T dg (i), i = 1, 2, …, N}. In an exemplary embodiment, the first discharge time window T dg (1), the second discharge time window T dg (2), …, the i-th discharge time window T dg (i), etc., may be controlled or determined respectively by a series of consecutive pulses of the discharge control PWM signal PWM_D. However, this is only provided as an example and is not intended to be limiting.

[0094] In an exemplary embodiment, the discharge unit 106 may have a first input terminal, such as an energy input terminal DRAIN. The first input terminal DRAIN of the discharge unit 106 may be coupled to the integrated semiconductor laser 101. In one example, the first input terminal DRAIN of the discharge unit 106 may be coupled to the second terminals of the N laser units {101(i), i = 1, 2, …, N} of the integrated semiconductor laser 101.

[0095] According to an exemplary embodiment, the discharge unit 106 may further include a reference ground terminal GND2. The discharge unit 106, as well as all sub-circuits or sub-elements that the discharge unit 106 may include, may be configured to use the reference ground potential on the reference ground terminal GND2 as the ground potential. In one example, the reference ground terminal GND2 of the discharge unit 106 may be connected to the reference ground terminal GND of the drive system 100.

[0096] According to an exemplary embodiment, the discharge unit 106 may further include a second input terminal, such as a PWM terminal PWM2. In one example, the second input terminal PWM2 of the discharge unit 106 may be configured to receive the discharge control PWM signal PWM_D. Although in Figure 1 the example, the second input terminal PWM2 of the discharge unit 106 is shown as a single terminal, this is not intended to limit its form.

[0097] Figure 7 An exemplary schematic diagram of the discharge unit 700 according to an exemplary embodiment of the present disclosure is shown. As an alternative exemplary embodiment of the present application, as Figure 7As shown, the second input terminal (e.g., PWM terminal) PWM2 of the discharge unit 106 may include a second positive input terminal PWM2+ and a second negative input terminal PWM2-. The discharge unit 700 can be used as an alternative to the discharge unit 106 in Figure 1 . In one example, the second positive input terminal PWM2+ of the discharge unit 106 can be configured to receive a first discharge control signal PWM_D+, and the second negative input terminal PWM2- of the discharge unit 106 can be configured to receive a second discharge control signal PWM_D-. In this case, the first discharge control signal PWM_D+ and the second discharge control signal PWM_D- define or determine the discharge control PWM signal PWM_D. For those skilled in the art, using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D- can adjust or control the first set (e.g., N) of discharge time windows {T dg (i), i = 1, 2,..., N} more flexibly and simply. For example, compared with the case of not using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D-, when using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D-, each pulse of the discharge control PWM signal PWM_D can have a narrower pulse width (which represents a narrower or shorter discharge time window). And the narrower pulse width or narrower discharge time window of the discharge control PWM signal PWM_D is beneficial to meet the actual requirements in laser driving applications.

[0098] According to an exemplary embodiment, the discharge unit 106 may further include a discharge path switching circuit 107. The discharge path switching circuit 107 can be configured to perform an on / off switching in response to the discharge control PWM signal PWM_D or in response to the first discharge control signal PWM_D+ and the second discharge control signal PWM_D-. When the discharge path switching circuit 107 is switched to the on state, the discharge path switching circuit 107 can be configured to transfer energy from the first input terminal DRAIN of the discharge unit 106 to the reference ground terminal GND2 of the discharge unit 106, and when the discharge path switching circuit 107 is switched to the off state, it can also be configured to stop or cut off the energy transfer from the first input terminal DRAIN to the reference ground terminal GND2. The energy transfer can be in the form of voltage, current, charge, etc. According to an exemplary embodiment, the discharge path switching circuit 107 can be switched to the on state during each of the first set (e.g., N) of discharge time windows, i.e., during the i-th discharge time window T dg (i). The discharge path switching circuit 107 can be in the first set (e.g., N) of discharge time windows {T dg(i), where i = 1, 2, …, N} is switched to the off state during the periods other than

[0099] According to an exemplary embodiment, the discharge path switching circuit 107 may include a controllable transistor. The controllable transistor may have a first terminal, a second terminal, and a control terminal. Its first terminal is coupled to the first input terminal DRAIN of the discharge unit 106, its second terminal is coupled to the reference ground terminal GND2 of the discharge unit 106, and its control terminal is configured to receive a control signal. In Figure 1 the example of, the discharge path switching circuit 107 is shown to include a metal oxide semiconductor field effect transistor (MOSFET). However, this is only provided as an example and is not intended to be limiting. In other embodiments, the discharge path switching circuit 107 may alternatively include other types of controllable transistors, such as DMOS, GaN FET, SiC FET, bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), or any combination thereof, etc.

[0100] According to an exemplary embodiment, the discharge unit 106 may further include a control circuit configured to control the discharge path switching circuit 107. In one embodiment, the discharge unit 106 may further include a drive circuit coupled between the control circuit and the discharge path switching circuit 107. The drive circuit is configured to drive the control terminal of the discharge path switching circuit 107 according to the output signal of the control circuit. For example, the drive circuit may be configured to provide a control signal to the control terminal of the controllable transistor in the discharge path switching circuit 107. In Figure 7 the example of, an exemplary illustration of the control circuit 701 and the drive circuit 702 is shown.

[0101] According to an exemplary embodiment, the discharge unit 106 may further include a third input terminal, such as a discharge unit power supply terminal VCC. The discharge unit power supply terminal VCC may be configured to receive a supply voltage suitable for providing an operating power supply for the discharge unit 106. For example, in Figure 7 the example of, a supply voltage of 3.3V is provided to the discharge unit power supply terminal VCC. However, this is only provided as an example and is not intended to be limiting.

[0102] According to an exemplary embodiment, the discharge unit 106 may further include a fault reporting terminal FLT2 configured to report any fault states, such as undervoltage (VCC UVLO), overtemperature (OTSD), etc. As Figure 7As shown, the discharge unit 106 may further include protection circuits configured to implement under-voltage (VCC UVLO), over-temperature (OTSD), and / or other fault protections. If the discharge unit 106 does not need to provide a fault reporting function in actual applications, the fault reporting terminal FLT2 may be omitted.

[0103] According to an exemplary embodiment, the charging unit 102 may be integrated on an integrated circuit (“IC”) die or chip and may be encapsulated in a package 800 as Figure 8 shown. In one example, the IC die or chip integrating the charging unit 102 may include a flip-chip die or chip. Correspondingly, the package 800 may have a flip-chip package form. The M output terminals (e.g., OUT(j), j = 1, 2, …, M) of the charging unit 102 are arranged in an output terminal array 801 of X rows by Y columns in the form of corresponding M conductive pads. The output terminal array 801 is disposed on the active surface of the package 800. Wherein, the variables X and Y are integers not less than 1, representing the total number of rows and the total number of columns of the output terminal array 801 respectively, and satisfying the relationship X * Y = M. For example, in Figure 8 the example, the package 800 is shown to include a charging unit 102 having 32 output terminals {OUT(j), j = 1, 2, …, 32}, and these output terminals are arranged in an output terminal array 801 of 4 rows by 8 columns. That is to say, in this specific example, M = 32, X = 4, and Y = 8. In Figure 8 the example, other terminals of the charging unit 102, such as the first input terminal (e.g., power terminal) IN1, the second input terminal (e.g., enable terminal) EN, the third input terminal (e.g., PWM terminal) PWM1, the reference ground terminal GND1, the fourth input terminal (e.g., selection terminal) OS, the indication terminal (e.g., fault indication terminal) FLT1, the switch terminal SW, the power output terminal BSTO, etc., may be arranged in one or more other terminal arrays, and these terminal arrays are also disposed on the active surface of the package 800. According to an exemplary embodiment, one or more other terminal arrays may have a plurality of conductive pads. According to an exemplary embodiment, one or more other terminal arrays may be disposed on one or more sides of the output terminal array 801. In Figure 8 the example, it is exemplarily illustrated that other terminals of the charging unit 102 are arranged in another terminal array 802 disposed at the bottom of the output terminal array 801. Those skilled in the art should understand that this is only an example and is not intended to be limiting.

[0104] According to an exemplary embodiment, the discharge unit 106 may be integrated on an integrated circuit (“IC”) die or chip and may be encapsulated in a package 900 as shown in Fig. 9 . In one example, the IC die or chip integrated with the discharge unit 106 may include a flip-chip die or chip, and correspondingly, the package 900 may have a flip-chip package form. The first input terminal (e.g., energy input terminal) DRAIN, reference ground terminal GND2, second input terminal (e.g., PWM terminal) PWM2, third input terminal (e.g., discharge unit power supply terminal) VCC, and fault reporting terminal FLT2 (if any) of the discharge unit 106 may be implemented in the form of corresponding multiple conductive pads and may be arranged on the active surface of the package 900. In one embodiment, for the reference ground terminal GND2, at least two conductive pads may be formed and symmetrically arranged on both sides of the center line of the discharge unit 106 in the package 900 ( Fig. 9 shown by the dashed line) to enhance its energy release capacity.

[0105] Fig.10 FIG. shows a package 950 including a discharge unit 700, which is integrated on an integrated circuit die / chip according to an embodiment of the present disclosure. A number of descriptions made with reference to the discharge unit 106 in the package 900 may be applicable to the discharge unit 700 in the package 950, because as previously described, the discharge unit 700 may be regarded as an implementation of the discharge unit 106. In Fig.10 the example, the second input terminal PWM is exemplified as the second positive input terminal PWM2+ and the second negative input terminal PWM2-, and the fault reporting terminal FLT2 may be omitted on the active surface of the package 950.

[0106] Fig.11FIG. 0 shows a schematic diagram of a drive system 150 according to an embodiment of the present disclosure. The drive system 150 is different from the drive system 100 in that its charging unit 102 may further include a set (e.g., represented by an integer variable K) of selection terminals SEL(0), SEL(1), …, SEL(K−1). Hereinafter, the set (e.g., K) of selection terminals SEL(0), SEL(1), …, SEL(K−1) may be referred to or represented as the K selection terminals {SEL(q), q = 0, 1, …, K−1}. Here, K is an integer variable representing the total number of selection terminals {SEL(q), q = 0, 1, …, K−1} included in the charging unit 102. Among them, q is an integer variable that traverses from 0 to K−1. The K selection terminals {SEL(q), q = 0, 1, …, K−1} may be configured to control or program a predetermined sequence or predetermined pattern for performing on / off switching on the M output terminals {OUT(j), j = 1, 2, …, M}. In one example, the K selection terminals {SEL(q), q = 0, 1, …, K−1} may be configured to control or program a predetermined sequence or predetermined pattern for performing on / off switching on the M charging path control circuits {104(j), j = 1, 2, …, M} of the charging unit 102. As described in the examples of the foregoing and Figure 3A , Figure 3B , Figure 5A , Figure 5B and Figure 6 , in these examples, the M output terminals {OUT(j), j = 1, 2, …, M} may be sequentially switched to the on state (i.e., in the order from OUT(1) to OUT(M)) according to a plurality of successive charging pulses of the charging control PWM signal PWM_C. Differently from these examples, in Fig.11 the example shown, the predetermined pattern or predetermined sequence of on / off switching of the i-th output terminal OUT(i) may be controlled or programmed by the K selection terminals {SEL(q), q = 0, 1, …, K−1}. In one embodiment, in order to make the predetermined pattern or predetermined sequence of on / off switching of the M output terminals {OUT(j), j = 1, 2, …, M} programmable / controllable, the integer variable K needs to satisfy 2 K ≥M.

[0107] Fig.12 FIG. 18 shows an exemplary embodiment of a charging unit 250, which may be used as an alternative embodiment of the charging unit 102 in Fig.11 . Compared with the charging unit 200 shown in Figure 2 , Fig.12The charging unit 250 further includes K selection terminals {SEL(q), q = 0, 1, …, K−1}. Those of ordinary skill in the art should understand that Figure 1 and Figure 2 a large number of related descriptions of the embodiments of Fig.11 and Fig.12 can be applied to the embodiments of Fig.11 and Fig.12 except that the predetermined pattern or predetermined order of the on / off switching of the M output terminals {OUT(j), j = 1, 2, …, M} is different. In the embodiments of

[0108] According to an exemplary embodiment, the K selection terminals {SEL(q), q = 0, 1, …, K−1} are adapted to receive a respective plurality (e.g., K) of selection control signals {SEL_C(q), q = 0, 1, …, K−1}. In one embodiment, the plurality (e.g., K) of selection control signals {SEL_C(q), q = 0, 1, …, K−1} may be implemented as a K-bit command signal. For example, for each selection control signal, the q-th selection control signal SEL_C(q) corresponds to the q-th bit in the K-bit command signal. In this way, a customer or user can program to control which one of the M output terminals {OUT(j), j = 1, 2, …, M} or which one of the M charge path control circuits {104(j), j = 1, 2, …, M} of the charging unit 102 to perform a turn-on operation at the start of each charging pulse of the charging control PWM signal PWM_C. For example, the K selection control signals {SEL_C(q), q = 0, 1, …, K−1} may include logic signals. At the start of each charging pulse of the charging control PWM signal PWM_C, the charging unit 102 may check the logic states of the K selection control signals {SEL_C(q), q = 0, 1, …, K−1} to determine which one of the M output terminals {OUT(j), j = 1, 2, …, M} should be turned on, or which one of the M charge path control circuits {104(j), j = 1, 2, …, M} should be turned on. If the s-th output terminal OUT(s) of the M output terminals {OUT(j), j = 1, 2, …, M} or the s-th charge path control circuit 104(s) of the M charge path control circuits {104(j), j = 1, 2, …, M} should be turned on, where s is an integer variable, then this integer variable s can be represented by the following equation (1). In equation (1), for each q traversing from 0 to (K−1), if the selection control signal SEL_C(q) is at a logic low at the start of each charging pulse of the charging control PWM signal PWM_C, then SEL_C(q) = 0; if the selection control signal SEL_C(q) is at a logic high at the start of each charging pulse of the charging control PWM signal PWM_C, then SEL_C(q) = 1. Hereinafter, for ease of description and understanding, the s-th output terminal OUT(s) of the M output terminals {OUT(j), j = 1, 2, …, M} programmed to be turned on according to equation (1) is referred to as the programmed s-th output terminal OUT(s), and the s-th charge path control circuit 104(s) of the M charge path control circuits {104(j), j = 1, 2, …, M} associated with the s-th output terminal OUT(s) programmed to be turned on is referred to as the programmed s-th charge path control circuit 104(s).

[0109]

[0110] For example, Fig.13 illustrates an exemplary waveform diagram 350, which shows Fig.11 the working waveforms of several signals of the drive system 150 in Fig.12 As shown, the charging unit 102 includes a charging unit 250 as shown in Figure 3A and Figure 3B and, by way of example, has 5 selection terminals {SEL(q), q = 0, 1, …, 4}, that is, K = 5. Those skilled in the art should understand that Fig.13 the waveforms exemplary described in Fig.13 can be applied to the waveforms shown in Fig.13 with the difference that in the example of cg (j), the predetermined pattern or predetermined order of the on / off switching of each of the M output terminals {OUT(j), j = 1, 2, …, M} can be controlled / programmed by the K selection terminals {SEL(q), q = 0, 1, …, K−1}, while in the example shown in cg K = 5. That is, for each j traversing 1 to M, the position or order of the j-th charging time window T Figure 3A and Figure 3B in which the j-th output terminal OUT(j) is switched to the on state can be controlled / programmed by the K selection terminals {SEL(q), q = 0, 1, …, K−1}. Thus, for some embodiments, a first set of output terminals {OUT(i), i = 1, 2, …, N} selected from the M output terminals {OUT(j), j = 1, 2, …, M} respectively drive a first set (e.g., N) of laser units {101(i), i = 1, 2, …, N}. For any i traversing 1 to N, the i-th charging time window T cg (i) in which the i-th output terminal OUT(i) is in the on state may no longer be Fig.13 as shown in the examples of

[0111] necessarily located after the i-th charging pulse of the charging control PWM signal PWM_C. Instead, the order or position of the i-th charging time window T Fig.13It can be seen that in this example, during the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 0, 0, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 2. Therefore, in this example, based on the first charging pulse of the charging control PWM signal PWM_C, the second output terminal OUT(2) among the M output terminals {OUT(j), j = 1, 2,..., M} or the second charging path control circuit 104(2) among the M charging path control circuits {104(j), j = 1, 2,..., M} will be programmed and controlled to be turned on. That is, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don1 (similar to Figure 3A 's description), or in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don2 (similar to Figure 3B 's description), the control signal 104(2)_G for controlling the second charging path control circuit 104(2) among the M charging path control circuits {104(j), j = 1, 2,..., M} can transition from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high) to turn on the second charging path control circuit 104(2) and enable the energy transfer path from the power output terminal BSTO to the second output terminal OUT(2). And, in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-off delay time T doff1 (similar to Figure 3A 's description), or in response to the next charging pulse of the charging control PWM signal PWM_C, i.e., the first transition edge (e.g., rising edge) of the second charging pulse and experiencing a predetermined turn-off delay time T doff2 (similar to Figure 3B(as described), the control signal 104(2)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to turn off the second charge path control circuit 104(2) and disable the energy transfer path from the power output terminal BSTO to the second output terminal OUT(2). In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the second output terminal OUT(2) in the example can be made to be turned on during the second charging time window T after the first charging pulse of the charging control PWM signal PWM_C. cg (2).

[0112] Similarly, in Fig.13 the example, during the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {0, 0, 0, 0, 0} respectively, which means s = 1 + 0 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 1. Therefore, in this example, based on the second charging pulse of the charging control PWM signal PWM_C, the first output terminal OUT(1) among the M output terminals {OUT(j), j = 1, 2,..., M} or the first charge path control circuit 104(1) among the M charge path control circuits {104(j), j = 1, 2,..., M} will be programmed to be turned on. That is, in response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don1 (similar to Figure 3A the description), or in response to the second transition edge (e.g., falling edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don2 (similar to Figure 3B(description), the control signal 104(1)_G for controlling the first charging path control circuit 104(1) among the M charging path control circuits {104(j), j = 1, 2, …, M} can transition from a first control voltage level or a first control logic level (e.g., logic low) to a second control voltage level or a second control logic level (e.g., logic high) to turn on the first charging path control circuit 104(1), and enable the energy transfer path from the power supply output terminal BSTO to the first output terminal OUT(1). And, in response to the second transition edge (e.g., falling edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-off delay time T doff1 (similar to Figure 3A description), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the third charging pulse, and experiencing a predetermined turn-off delay time T doff2 (similar to Figure 3B description), the control signal 104(1)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to turn off the first charging path control circuit 104(1), and disable the energy transfer path from the power supply output terminal BSTO to the first output terminal OUT(1). In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the first output terminal OUT(1) in the example can be turned on during the first charging time window T cg (1) after the second charging pulse of the charging control PWM signal PWM_C.

[0113] During the twelfth charging pulse of the charging control PWM signal PWM_C, the logical states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 1, 1, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 1 * 2 1 + 1 * 2 2 + 0 * 2 3 + 0 * 2 4= 8. Thus, in this example, based on the twelfth charging pulse of the charging control PWM signal PWM_C, the eighth output terminal OUT(8) among the M output terminals {OUT(j), j = 1, 2, …, M} or the eighth charging path control circuit 104(8) among the M charging path control circuits {104(j), j = 1, 2, …, M} will be programmed and controlled to be turned on. That is, in response to the first transition edge (e.g., rising edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don1 (similar to Figure 3A 's description), or in response to the second transition edge (e.g., falling edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don2 (similar to Figure 3B 's description), the control signal 104(8)_G for controlling the eighth charging path control circuit 104(8) among the M charging path control circuits {104(j), j = 1, 2, …, M} can transition from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high) to turn on the eighth charging path control circuit 104(8), and enable the energy transfer path from the power supply output terminal BSTO to the eighth output terminal OUT(8). And, in response to the second transition edge (e.g., falling edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-off delay time T doff1 (similar to Figure 3A 's description), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the thirteenth charging pulse, and experiencing a predetermined turn-off delay time T doff2 (similar to Figure 3B 's description), the control signal 104(8)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to turn off the eighth charging path control circuit 104(8), and disable the energy transfer path from the power supply output terminal BSTO to the eighth output terminal OUT(8). In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the eighth output terminal OUT(8) in the example can be turned on during the eighth charging time window T cg (8) after the twelfth charging pulse of the charging control PWM signal PWM_C.

[0114] Those of ordinary skill in the art should understand that regarding Fig.12 and Fig.13 For the example of Fig.13 , the above description applies to a more general case where the s-th output terminal OUT(s) among the M output terminals {OUT(j), j = 1, 2, …, M} or the s-th charge path control circuit 104(s) associated with the s-th output terminal OUT(s) among the M charge path control circuits {104(j), j = 1, 2, …, M} can be programmed to turn on according to Equation (1) at the i-th charging pulse of the charging control PWM signal PWM_C. For example, in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don1 (similar to Figure 3A the description), or in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T don2 (similar to Figure 3B the description), the control signal 104(s)_G for controlling the s-th charge path control circuit 104(s) among the M charge path control circuits {104(j), j = 1, 2, …, M} can transition from a first control voltage level or a first control logic level (e.g., logic low) to a second control voltage level or a second control logic level (e.g., logic high) to turn on the s-th charge path control circuit 104(s) and enable the energy transfer path from the power supply output terminal BSTO to the s-th output terminal OUT(s). And, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-off delay time T doff1 (similar to Figure 3A the description), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the (i + 1)-th charging pulse, and experiencing a predetermined turn-off delay time T doff2 (similar to Figure 3B the description), the control signal 104(s)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to turn off the s-th charge path control circuit 104(s) and disable the energy transfer path from the power supply output terminal BSTO to the s-th output terminal OUT(s). In this way, for each i ranging from 1 to N, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the s-th output terminal OUT(s) can be made to have the s-th charging time window T after the i-th charging pulse of the charging control PWM signal PWM_C cg(s) is turned on during the

[0115] Those of ordinary skill in the art should understand that the above reference Fig.12 and Fig.13 The detailed description of the control signal 104(s)_G for controlling the s-th charge path control circuit 104(s) in the charging unit 250 changing its control voltage level or control logic level in response to the charging control PWM signal PWM_C is merely an example and is not intended to be limiting. The charging unit 250 can be configured to change the control voltage level or control logic level of the control signal 104(s)_G in response to changes in the charging control PWM signal PWM_C in various other ways to provide the control signal 104(s)_G. These ways cannot be elaborated one by one here, as long as these ways do not depart from the spirit and scope of this disclosure, they are acceptable. As long as the s-th conduction time window Ton(s) of the s-th charge path control circuit 104(s) coupled to the s-th output terminal OUT(s) can be controlled to start during the period when the controllable power switch 103 is kept on (e.g., in response to the i-th charging pulse of the charging control PWM signal PWM_C) and end no later than the moment when the controllable power switch 103 is turned off in response to the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, such ways are in line with the spirit and scope of this application. In this way, the charging unit 250 can be configured to flexibly adjust the s-th conduction time window Ton(s) to ensure that the charge path control circuit 104(s) coupled to the programmed s-th output terminal OUT(s) is turned on no later than the moment when the s-th charging time window T cg (s) starts, enabling the energy transfer path from the power output terminal BSTO to the programmed s-th output terminal OUT(s), and the charge path control circuit 104(s) coupled to the programmed s-th output terminal OUT(s) is turned off no later than the moment when the s-th charging time window T cg (s) starts, disabling the energy transfer path from the power output terminal BSTO to the programmed s-th output terminal OUT(s), where the next programmed s-th output terminal OUT(s) is turned on after the s-th output terminal OUT(s).

[0116] Fig.14 Shows an exemplary schematic diagram of a charging unit 450 according to another exemplary embodiment of the present disclosure. This charging unit 450 can be used as Fig.11 An alternative embodiment of the charging unit 102 in Figure 4 Compared with the charging unit 400 shown in Fig.14The charging unit 450 further includes the K selection terminals {SEL(q), q = 0, 1, …, K−1}. Those skilled in the art should understand that, Figure 1 and Figure 4 the illustrated embodiments and their corresponding descriptions can be applied to Fig.11 and Fig.14 the embodiments in Fig.11 and Fig.14 wherein, in the embodiments of

[0117] Fig.15 a illustrative waveform diagram 550 is shown, which shows the working waveforms of several signals of the drive system 150 in Fig.11 wherein the charging unit 102 includes the charging unit 450 as shown in Fig.14 and, as an example, has five selection terminals {SEL(q), q = 0, 1, …, 4}, that is, K = 5. Those skilled in the art should understand that, Figure 5A and Figure 5B the waveforms described by way of example in Fig.15 can be applied to Fig.15 the example shown in Fig.15 wherein K = 5 in the example shown in cg (j). For each j traversing from 1 to M, the position or order of the j-th charging time window T cg (j) at which the j-th output terminal OUT(j) is switched to the on state can be controlled / programmed by the K selection terminals {SEL(q), q = 0, 1, …, K−1}. Thus, in the exemplary embodiment, when a set (e.g., N) of output terminals is selected from the M output terminals {OUT(j), j = 1, 2, …, M} to drive the N laser units {101(i), i = 1, 2, …, N}, for each i traversing from 1 to N, the i-th charging time window T Figure 5A and Figure 5Bmust be located after the i-th charging pulse of the charging control PWM signal PWM_C as shown. Conversely, the i-th output terminal OUT(i) is switched to the on state at the i-th charging time window T cg (i)'s position or order can be controlled / programmed by the K selection terminals {SEL(q), q = 0, 1, …, K - 1}, where, in Fig.15 the example shown K = 5.

[0118] Similar to Fig.13 the waveforms shown in the example, as can be seen from the Fig.15 example, at the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} respectively provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 0, 0, 0, 0}, which means s = 1 + 1 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 2. Therefore, in this example, by programming, the second output terminal OUT(2) among the M output terminals {OUT(j), j = 1, 2, …, M} or the second charging path control circuit 104(2) among the M charging path control circuits {104(j), j = 1, 2, …, M} is turned on at the first charging pulse of the charging control PWM signal PWM_C. At the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} respectively provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {0, 0, 0, 0, 0}, which means s = 1 + 0 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4= 1. Thus, in this example, it is programmed such that the first output terminal OUT(1) among the M output terminals {OUT(j), j = 1, 2, …, M} or the first charge path control circuit 104(1) among the M charge path control circuits {104(j), j = 1, 2, …, M} is turned on at the second charging pulse of the charging control PWM signal PWM_C. At the twelfth charging pulse of the charging control PWM signal PWM_C, the logical states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {1, 1, 1, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 1 * 2 1 + 1 * 2 2 + 0 * 2 3 + 0 * 2 4 = 8. Thus, in this example, it is programmed such that the eighth output terminal OUT(8) among the M output terminals {OUT(j), j = 1, 2, …, M} or the eighth charge path control circuit 104(8) among the M charge path control circuits {104(j), j = 1, 2, …, M} is turned on at the twelfth charging pulse of the charging control PWM signal PWM_C.

[0119] More specifically, in the examples of Fig.14 and Fig.15 , the on / off switching of the output terminal OUT(s) programmed through multiple (e.g., K) selection terminals {SEL(q), q = 0, 1, …, K - 1} can be achieved by controlling the high-side switch MH and the low-side switch ML in the charge path control circuit 104(s) coupled or associated with the programmed output terminal OUT(s). Those of ordinary skill in the art should understand that the detailed description of the change in the control voltage level or control logic level of the control signal 104(s)_G generated in response to the charging control PWM signal PWM_C as described in the examples of Fig.12 and Fig.13 also applies to the high-side control signal 104(s)_GH in the examples of Fig.14 and Fig.15 , and for the sake of brevity, it will not be repeated here.

[0120] Regarding the low-side control signal 104(s)_GL, it can be understood that the description of the low-side control signal 104(i)_GL of the low-side switch ML in the i-th charge path control circuit 104(i) as described in the examples with reference to Figure 5A and Figure 5B applies to Fig.14 and Fig.15 In the example of the programmed low-side control signal 104(s)_GL of the low-side switch ML of the s-th charging path control circuit 104(s). That is, the low-side control signal 104(s)_GL can be at least in the period T from the moment when the high-side switch MH of the s-th charging path control circuit 104(s) is turned on based on the i-th charging pulse of the charging control PWM signal PWM_C to the moment when the first switching edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C arrives. off(i) The low-side switch ML of the programmed sth charging path control circuit 104(s) is kept in the off state to ensure that during the period T off(i) The discharge path from the programmed sth output terminal OUT(s) to the reference ground terminal GND1 is disabled, and the low-side control signal 104(s)_GL can be at least T off(s) The low-side switch ML of the s-th charging path control circuit 104 (s) is turned on within a predetermined time window outside the period to release the remaining energy / charge on the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450 .

[0121] Fig.16 An illustrative waveform diagram 650 is shown, depicting Fig.11 In this example, the charging unit 102 can still be considered to include Fig.14 The charging unit 450 is shown and has five selection terminals {SEL(q), q=0, 1, . . . , 4} as an example, that is, K=5. Fig.16 The exemplary embodiment shown is Fig.15 One difference in the exemplary implementation shown is that the control logic of the low-side control signal 104(s)_GL is changed, while the control logic of the high-side control signal 104(s)_GH is the same as Fig.15 The same as described in. A person skilled in the art with ordinary skills should understand that Fig.16 In the example, the control logic of the low-side control signal 104(s)_GL is Figure 6 That is, according to Fig.16Example, at any charging pulse of the charging control PWM signal PWM_C (e.g., the i-th charging pulse, ranging from 1 to M), the s-th output terminal OUT(s) among the M output terminals {OUT(j), j = 1, 2,..., M} or the s-th charging path control circuit 104(s) associated with the s-th output terminal OUT(s) of the M charging path control circuits {104(j), j = 1, 2,..., M} can be programmed to turn on according to Equation (1). Then, in one embodiment, the low-side control signal 104(s)_GL provides a predetermined pre-discharge time window Tpre in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C. During this pre-discharge time window Tpre, the low-side control signal 104(s)_GL can have a third control logic level (e.g., logic high) to control the low-side switch ML in the s-th charging path control circuit 104(s) to be in the on state, thereby allowing discharge from the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450, and the low-side control signal 104(s)_GL can be configured to control the low-side switch ML in the s-th charging path control circuit 104(s) to be in the off state outside the pre-discharge time window Tpre. In another embodiment, in order to respond to the first transition edge (e.g., rising edge) of the next charging pulse (i.e., the (i + 1)-th charging pulse after the (i + 1)-th charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(s)_GL may be configured to generate a predetermined post-discharge time window Tpost. During this post-discharge time window Tpost, the low-side control signal 104(2)_GL can have a third control logic level (e.g., logic high), and can be applicable to control the low-side switch ML in the programmed s-th charging path control circuit 104(s) to be in the on state, and discharge energy from the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450, and the low-side control signal 104(s)_GL can be adapted to control the low-side switch ML in the programmed s-th charging path control circuit 104(s) to be in the off state outside the predetermined post-discharge time window T post Outside. In another embodiment, the low-side control signal 104(s)_GL can be adapted to respectively respond to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and the first transition edge (e.g., rising edge) of the (i + 1)-th charging pulse of the charging control PWM signal PWM_C, and provide a predetermined pre-discharge time window T pre And a predetermined post-discharge time window T post .

[0122] For example, from Fig.16 As can be seen from the exemplary and illustrative waveforms shown, in the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {1, 0, 0, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 2, to control or program the second output terminal OUT(2) or the second charging path control circuit 104(2) to be switched to the on state, and the control logic of the high-side control signal 104(2)_GH of the high-side switch MH in the second charging path control circuit 104(2) can be the same as that described in the Fig.15 example. For the low-side control signal 104(2)_GL, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(2)_GL is adapted to provide a predetermined pre-discharge time window T pre . Within this time window, the low-side control signal 104(2)_GL can have a third control logic level (e.g., logic high) to control the low-side switch ML in the second charging path control circuit 104(2) to turn on, and is adapted to discharge energy from the second output terminal OUT(2) to the reference ground terminal GND1 of the charging unit 450. The low-side control signal 104(2)_GL can further be adapted to provide a predetermined post-discharge time window T in response to the first transition edge (e.g., rising edge) of the next charging pulse (i.e., the second charging pulse here) after the first charging pulse of the charging control PWM signal PWM_C post , to control the low-side switch ML in the second charging path control circuit 104(2) to turn on, and during the post-discharge time window T post期 to discharge energy from the second output terminal OUT(2) to the reference ground terminal GND1 of the charging unit 450. A similar description applies to the low-side control signal 104(1)_GL. In the example shown, at the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {0, 0, 0, 0, 0} respectively, which means s = 1 + 0 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4= 1 to control or program the first output terminal OUT(1) or the first charge path control circuit 104(1) to be switched to the on state. A similar description applies to the low-side control signal 104(8)_GL. In the illustrated example, at the 12th charging pulse of the charging control PWM signal PWM_C, the logical states of the control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {1, 1, 1, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 1 * 2 1 + 1 * 2 2 + 0 * 2 3 + 0 * 2 4 = 8 to control or program the eighth output terminal OUT(8) or the eighth charge path control circuit 104(8) to be switched to the on state.

[0123] According to another embodiment of the present disclosure, the charging unit 102 can be integrated on an integrated circuit (“IC”) die or chip and can be encapsulated in a package 850 as shown in Fig.17 the illustrated package 850. Fig.17 One difference between the illustrated package 850 and Figure 8 the illustrated package 800 is that the package 850 can further include the K selection terminals {SEL(q), q = 0, 1, …, K−1}. In one example, the K selection terminals {SEL(q), q = 0, 1, …, K−1} are arranged in a selection terminal array 851 of the package 850 in the form of corresponding K conductive pads. The selection terminal array 851 is disposed on the active surface of the package 850. In Fig.17 the example, the charging unit 102 encapsulated in the package 850 can include Fig.12 the illustrated charging unit 250 or Fig.14 the illustrated charging unit 450. In Fig.17 , 32 output terminals {OUT(j), j = 1, 2, …, 32} are exemplarily shown, and these output terminals are arranged in a 4-by-8 output terminal array 801 (i.e., M = 32, X = 4, and Y = 8). Thus, in this example, to ensure that the on / off switching of each of the 32 output terminals {OUT(j), j = 1, 2, …, 32} can be programmed / controlled in a predetermined pattern or sequence, the value of K can be determined as 5 according to 2 K ≥ M = 32.

[0124] Fig.18 is a board-level layout diagram of an application corresponding to the drive system 100 or 150 of Figure 1 or Fig.11 according to an embodiment of the present disclosure. According to an exemplary embodiment of the present disclosure, 18A to 18F shows the Figure 1 drive system 100 in Fig.11 or the drive system 150 in Fig.18 and 18A to 18F for each layer of the application board - level layout diagram corresponding to the drive system 100 or 150. In one embodiment, the drive system 100 or 150 is placed on a multi - layer circuit board, such as a printed circuit board (PCB) 1800. Now, with reference to Fig.18 and 18A to 18F , the multi - layer circuit board level 1800 for the drive system 100 or 150 will be described. The multi - layer circuit board 1800 may include a plurality of (e.g., represented by the integer variable H) board levels 180(1), 180(2),..., 180(H). After that, the plurality of (e.g., H) board levels 180(1), 180(2),......, 180(H) can be referred to as or represented by {180(h), h = 1, 2,......, H}. Here, H is an integer variable not less than 1, representing the total number of board levels 180(1), 180(2),......, 180(H) that the multi - layer circuit board level 1800 may include, and in actual applications, it can be set or determined by the customer / user according to actual application requirements. In one embodiment, the plurality of (e.g., H) circuit board levels {180(h), h = 1, 2,..., H} can be arranged one by one in the order from 180(1) to 180(H). That is to say, the first board level 180(1) can be the top - most layer of the multi - layer circuit board level 1800, and the H - th board level 180(H) can be the bottom - most layer of the multi - layer circuit board level 1800, and the remaining board levels 180(2) to 180(H - 1) (if any) can be intermediate board levels sandwiched between the first board level 180(1) and the H - th board level 180(H). For each h from 1 to (H - 1), the h - th board level 180(h) is placed on top of the (h + 1) - th board level 180(h + 1). In the example shown in Fig.18 and 18A to 18F , the multi - layer circuit board level 1800 includes six board levels {180(h), h = 1, 2,..., 6}, that is, in this example, H = 6, 18A to 18F showing the plan views of each layer in the six board levels {180(h), h = 1, 2,..., 6} respectively. However, this is only an example and is not restrictive.

[0125] In one embodiment, with reference to Fig.18ATop view. The integrated semiconductor laser 101 can be placed and mounted on the first board level 180(1) of the multi-layer circuit board level 1800, in a predetermined laser mounting area 181 on the top surface of the first board level 180(1). It can be understood that the top surface of the first board level 180(1) can also be referred to as the top surface of the multi-layer circuit board level 1800. Here, an integrated semiconductor laser 101 with a first plurality (for example, N = 28) of laser units {101(i), i = 1, 2,..., 28} is taken as an example for illustration. On the top surface of the multi-layer circuit board 1800, a corresponding first plurality (for example, N = 28) of electrical connection structures 184 can be provided at a predetermined connection structure area 183. In one embodiment, each electrical connection structure 184 can include a pad portion 1841 (represented by small circles in the exemplary drawings) connected to an interlayer connection via 188 and a connection trace 1842 connected to the pad portion 1841. The corresponding first plurality (for example, N = 28) of electrical connection structures 184 can be configured to provide electrical interconnection availability between the integrated semiconductor laser 101 and other components (for example, the first plurality (for example, N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} and the charging unit 102 in the drive system 100 or 150). For example, in one embodiment, the first terminals of the first plurality (for example, N = 28) of laser units {101(i), i = 1, 2,..., 28} are respectively connected to the corresponding first plurality (for example, N = 28) of electrical connection structures 184 in a one-to-one correspondence. That is, the first end (for example, the anode) of each unit in the first plurality (for example, N = 28) of laser units {101(i), i = 1, 2,..., 28} is connected to a corresponding one of the electrical connection structures 184, for example, by a bonding wire 185. In Fig.18A , the first terminals (for example, anodes) of each of the first plurality (for example, N = 28) of laser units {101(i), i = 1, 2,..., 28} are represented by small orange squares. The second terminals (for example, cathodes) of the first plurality (for example, N = 28) of laser units {101(i), i = 1, 2,..., 28} of the integrated semiconductor laser 101 are electrically connected together by a conductive sheet 182 ( Fig.18A shown in red in the figure). The conductive sheet 182 is placed in the predetermined laser mounting area 181 on the top surface of the first board level 180(1) and is located below the integrated semiconductor laser 101. The corresponding first plurality (for example, N = 28) of electrical connection structures 184 are separated from each other and are electrically isolated from the conductive sheet 182.

[0126] As Fig.18AAs shown, in one embodiment, a first portion of a corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} can be arranged and mounted in a predetermined capacitive device mounting area 186 on the top surface of the first board level 180(1). The predetermined capacitive device mounting area 186 on the top surface of the multi-layer circuit board level 1800 can be as close as possible to the predetermined laser mounting area 181, e.g., located on the first side of the predetermined laser mounting area 181D (such as Figures 18 to 18F the upper side indicated by the arrow 180U pointing upward in the example) or the second side of the predetermined laser mounting area 181 (such as Figures 18 to 18F the lower side indicated by the arrow 180D pointing downward in the example). The predetermined connection structure area 183 can be arranged between the predetermined laser mounting area 181 and the predetermined capacitive device mounting area 186 on the top surface of the multi-layer circuit board level 1800. In this way, the interconnection between the integrated semiconductor laser 101 and the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} can be more easily achieved, and the interconnection resistance will also be smaller.

[0127] Now referring to Fig.18F the plan view of the bottom surface of the multi-layer circuit board level 1800 shown in, this multi-layer circuit board level 1800 can also be regarded as a bottom view observed from the bottom surface of the H-th board level 180(H) of the bottom layer (H = 6 in this example). A second portion of a corresponding first plurality (e.g., 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} can be arranged and mounted on a predetermined capacitive device mounting area 187 on the bottom surface of the H-th board level 180(H). It can be understood that the bottom surface of the H-th board level 180(H) can also be referred to as the bottom surface of the multi-layer circuit board level 1800. This will help improve the space utilization rate and save the overall size or circuit board area of the multi-layer circuit board level 1800 required to implement and install the drive system 100 or 150. In one embodiment, the position of the predetermined capacitive device mounting area 187 on the bottom surface of the multi-layer circuit board level 1800 can be matched with the position of the predetermined capacitive device mounting area 186 on the top surface of the multi-layer circuit board level 1800. For example, the projection of the predetermined capacitive device mounting area 187 on the upper surface of the multi-layer circuit board level 1800 can coincide with the predetermined capacitive device mounting area 186.

[0128] In one embodiment, a first portion of a corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} includes a first number NUM1 of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28}. And a second portion of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} includes a second number NUM2 of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28}. In one embodiment, the first number NUM1 and the second number NUM2 are substantially the same. For example, in a specific example where N = 28, the first portion may include the first 14 capacitive energy storage devices {CR(i), i = 1, 2, …, 7 and i = 15, 16, …, 21}, and the second portion may include the last 14 capacitive energy storage devices {CR(i), i = 8, 9, …, 14 and i = 22, 23, …, 28}. However, those of ordinary skill in the art will understand that in other embodiments, the first number NUM1 and the second number NUM2 are not necessarily exactly the same, and a customer or user may set other appropriate values. In another embodiment, all of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} may be placed on the top or bottom surface of a multi-layer circuit board level 1800.

[0129] In one embodiment, the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} may be electrically coupled to a corresponding first plurality (e.g., N = 28) of electrical connection structures 184 to be coupled to a first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2, ..., 28} of an integrated semiconductor laser 101. That is, each of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} may be electrically coupled to one of the corresponding first plurality (e.g., N = 28) of electrical connection structures 184. For example, a first terminal of each capacitive energy storage device among the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28} is electrically coupled to a corresponding one of the electrical connection structures 184. In Figures 18 to 18FIn the example shown, the first terminal of each capacitive energy storage device in the first part of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} can be connected to the connection trace 1842 of a corresponding one of the electrical connection structures 184 within the top surface of the multi-layer circuit board level 1800. That is, the electrical connection between the first part of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} and the corresponding electrical connection structure 184 can be implemented on the first board level 180(1) within the top surface of the multi-layer circuit board level 1800. The first terminal of each capacitive energy storage device in the second part of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} can be coupled to the connection trace 1842 of a corresponding one of the electrical connection structures 184 through an inter-layer connection via 188. The inter-layer connection via 188 is formed between every two adjacent circuit board levels among a plurality (e.g., H) of circuit board levels {180(h), h = 1, 2,..., H} (e.g., H = 6) according to the actual connection requirements. That is, the electrical connection between the second part of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} provided on the bottom surface of the multi-layer circuit board level 1800 and the corresponding electrical connection structure 184 provided on the top surface of the multi-layer circuit board level 1800 can be achieved through the inter-layer connection via 188. Hereinafter, it should be understood that the inter-layer connection via 188 can be formed flexibly according to the electrical connections required between circuit board levels, which is easily understood by those of ordinary skill in the art, and thus no more detailed description or explanation is needed here. Each inter-layer connection via 188 is filled with a conductive material. As Figures 18 to 18F shown, the inter-layer connection vias 188 formed between each circuit board level {180(h), h = 1, 2,..., H} and the immediately adjacent circuit board level above it are represented by small circles in each circuit board level floor plan. And the slightly larger circles drawn to coincide with each small circle represent the conductive pads formed on each circuit board level {180(h), h = 1, 2,..., H} to receive a corresponding one of the inter-layer connection vias 188.

[0130] In one embodiment, as Fig.18A shown, the discharge unit 106 can be mounted on the first board level 180(1) in a manner with its active surface facing down on a predetermined discharge unit mounting area 189 on the top surface of the multi-layer circuit board level 1800. The discharge unit 106 can be in the form of a packaged IC as referenced Fig. 9 or Fig.10 described. Since the active surface is facing down on the top surface of the multi-layer circuit board level 1800, the multiple terminals on the active surface of the discharge unit 106 are at Fig.18Ashown in the top view as a dashed line, the active surface includes a first input terminal (e.g., an energy input terminal) DRAIN, a reference ground terminal GND2, a second input terminal (e.g., a PWM terminal) PWM2 or a second positive input terminal PWM2+ and a second negative input terminal PWM2-, a third input terminal (e.g., a discharge unit power supply terminal) VCC, and a fault reporting terminal FLT2 (if any). A predetermined discharge unit mounting area 189 on the top surface of the multi-layer circuit board level 1800 can be as close as possible to the predetermined laser mounting area 181. For example, it can be set on the first side of the predetermined laser mounting area 181 (e.g., Figures 18 to 18F the upper side indicated by the arrow 180U pointing upward in the example), or it can be set on the second side of the predetermined laser mounting area 181 (e.g., Figures 18 to 18F the lower side indicated by the arrow 180D pointing downward in the example). In one embodiment, the predetermined discharge unit mounting area 189 and the predetermined capacitive device mounting area 186 can be arranged on the same side of the top surface of the multi-layer circuit board level 1800 (e.g., Figures 18 to 18F the first side in the shown embodiment). In this way, the interconnection between the integrated semiconductor laser 101, the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}, and the discharge unit 106 can be more easily achieved, and the interconnection resistance is smaller.

[0131] In one embodiment, the first input terminal DRAIN (the conductive pad of the first input terminal DRAIN) of the discharge unit 106 can be electrically connected to the conductive sheet 182 through, for example, a conductive trace 190 ( Fig.18A also shown in red), so as to be electrically connected to the second terminals of the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} of the integrated semiconductor laser 101. In one example, the discharge unit 106 can be symmetrically placed along the middle line 180M of the multi-layer circuit board level 1800, that is, the discharge unit 106 is mounted so that the middle line of the discharge unit 106 substantially coincides with the middle line 180M of the multi-layer circuit board level 1800. This will be beneficial to improving the energy discharge performance of the integrated semiconductor laser 101. For example, from the second terminals of each of the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} to the discharge unit 106, and then to the reference ground terminal GND. The conductive trace 190 extends from below the first input terminal DRAIN to the conductive sheet 182 and is connected thereto.

[0132] Refer to Fig.18A, in one embodiment, the conductive pads of the reference ground terminal GND2 of the discharge unit 106 can be electrically coupled to the second terminals of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} through, for example, a conductive sheet 191. The conductive sheet 191 is symmetrically distributed on both sides of the middle line 180M on the top surface of the multi-layer circuit board level 1800. The conductive sheet 191 extends from below the conductive pads of the reference ground terminal GND2 of the discharge unit 106 and reaches below the second terminals of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}. The conductive sheet 191 is separated and electrically isolated from the conductive trace 190. The conductive sheet 191 can be configured as the reference ground GND on the first board level 180(1) of the multi-layer circuit board 1800 and can be connected to the reference ground GND of the drive system 100 or 150. In one embodiment, the conductive trace 190 can extend substantially along the middle line 180M of the multi-layer circuit board level 1800 and between the symmetrically arranged conductive sheets 191, starting from below the first input terminal DRAIN and reaching and connecting to the conductive sheet 182.

[0133] The electrical connections of the other terminals in the discharge unit 106, including the second input terminal (e.g., PWM terminal) PWM2, the third input terminal (e.g., discharge unit power supply terminal) VCC, and the fault reporting terminal FLT2 (if any), can be implemented using various printed circuit wiring schemes according to the connection requirements, which are obvious to those of ordinary skill in the art and will not be described in detail herein.

[0134] As Fig.18A shown, in one embodiment, the charging unit 102 can be mounted with its active surface facing down at a predetermined charging unit mounting area 192 on the top surface of the multi-layer circuit board level 1800 of the first board level 180(1). The charging unit 108 can be in the form of a packaged IC as Figure 8 or Fig.17 described. Since the active surface of the discharge unit 102 is mounted facing down on the top surface of the multi-layer circuit board level 1800, the terminals of the discharge unit 102 are formed on the active surface of the charging unit 102, at Fig.18AIn the top view shown, it is represented by a dashed line. The terminals of the discharge unit 102 include a second plurality (e.g., M = 32) of conductive pads for a second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., M = 32}, a first input terminal (e.g., power supply terminal) IN1, a second input terminal (e.g., enable terminal) EN, a third input terminal (e.g., PWM terminal) PWM2, a reference ground terminal GND1, a fourth input terminal (e.g., selection terminal) OS, an indication terminal (e.g., fault indication terminal) FLT1, a switch terminal SW, a power supply output terminal BSTO, and selection pins (if any, e.g., Figures 18 to 18F five selection pins SEL(0), SEL(1),......, SEL(4)) as shown. The predetermined charging device mounting area 192 on the top surface of the multi-layer circuit board level 1800 can be as close as possible to the predetermined capacitive device mounting area 186. For example, it can be arranged on the first side of the predetermined laser mounting area 181 (e.g., Figures 18 to 18F the upper side indicated by the arrow 180U pointing upward in the example), or it can be arranged on the second side of the predetermined laser mounting area 181 (e.g., Figures 18 to 18F the lower side indicated by the arrow 180D pointing downward in the example) 。 In one embodiment, the predetermined discharge unit mounting area 189 and the predetermined capacitive device mounting area 186 can be arranged on the same side of the top surface of the multi-layer circuit board level 1800 (e.g., Figures 18 to 18F the first side in the shown embodiment). However, this does not mean a limitation. In another embodiment, the predetermined charging device mounting area 192 can be arranged on the other side opposite to the side where the predetermined capacitive device mounting area 186 is arranged (e.g., Figures 18 to 18F the second side indicated by the arrow 180D in the shown example) (e.g., Figures 18 to 18F the first side indicated by the arrow 180U in the shown example). Therefore, in this embodiment, the second power switch 105 and the inductive energy storage device L can be arranged and mounted on the top surface of the multi-layer circuit board level 1800 close to the charging unit 102, so that it is easier to form a power conversion device.

[0135] In one embodiment, the electrical coupling from a second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., 32} to a first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} and corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} can be achieved through intermediate board levels 180(2) to 180(H - 1) sandwiched between the first board level 180(1) and the H-th board level 180(H). In Figures 18 to 18F the shown example, H = 6. In FIG. 18B to FIG. 18F In the plan views of the respective intermediate board levels 180(2) to 180(H-1) shown separately, the charging unit 102 is shown by a dashed line to illustrate that the charging unit 102 is not actually installed on each intermediate board level, but only to help better understand the relative positions and electrical coupling relationships described below.

[0136] Now refer to Fig.18B the plan view of the top surface of the second board level 180(2) shown, which in this embodiment can also be regarded as a top view of the top surface of the second board level 180(2). A conductive bus 193 is formed to connect a first group of output terminals among the second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., 32} to the corresponding first group of laser units among the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} and the corresponding first group of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}. In this example, the first group of output terminals shown includes output terminals OUT(2) to OUT(8). The output terminals OUT(2) to OUT(8) are selected to be respectively coupled to the first group of laser units 101(1) to 101(7) and the first group of capacitive energy storage devices CR(1) to CR(7). Therefore, in this example, the first group of output terminals OUT(2) to OUT(8) are the re-numbered selected output terminals OUT(1) to OUT(7) respectively coupled to the first group of laser units 101(1) to 101(7). This helps better understand the description with reference to Figures 1 to 17 which is about how a customer randomly selects or selects any first plurality (e.g., N) of output terminals among the second plurality (e.g., M) of output terminals {OUT(j), j = 1, 2,..., M} to correspondingly drive the first plurality (e.g., N) of laser units {101(i), i = 1, 2,..., 28}. In one embodiment, a conductive sheet 194 can be formed on the second board level 180(2) for receiving and connecting to an interlayer connection via 188, which is used to connect a conductive sheet 191 of the reference ground terminal GND on the first board level 180(1).

[0137] Now refer to Fig.18CA plan view of the top surface of the third board level 180(3) shown, which in this embodiment can also be regarded as a top view of the top surface of the third board level 180(3). The conductive bus 195 is formed to connect a second group of output terminals among the second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., 32} to corresponding second groups of laser units among the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} and corresponding second groups of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}. In this example, the second group of output terminals shown includes output terminals OUT(10) to OUT(16). The output terminals OUT(10) to OUT(16) are selected to be respectively coupled to the second group of laser units 101(8) to 101(14) and the second group of capacitive energy storage devices CR(8) to CR(14). Thus, in this example, the second group of output terminals OUT(10) to OUT(16) are the re-numbered selected output terminals OUT(8) to OUT(14) correspondingly coupled to the second group of laser units 101(8) to 101(16). In one embodiment, a conductive sheet 196 can be formed on the third board level 180(3) for receiving and connecting to the interlayer connection via 188, which is used to connect the conductive sheet 194 of the reference ground terminal GND on the second board level 180(2).

[0138] Now refer to Fig.18DA plan view of the top surface of the fourth board level 180(4) shown, which in this embodiment can also be regarded as a top view of the top surface of the fourth board level 180(4). The conductive bus 197 is formed to connect a third group of output terminals among the second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., 32} to corresponding third groups of laser units among the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} and corresponding third groups of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}. In this example, the said third group of output terminals includes output terminals OUT(18) to OUT(24). The output terminals OUT(18) to OUT(24) are selected to be respectively coupled to the third group of laser units 101(15) to 101(21) and the third group of capacitive energy storage devices CR(15) to CR(21). Thus, in this example, the third group of output terminals OUT(18) to OUT(24) are the re-numbered selected output terminals OUT(15) to OUT(21) respectively coupled to the third group of laser units 101(15) to 101(21). In one embodiment, a conductive sheet 198 can be formed on the fourth board level 180(3) for receiving and connecting to an interlayer connection via 188, which is used to connect a conductive sheet 196 of the reference ground terminal GND on the third board level 180(3).

[0139] Now refer to Fig.18EA plan view of the top surface of the fifth board level 180(5) shown in the figure, which can also be regarded as a top view of the top surface of the fifth board level 180(5) in this embodiment. The conductive bus 199 is formed to connect the fourth group of output terminals among the second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2,..., 32} to the corresponding fourth group of laser units among the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2,..., 28} and the corresponding fourth group of capacitive energy storage devices among the first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28}. In this example, the fourth group of output terminals includes output terminals OUT(26) to OUT(32). The output terminals OUT(26) to OUT(32) are selected to be respectively coupled to the fourth group of laser units 101(22) to 101(28) and the fourth group of capacitive energy storage devices CR(22) to CR(28). Therefore, in this example, the fourth group of output terminals OUT(26) to OUT(32) are the re-numbered selected output terminals OUT(22) to OUT(28) respectively coupled to the fourth group of laser units 101(22) to 101(28). In one embodiment, a conductive sheet 1991 can be formed on the fifth board level 180(5) for receiving and connecting to the interlayer connection via 188, which is used to connect the conductive sheet 198 of the reference ground terminal GND on the fourth board level 180(4).

[0140] In the above manner, in Figure 18-18FIn a specific embodiment shown, the charging unit 102 has a first plurality (e.g., N = 28) of output terminals OUT(2) to OUT(8), OUT(10) to OUT(16), OUT(18) to OUT(24), and OUT(26) to OUT(32) selected from a second plurality (e.g., M = 32) of output terminals {OUT(j), j = 1, 2, …, 32} for driving a corresponding first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2, ..., 28}. The charging unit 102 can be mounted on a multi-layer circuit board 1800 and can be implemented by an intermediate circuit board sandwiched between a first circuit board level 180(1) and an H-th circuit board level 180(H) (H = 6 in this example) to achieve electrical coupling from the first plurality (e.g., N = 28) of selected output terminals to the first plurality (e.g., N = 28) of laser units {101(i), i = 1, 2, ..., 28} and corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28}. Although in this example, the first plurality (e.g., N = 28) of selected output terminals are divided into four groups, it should be understood that in other embodiments, the first plurality (e.g., N = 28) of selected output terminals can be divided into more or fewer groups, and more or fewer intermediate circuit boards can be formed accordingly to achieve electrical coupling from the first plurality (e.g., N = 28) of selected output terminals to the first plurality (e.g., N = 28) of laser units {101(i, i = 1, 2, ..., 28} and corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2, ..., 28}. Those of ordinary skill in the art can understand that in other embodiments, the number of intermediate circuit boards 180(2) to 180(H - 1) included in the multi-layer circuit board level 1800 and the total number H of circuit boards 180(1) to 180(H) can depend on the number N of the first plurality of laser units {101(i), i = 1, 2, ..., N} to be driven, the number of groups into which the first plurality of selected output terminals re-numbered as {OUT(i), i = 1, 2, ..., N} are divided, and / or the number of rows (e.g., X rows) of the output terminal matrix 801 of the package enclosing the charging unit 102, etc.

[0141] The other terminals of the charging unit 102 can be implemented by different printed circuit wiring schemes according to connection requirements, which is obvious to those of ordinary skill in the art and need not be described in detail herein. The other terminals include a first input terminal (e.g., a power supply terminal) IN1, a second input terminal (e.g., an enable terminal) EN, a third input terminal (e.g., a PWM terminal) PWM1, a reference ground terminal GND1, a fourth input terminal (e.g., a selection terminal) OS, an indication terminal (e.g., a fault indication terminal) FLT1, a switch terminal SW, a power output terminal BSTO, and selection pins (if any, e.g., Figure 18-18F five selection pins SEL(0), SEL(1),..., SEL(4)) in the example.

[0142] Referring again to Fig.18F , a conductive sheet 1992 can be formed and used for the reference ground terminal GND of the bottommost Hth board level 180(H) (in this example, H = 6). The conductive sheet 1992 can be electrically connected to the conductive sheet 1991 for the reference ground terminal GND on the fifth board level 180(5). In this example, the fifth board level 180(5) is located above the bottommost sixth board level 180(6). The first terminal of each of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} in the second part (e.g., including capacitive energy storage devices CR(15) to CR(28) in this example) can be connected to a connection trace 1993 formed on the bottom surface of the multi-layer circuit board level 1800, and then coupled through an interlayer connection via 188 to a connection trace 1842 of a corresponding electrical connection structure 184 on the top surface of the multi-layer circuit board level 1800. The interlayer connection via 188 can be formed between every two adjacent circuit board levels among a plurality (e.g., H) of circuit board levels {180(h), h = 1, 2,..., H} (in this example, H = 6) according to actual connection requirements. The second terminal of each of the corresponding first plurality (e.g., N = 28) of capacitive energy storage devices {CR(i), i = 1, 2,..., 28} in the second part (e.g., including capacitive energy storage devices CR(15) to CR(28) in this example) can be connected to the conductive sheet 1992, and the conductive sheet 1992 is connected to the reference ground terminal GND of the drive system 100 or 150.

[0143] In another embodiment, the charging unit 102 can be mounted with its active surface facing down on the bottommost Hth board level 180(H), where FIG. 18G to FIG. 18H H = 6 in the example shown. Figure 18G A plan view of the top surface of the first board level 180(1) is shown, which can also be regarded as a top view observed from the top surface of the first board level 180(1) in an alternative embodiment. Fig.18HShows a plan view of the bottom surface of the multi-layer circuit board level 1800, which can also be considered as a bottom view observed from the bottom surface of the bottom-most H-th board level 180(H). In this alternative example, H = 6. Those of ordinary skill in the art should understand that the substantial description made with reference to Figures 18 to 18F applies to the example of FIG. 18G to FIG. 18H . The difference may be that, in this alternative embodiment, the predetermined charging device installation area 192 can be arranged on the bottom surface of the multi-layer circuit board level 1800. Accordingly, in one embodiment, the second power switch 105 and the inductive energy storage device L can be arranged and installed on the bottom surface of the multi-layer circuit board level 1800 near the charging unit 102 in this alternative embodiment, so that it is easier to form a power conversion device.

[0144] It is obvious to those of ordinary skill in the art that in the Figures 18G to 18H shown alternative example, the description and illustration of the intermediate circuit board levels 180(2) to 180(5) formed between the first circuit board level 180(1) and the bottom-most H-th circuit board level 180(H) (for example, H = 6) can be similar to the description and illustration made with reference to Figures 18B to 18E , except that the positions of the conductive buses (for example, 193, 195, 197, and 199) need to be changed according to the position change of the predetermined charging unit installation area 192 (and the position change of the charging unit 102), and no detailed description is needed here.

[0145] Figure 19 Shows a schematic diagram of a drive system 1000 according to an embodiment of the present disclosure. The drive system 1000 includes two drive systems 100. The drive system 1000 can be configured to drive an integrated semiconductor laser device 1001, and the number of laser units included in the integrated semiconductor laser device 1001 (for example, 2*N) is twice the number of laser units of the semiconductor laser device 101 (for example, N). The integrated semiconductor laser device 1001 can be regarded as including two semiconductor laser devices 101. In one embodiment, the operating sequence of the two charging units 102 in the drive system 1000, and the operating sequence of the two drive systems 100 can be set by a customer or user through the fourth input terminal (for example, chip select terminal) OS of each charging unit 102. For example, when the system 1000 is enabled by an enable signal EN_C provided to the enable terminal EN of each charging unit 102, by providing a chip select signal OS_C1 to the chip select terminal OS of the first charging unit 102 (for example, Figure 19 the left one in Figure 19The chip select terminal OS on the right side in the figure provides a chip select signal OS_C2, and the second charging unit 102 can be programmed to turn on after the first charging unit 102 is turned off to drive the second group of N laser units in the integrated semiconductor laser device 1001. The chip select signal OS_C1 and the chip select signal OS_C2 may have complementary logic levels to ensure that the first charging unit 102 and the second charging unit 102 are not both in the on state, that is, when the chip select signal OS_C1 is at a logic high, the chip select signal OS_C2 should be at a logic low, and vice versa. Those of ordinary skill in the art should understand that when the first charging unit 102 and the second charging unit 102 are in the on state, their operating modes can follow the above description about Figures 1 to 17 which will not be repeated here. The charging control PWM signal PWM_C1 provided to the third input terminal (e.g., PWM terminal) PWM1 of the first charging unit 102, and the charging control PWM signal PWM_C2 provided to the third input terminal (e.g., PWM terminal) PWM1 of the second charging unit 102, can come from the same charging control PWM signal PWM_C or be different. However, when the first charging unit 102 is in the on state, the charging control PWM signal PWM_C1 can function in the same way as the charging control PWM signal PWM_C in the above Figures 1 to 17 and its corresponding description, and the same is true for the charging control PWM signal PWM_C2 when the second charging unit 102 is in the on state, which will not be repeated here. The discharge control PWM signal PWM_D1 provided to the second input terminal PWM2 of the first discharge unit 106, and the discharge control PWM signal PWM_D2 provided to the second input terminal PWM2 of the second discharge unit 106, can come from the same discharge control PWM signal PWM_D or be different. However, when the first charging unit 102 (and the corresponding first drive system 100) is in the on state, the discharge control PWM signal PWM_D1 can function in the same way as the discharge control PWM signal PWM_D in the above Figures 1 to 17 and its corresponding description, and the same is true for the discharge control PWM signal PWM_D2 when the second charging unit 102 (and the corresponding first drive system 100) is in the on state, which will not be repeated here.

[0146] Figure 20The schematic diagram of a drive system 1500 according to an embodiment of the present disclosure is shown. The drive system 1500 can be considered to include two drive systems 150. The drive system 1500 can be configured to drive an integrated semiconductor laser device 1001, and the number of laser units included in the drive integrated semiconductor laser device 1001 (e.g., 2*N) is twice the number of laser units in the semiconductor laser device 101 (e.g., N). The integrated semiconductor laser 1001 can be regarded as including two semiconductor lasers 101. In one embodiment, similar to the above Figure 19 example, the operating sequence of the two charging units 102 in the drive system 1500, as well as the operating sequence of the corresponding two drive systems 150, can be set by a customer or user through the fourth input terminal (e.g., chip select terminal) OS of each charging unit 102. For example, when the system 1500 is enabled by an enable signal EN_C provided to the enable terminal EN of each charging unit 102, by providing a chip select signal OS_C1 to the chip select terminal OS of the first charging unit 102 (e.g., Figure 20 the left one in Figure 20 ), the first charging unit 102 can be programmed to turn on first to drive the first group of N laser units of the integrated semiconductor laser device 1001 in the drive system 1500. For another example, by providing a chip select signal OS_C2 to the chip select terminal OS of the second charging unit 102 (e.g., Figures 11 to 17 the right one in Figures 11 to 17It functions in the same way as the charging control PWM signal PWM_C in its corresponding description. The same applies to the charging control PWM signal PWM_C2 when the second charging unit 102 (and its corresponding second drive system 150) is in the on state, which will not be repeated here. The discharge control PWM signal PWM_D1 provided to the second input terminal PWM2 of the first discharge unit 106 and the discharge control PWM signal PWM_D2 provided to the second input terminal PWM2 of the second discharge unit 106 can come from the same discharge control PWM signal PWM_D or be different. However, when the first charging unit 102 (and the corresponding first drive system 150) is in the on state, the discharge control PWM signal PWM_D1 can be in accordance with the above Figures 11 to 17 It functions in the same way as the discharge control PWM signal PWM_D in its corresponding description. The same applies to the discharge control PWM signal PWM_D2 when the second charging unit 102 (and the corresponding first drive system 150) is in the on state, which will not be repeated here.

[0147] Figure 21A shows an application board-level layout diagram related to Figure 19 the drive system 1000 in Figure 20 or related to the drive system 1500 in

[0148] Figures 21B to 21G shows an application board-level layout diagram of each layer related to Figure 19 the drive system 1000 in Figure 20 or related to the drive system 1500 in

[0149] In one embodiment, the drive system 1000 or 1500 is installed on a multi-layer circuit board, such as a printed circuit board (PCB) 2100. Now, reference will be made to Figures 21A to 21G, a multi - layer circuit board 2100 for driving system 1000 or 1500 will be described. The multi - layer circuit board 2100 may include multiple (e.g., represented by an integer variable H) board levels 210(1), 210(2),..., 210(H). After that, the multiple (e.g., H) board levels 210(1), 210(2),......, 210(H) can be referred to as or represented by {210(h), h = 1, 2,......, H}. Here, H is an integer variable not less than 1, representing the total number of board levels 210(1), 210(2),......, 210(H) that the multi - layer circuit board 2100 can include, which can be set or determined by the customer / user according to actual application requirements in practical applications. That is to say, h is a variable that traverses integers from 1 to H. In one embodiment, the multiple (e.g., H) board levels {210(h), h = 1, 2,..., H} can be arranged one by one in the order from 210(1) to 210(H). That is, the first board level 210(1) can be the topmost layer of the multi - layer circuit board 2100, and the H - th board level 210(H) can be the bottom - most layer of the multi - layer circuit board 2100, and the remaining board levels 210(2) to 210(H - 1) (if any) can be intermediate board levels sandwiched between the first board level 210(1) and the H - th board level 210(H). For each h from 1 to (H - 1), the h - th board level 210(h) is placed on top of the (h + 1)-th board level 210(h + 1). In Figures 21A to 21G In the example shown, the multi - layer circuit board 2100 includes six board levels {210(h), h = 1, 2,..., 6}, that is, H = 6 in this example, Figures 21B to 21G and the plan views of each layer in the six board levels {210(h), h = 1, 2,..., 6} are respectively shown. However, this is only for illustration and is not restrictive.

[0150] In one embodiment, referring to Figure 21B the top - view, the integrated semiconductor laser 1001 can be arranged and mounted on the first board level 210(1) of the multi - layer circuit board 2100, at a predetermined laser - mounting area 181 on the upper surface of the first board level 210(1). It can be understood that the top surface of the first board level 210(1) can also be referred to as the top surface of the multi - layer circuit board 2100. As described in the existing references Figure 19 and Figure 20 , the integrated semiconductor laser 1001 can be regarded as including two semiconductor lasers 101, and the number of laser units of the laser unit of the integrated semiconductor laser device 1001 is twice the number of the first multiple (e.g., N = 28) laser units {101(i), i = 1, 2,..., 28} in the semiconductor laser device 101. For example, as Figures 18 to 18HCompared with the example shown, here, 2*N = 56 laser units 2*{101(i), i = 1, 2,..., 28} are taken as an example. For ease of description, the top surface of the first board level 210(1) for receiving the predetermined laser installation area of the integrated semiconductor laser 1001 is still labeled as 181.

[0151] It is not difficult for those of ordinary skill in the art to understand that the board-level layout diagram (as shown in Figure 19 ) implemented on the multi-layer circuit board 2100 corresponding to the drive system 1000 of Figure 20 or the drive system 1500 of Figures 21A to 21G can be regarded as being modified from the board-level layout diagram (as shown in Figure 1 ) corresponding to the drive system 100 of Figure 11 or the drive system 150 of Figures 18 to 18H . For example, two layouts (including layer-by-layer layout and electrical coupling) implemented on the multi-layer circuit board 1800 by the drive system 100 of Figure 1 or the drive system 150 of Figure 11 can be used to obtain the board-level layout diagram implemented on the multi-layer circuit board 2100 corresponding to the drive system 1000 of Figure 19 or the drive system 1500 of Figure 20 , except that the integrated semiconductor laser 101 installed in the predetermined laser installation area 181 is replaced by the integrated semiconductor laser 1001. Thereafter, for ease of description and understanding, Figure 1 the drive system 100 in Figure 11The board-level layout of the drive system 150 implemented on the multi-layer circuit board 1800 (including the layout of each layer and the electrical coupling between each board level and every two board levels) can be referred to as N laser unit drive system layout units. That is to say, the board-level layout implemented on the multi-layer circuit board 2100 can be regarded as including two such N-laser unit drive system layout units, which are respectively referred to as the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2). Each of the two N laser unit drive system layout units can be flexibly arranged within the multi-layer circuit board 2100 according to actual design considerations. The first N laser unit drive system layout unit U(1) is at least configured to implement the installation and electrical coupling of the first charging unit 102 and the first discharging unit 106, so as to cooperate with the first N capacitive energy storage devices {CR(i), i = 1, 2,..., N} in the drive system 1000 or 1500, thereby driving the first N laser units {101(i), i = 1, 2,..., N} of the integrated semiconductor laser 1001. The second N laser unit drive system layout unit U(2) is at least configured to implement the installation and electrical coupling of the second charging unit 102 and the second discharging unit 106, so as to cooperate with the second N capacitive energy storage devices {CR(i), i = 1, 2,..., N} in the drive system 1000 or 1500, thereby driving the second N laser units {101(i), i = 1, 2,..., N} of the integrated semiconductor laser device 1001. In Figures 21A to 21G In the example shown, N = 28.

[0152] For example, as Figures 21A to 21G shown, the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2) are respectively arranged on the first side 180U and the second side 180D of the predetermined laser installation area 181 for receiving and installing the integrated semiconductor laser 1001. In this embodiment, the integrated semiconductor laser 1001 can be regarded as including two semiconductor lasers 101. Those of ordinary skill in the art can understand that the description made with reference to Figures 18A to 18H basically applies to the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2), so there is no need to repeat it here.

[0153] In Figures 21A to 21G the example shown, each of the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2) is composed of Figures 18 to 18FCopied from the layout shown. The second N laser unit drive system layout unit U(2) is arranged such that it coincides with the first N laser unit drive system layout unit U(1) when rotated 180° with reference to the midline 180M of the multilayer circuit board 2100. In another embodiment, the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2) can be symmetrically arranged and aligned with reference to another midline 180M' perpendicular to the midline 180M of the multilayer circuit board 2100. In another embodiment, each unit in the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2) may not be Figures 18 to 18F an exact repetition of the layout shown. For example, in one embodiment, the first discharge unit 106 in the first N laser unit drive system layout unit U(1) and the corresponding first N capacitive energy storage devices {CR(i), i = 1, 2, …, N}, and the second discharge unit 106 in the second N laser unit drive system layout unit U(2) and the corresponding second N capacitive energy storage devices {CR(i), i = 1, 2, …, N} can be symmetrically arranged and aligned with reference to another midline 180M' of the multilayer circuit board 2100, while the first charging unit 102 in the first N laser unit drive system layout unit U(1) and the second charging unit 102 in the second N laser unit drive system layout unit U(2) are not necessarily symmetrically arranged with reference to another midline 180M' of the multilayer circuit board 2100.

[0154] Figure 22 Shows a schematic diagram of a drive system 2000 according to an embodiment of the present disclosure. The drive system 2000 can be considered to include multiple (e.g., z) drive systems 150 (or drive systems 100). Although Figure 22The example shows z drive systems 150. However, those skilled in the art should understand that in another embodiment, the drive system 2000 may include z drive systems 100, and the description provided here also applies to the case where it includes z drive systems 100. Here, z is an integer variable not less than 1, which represents the total number of drive systems 150 (or drive 100) included in the drive system 2000, and z can be set by the customer / user in the actual application according to the actual application requirements. The drive system 2000 can be configured to drive an integrated semiconductor laser device, and the number of laser units that the integrated semiconductor laser device can include (e.g., z*N) is z times the number of laser units (e.g., N) in the semiconductor laser device 101. Therefore, it can be considered that the drive system 2000 is configured to drive multiple (e.g., z) semiconductor laser devices 101. In one embodiment, the operating order of the multiple (e.g., z) charging units 102 in the drive system 2000, and the corresponding operating order of the multiple (e.g., z) drive systems 150 (or 100) can be set by the customer or user through the fourth input terminal (e.g., chip select terminal) OS of each charging unit 102. For example, when the system 2000 is enabled by the enable signal EN_C provided to the enable terminal EN of each charging unit 102, for example, by setting the chip select signal (e.g., labeled OS_C(r)) provided to the chip select terminal OS of one of the charging units 102 (e.g., the r-th charging unit 102 among the z charging units 102) to a logic high level to turn on the r-th charging unit 102, and at the same time setting the chip select signals provided to the chip select terminals OS of the remaining charging units 102 to a logic low level to turn them all off, the z charging units 102 (and the corresponding z drive systems 150 or 100) can be programmed to achieve turn-on one by one. Here, r is an integer variable that traverses from 1 to z. Those skilled in the art should understand that the operating mode of each of the z charging units 102 when turned on can follow the above Figures 1 to 17 description, which will not be repeated here. For each r that traverses from 1 to z, the charging control PWM signal PWM_C(r) provided to the third input terminal (e.g., PWM terminal) PWM1 of the r-th charging unit 102 can be from the same charging control PWM signal PWM_C or different. However, when the r-th charging unit 102 (correspondingly, the r-th drive system 150 or 100) is in the on state, the charging control PWM signal PWM_C1 can follow the above Figures 1 to 17It functions in the same way as the charging control PWM signal PWM_C in its corresponding description, which will not be repeated here. The discharge control PWM signal PWM_D(r) provided to the second input terminal PWM2 of the r-th discharge unit 106 can be from the same discharge control PWM signal PWM_D or different. However, when the r-th charging unit 102 (correspondingly, the r-th drive system 150 or 100) is in the on state, the discharge control PWM signal PWM_D(r) can be in accordance with the above Figures 1 to 18 It functions in the same way as the discharge control PWM signal PWM_D in its corresponding description, which will not be repeated here.

[0155] Those of ordinary skill in the art can understand that the drive system 2000 can be implemented and installed on a multi-layer circuit board such as a printed circuit board (PCB), similar to the way the above drive system 100 or 150 is implemented and installed on the multi-layer circuit board 1800 and the drive system 1000 or 1500 is implemented and installed on the multi-layer circuit board 2100. The multi-layer circuit board used to implement the drive system 2000 can be regarded as including a plurality of (for example, z) N laser unit drive system layout units.

[0156] Figure 23 An illustrative waveform diagram 2300 according to an exemplary embodiment of the present disclosure is shown, which shows Figure 11 the working waveforms of several signals when the drive system 150 operates in the parallel output mode. In the parallel output mode, each group of every T output terminals among the second plurality of (for example, M) output terminals {OUT(j), j = 1, 2,..., M} can be programmed to be turned on simultaneously each time, for example, in every T working cycles or every T charging pulses of the charging control PWM signal PWM_C. The variable T is an integer variable not less than 1 and not greater than M, representing the total number of output terminals programmed to be turned on simultaneously each time. In Figure 23 the example, it is illustrated that each group of every three output terminals among the second plurality of (for example, M) output terminals {OUT(j), j = 1, 2,..., M} can be programmed to be turned on simultaneously each time, for example, in every three working cycles or every three charging pulses of the charging control PWM signal PWM_C, that is, M = 3 in this example. However, this does not mean a limitation. Those of ordinary skill in the art should understand that the variable T can be set to other values according to actual application needs, such as 4 or 5, etc.

[0157] To help understand the parallel output mode, reference will be made to Figure 23An exemplary illustration with T = 3 will be described. In the parallel output mode, at the start of each charging pulse of the charging control PWM signal PWM_C, the charging unit 102 can check the logic states of a plurality of (e.g., K) selection control signals {SEL_C(q), q = 0, 1,..., K - 1} and determine, according to Equation (1), which of the second plurality of (e.g., M) output terminals {OUT(j), j = 1, 2,..., M} or the second plurality of (e.g., M) charge path control circuits {104(j), j = 1, 2,..., M} will be programmed to be simultaneously turned on in parallel among the current T groups (e.g., T = 3) of output terminals. That is, at the start of each charging pulse of the charging control PWM signal PWM_C, the s-th output terminal OUT(s) or the s-th charge path control circuit 104(s) programmed according to Formula (1) will be among the output terminals of the current T groups (e.g., T = 3) to be simultaneously turned on in parallel and recorded. After all the current T groups (e.g., T = 3) of output terminals are recorded, the recorded current T groups (e.g., T = 3) of output terminals can be used, according to every T charging pulses of the charging pulse charging control PWM signal PWM_C (e.g., the 3 charging pulses of the first group are the 1st - 3rd charging pulses, the 3 charging pulses of the second group are the 4th - 6th charging pulses, the 3 charging pulses of the third group are the 6th - 9th charging pulses, and so on), in a manner similar to that described in the example with reference to Figures 12 to 16 to control the programmed s-th output terminal OUT(s) and the s-th charge path control circuit 104(s). Those of ordinary skill in the art can clearly and easily understand this by combining the illustrations in Figure 23 and there is no need to repeat it in detail here again.

[0158] From Figure 23 the example, it can be seen that at the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} respectively provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {0, 0, 0, 0, 0}, which means s = 1 + 0 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4= 1. Therefore, in this example, the first output terminal OUT(1) is programmed as one of the current T-group (e.g., T = 3) output terminals and is simultaneously and parallely turned on and recorded during the first charging pulse. During the second charging pulse of the charging control PWM signal PWM_C, the logical states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {1, 0, 0, 0, 0} respectively, which means s = 1 + 1 * 2 0 + 0 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 2. Therefore, in this example, the second output terminal OUT(2) is programmed as one of the current T-group (e.g., T = 3) output terminals and is simultaneously and parallely turned on and recorded during the second charging pulse. During the third charging pulse of the charging control PWM signal PWM_C, the logical states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {0, 1, 0, 0, 0} respectively, which means s = 1 + 0 * 2 0 + 1 * 2 1 + 0 * 2 2 + 0 * 2 3 + 0 * 2 4 = 2. Therefore, in this example, the third output terminal OUT(3) is programmed as one of the current T-group (e.g., T = 3) output terminals and is simultaneously and parallely turned on and recorded during the third charging pulse.

[0159] During the third charging pulse of the charging control PWM signal PWM_C, all the output terminals OUT(1), OUT(2) and OUT(3) programmed as the current T (e.g., T = 3) group are recorded, and thus are simultaneously and parallely turned on during the charging time window T cg (1) / T cg (2) / T cg (3). It should be understood that in this case, the charging time window T cg (1) of the relevant output terminal OUT(1), the charging time window T cg (2) of the relevant output terminal OUT(2) and the charging time window T cg(3) is the same and coincides with each other. Then, during the charging time window T cg (1) / T cg (2) / T cg (3) After the end, the discharging unit 106 can be configured to absorb or release energy from the output terminals OUT(1), OUT(2), and OUT(3) of the integrated semiconductor laser 101 to the reference ground GND simultaneously and in parallel during the discharging time window T dg (1) / T dg (2) / T dg (3). Similarly, in the next three charging pulses, that is, the 4th, 5th, and 6th charging pulses of the charging control PWM signal PWM_C, the 4th output terminal OUT(4), the 5th output terminal OUT(5), and the 6th output terminal OUT(6) are programmed and recorded according to the selection control signal {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} respectively as the next group of T (for example, T = 3) output terminals to be turned on simultaneously and in parallel. Therefore, in this example, at the 6th charging pulse of the charging control PWM signal PWM_C, all the next group of T (for example, T = 3) programmed output terminals OUT(4), OUT(5), and OUT(6) are recorded, so that during the charging time window T

[0160] after the 6th charging pulse cg (4) / T cg (5) / T cg (6) they are turned on simultaneously and in parallel. It should be understood that in this case, the charging time window T cg (4) of the relevant output terminal OUT(4), the charging time window T cg (5) of the relevant output terminal OUT(5), and the charging time window T cg (6) of the relevant output terminal OUT(6) are the same and coincide with each other. Then, during the charging time window T cg (4) / T cg (5) / T cg (6) After the end, the discharging unit 106 can be configured to absorb or release energy from the output terminals OUT(4), OUT(5), and OUT(6) of the integrated semiconductor laser 101 to the reference ground GND simultaneously and in parallel during the discharging time window T dg (4) / T dg (5) / T dg (6). A similar description applies to the rest of each group of T (for example, T = 3) programmed output terminals, which will be turned on simultaneously and in parallel and discharged simultaneously and in parallel.

[0161] The advantages of the various embodiments of the present disclosure are not limited to the above description. These and other advantages will become more apparent upon reading the complete detailed description and studying the various figures of the drawings.

[0162] As can be seen from the above, the specific embodiments of the present disclosure are described herein for illustrative purposes and various modifications can be made without departing from the technology. Many elements in one embodiment can be combined with or replace elements in other embodiments. Therefore, the present invention is only limited by the appended claims.

Claims

1. A charging unit for driving an integrated semiconductor laser, comprising: a first input terminal configured to receive input drive energy; a second input terminal configured to enable or disable the charging unit; A third input terminal configured to receive a charging control PWM signal; as well as a second plurality of output terminals; in The charging unit is configured to turn on or off the second plurality of output terminals in a predetermined pattern according to the charging control PWM signal PWM_C.

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