Semiconductor device, method for manufacturing semiconductor device, and power conversion device

Abstract

The purpose of the present disclosure is to suppress warpage of a semiconductor wafer caused by impurity ion implantation for forming a channel formation layer in contact with a sidewall of a trench. A semiconductor device (101) is provided with a drift layer, a P-type underlayer (16), an N-type source layer (15), and a gate electrode (13). The underlayer (16) is formed on a part of the surface layer of the drift layer (14). The source layer (15) is formed on a part of the surface layer of the base layer (16). A gate electrode (13) is provided in a plurality of trenches (10) penetrating a source layer (15) and an underlayer (16) via a gate insulating film (17). The source layer (15) formed between the plurality of trenches (10) is shallower as the source layer (15) is farther away from the sidewalls of the plurality of trenches (10), and the impurity concentration is lower.

Description

Technical Field

[0001] The present disclosure relates to a technique for suppressing warping of a semiconductor wafer caused by impurity ion implantation. Background Art

[0002] A semiconductor device for electric power, commonly called a power device, is used for a switching element that controls power supply to a motor load or the like. The power device requires several performances, and one of the greatest requirements among them can be cited as reduction of power loss. Reduction of power loss in the power device has effects such as miniaturization and light weight of the device, and in a broad sense, has an effect of contributing to the global environment due to reduction of energy consumption. In addition, it is required to achieve these characteristics at as low a cost as possible.

[0003] As a semiconductor element for electric power that satisfies these requirements, insulated gate type semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are widely used.

[0004] Conventionally, as a method for reducing power loss of an insulated gate type semiconductor device, there is a method of increasing the channel density, and as one of the structures corresponding to this method, a structure called a trench type has been proposed (for example, Patent Document 1).

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-117016

[0006] In a trench type MOSFET, in order to reduce the on-resistance, a narrow pitch is realized, and thus a structure in which an interlayer insulating film is buried inside the trench is considered. However, in order to bury the interlayer insulating film inside the trench, it is necessary to form the trench deeper than before corresponding to the depth of the interlayer insulating film inside the trench. Accordingly, the source layer as a channel formation layer also needs to be formed deeper, and thus it is necessary to increase the ion implantation energy for forming the source layer. As a result, there is a problem that the warping of the semiconductor wafer becomes larger after ion implantation. Summary of the Invention

[0007] The present disclosure has been made to solve the above problems, and an object thereof is to suppress warping of a semiconductor wafer caused by impurity ion implantation for forming a channel formation layer in contact with a trench side wall.

[0008] The semiconductor device of the present disclosure includes a drift layer, a base layer of a second conductivity type, a channel formation layer of a first conductivity type, and a gate electrode. The base layer is formed on a part of the surface layer of the drift layer. The channel formation layer is formed on a part of the surface layer of the base layer. The gate electrode is disposed via a gate insulating film in a plurality of trenches that penetrate the channel formation layer and the base layer. The channel formation layer formed between the plurality of trenches becomes shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches.

[0009] The semiconductor device of the present disclosure includes a channel formation layer that becomes shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches. Such a channel formation layer can be formed with a lower implantation energy by performing ion implantation from an inclined direction with respect to the side walls of the trenches. Therefore, warping of the semiconductor after ion implantation for forming the channel formation layer can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a top view of the semiconductor device of Embodiment 1.

[0011] Figure 2 is a top view showing a main silicon carbide semiconductor portion of the semiconductor device of Embodiment 1.

[0012] Figure 3 is Figure 2 an enlarged view of region R1 of

[0013] Figure 4 is a cross-sectional view taken along line A-A of Figure 3

[0014] Figure 5 is Figure 4 an enlarged view of region R2 of

[0015] Figure 6 is a flowchart showing the manufacturing process of the semiconductor device of Embodiment 1.

[0016] Figure 7 is a cross-sectional view showing a state in which a drift layer is formed on a semiconductor substrate.

[0017] Figure 8 is a cross-sectional view showing a state in which a base layer is formed on the surface layer of the drift layer.

[0018] Figure 9 is a cross-sectional view showing a state in which trenches are formed that penetrate the base layer and reach the drift layer.

[0019] Figure 10 is a cross-sectional view showing a state in which a source layer is formed on the surface layer of the base layer and the side walls of the trenches by inclined ion implantation.

[0020] Figure 11 ​It is a cross-sectional view showing a situation where the depth of the source layer is adjusted according to the thickness of the oxide film mask.

[0021] Figure 12 It is a cross-sectional view showing a situation where the depth of the source layer is adjusted according to the etching amount of the SiC surface.

[0022] Figure 13 It is a cross-sectional view showing a manufacturing method of a semiconductor device of a comparative example.

[0023] Figure 14 It is a cross-sectional view showing a manufacturing method of a semiconductor device of a comparative example.

[0024] Figure 15 It is a diagram for comparing the warpage amount of a semiconductor wafer between a comparative example and the present embodiment.

[0025] Figure 16 It is a cross-sectional view of a semiconductor device of Embodiment 2.

[0026] Figure 17 It is a flowchart showing a manufacturing process of a semiconductor device of Embodiment 2.

[0027] Figure 18 It is a block diagram showing the structure of a power conversion system of Embodiment 3.

[0028] Explanation of reference numerals: 4... trench gate; 10... trench; 12... drain electrode; 13... gate electrode; 14... drift layer; 15... source layer; 16... base layer; 17... gate insulating film; 18... semiconductor substrate; 19... interlayer insulating film; 20... electric field relaxation layer; 21... oxide film mask; 22... well layer; 23... mesa region; 31... terminal well region; 37... JTE region; 80... source electrode; 81... gate pad; 82... gate wiring; 100... power supply; 101, 102... semiconductor devices; 200... power conversion device; 201... main conversion circuit; 202... drive circuit; 203... control circuit; 300... load. Detailed Description of the Invention

[0029] In the following description, the first conductivity type is set to n-type and the second conductivity type is set to p-type, but conversely, the first conductivity type may be set to p-type and the second conductivity type may be set to n-type.

[0030] <A. Embodiment 1>

[0031] <A-1. Structure>

[0032] Figure 1FIG. 0 is a top view of the semiconductor device 101 of Embodiment 1 as viewed from the upper surface. Hereinafter, the semiconductor device 101 will be described as a MOSFET, but the semiconductor device 101 may also be other switching elements such as an IGBT. The semiconductor substrate may be a normal semiconductor wafer, an epitaxial growth layer, or a combination thereof. In addition, the semiconductor device 101 is formed using a semiconductor substrate made of silicon carbide (SiC). However, the material of the semiconductor substrate is not limited to silicon carbide, and may also be silicon (Si), gallium nitride (GaN)-based materials, gallium oxide, diamond, or other wide-bandgap semiconductors. In addition, in Figure 1 for convenience, illustrations of the gate insulating film, field insulating film, interlayer insulating film, gate electrode, and protective film in the structure of the upper surface of the semiconductor device 101 are omitted.

[0033] Figure 1 In FIG., a gate pad 81 is formed on a part of the upper surface of the semiconductor device 101, and a source electrode 80 is formed adjacent thereto. In addition, a gate wiring 82 is formed so as to extend from the gate pad 81. In addition, the gate pad 81 may be provided at any part of the upper surface of the semiconductor device 101, for example, it may be provided at the central part. In addition, control pads other than the gate pad 81 may be provided on the upper surface of the semiconductor device 101. Control pads other than the gate pad 81 include, for example, at least any one of a current sensing pad, a Kelvin source pad, and a temperature sensing diode pad.

[0034] Next, the current sensing pad, the Kelvin source pad, and the temperature sensing diode pad will be described. The current sensing pad is a control pad for detecting the current flowing in the cell region of the semiconductor device 101. The current sensing pad is electrically connected to the cell region of the semiconductor device 101, and when a current flows in the cell region, a current of one fraction to one ten-thousandth of the current flowing in the entire cell region flows to the current sensing pad. The Kelvin source pad is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor device 101 is applied.

[0035] The temperature sensing diode pad is a control pad electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 101. The voltage between the anode and cathode of the temperature sensing diode provided in the cell region is measured via the temperature sensing diode pad, and the temperature of the semiconductor device 101 is measured based on this voltage. In addition, control pads other than the gate pad 81 may be provided at any part of the upper surface of the semiconductor device 101, for example, they may be provided at the end or the central part.

[0036] Figure 2 FIG. 16 is a top view showing the main silicon carbide semiconductor part of the semiconductor device 101. Figure 2In [the semiconductor device], unit cell regions each composed of a p-type base layer 16 and a trench gate 4 having a trench-type gate electrode are arranged in a stripe pattern. In other words, the unit cell regions are repeatedly arranged in one direction when viewed from above. A semiconductor device 101 having such an arrangement of unit cell regions is called a stripe type. In addition, the arrangement of the unit cell regions of the semiconductor device 101 is not limited to the stripe type, and may be other arrangements such as a lattice shape or a hexagonal shape.

[0037] In addition, a trench source having a trench-type source electrode may be alternately provided with the trench gate 4. The trench gate 4 and the trench source are collectively referred to as an active trench. A region in which unit cell regions constituting a MOSFET are repeatedly arranged is called an active region, and a region formed on the outer periphery of the active region is called a terminal region. The terminal region includes a p-type terminal well region 31, a JTE region 37 for maintaining a breakdown voltage, and a gate pad 81.

[0038] In addition, an FLR (Field Limiting Ring) may be provided instead of the JTE region 37. Further, a structure combining the JTE region 37 and the FLR may be employed.

[0039] The impurity concentration of the JTE region 37 selectively provided in the terminal well region 31 is lower than the impurity concentration of the terminal well region 31. Although not shown, a terminal trench may be provided in the terminal region, and the terminal well region 31 and the JTE region 37 may be provided at the bottom of the terminal trench. The depth of the terminal trench may be the same as the depth of the trench of the trench gate 4, or may be greater than that. A gate wiring 82 may be provided on the terminal region. The source contact hole of the source electrode 80 may not be provided on the terminal region side at the end of the trench gate 4. That is, the source contact hole may not be provided in a region where the terminal well region 31 and the JTE region 37 are provided below the terminal trench.

[0040] Figure 3 is Figure 2 an enlarged view of the region R1 of Figure 4 is a cross-sectional view taken along the Figure 3 line A-A of Figure 5 is Figure 4 an enlarged view of the region R2 of Figure 3 As shown in

[0041] As shown in Figure 4 the semiconductor device 101 includes a semiconductor substrate 18, a drift layer 14, a base layer 16, a source layer 15, a gate insulating film 17, a gate electrode 13, an interlayer insulating film 19, a source electrode 80, and a drain electrode 12.

[0042] An n-type drift layer 14 is formed on a semiconductor substrate 18. A p-type base layer 16 is formed on the surface layer of the drift layer 14 on the side opposite to the semiconductor substrate 18. N-type source layers 15 are discretely formed on the surface layer of the base layer 16 on the side opposite to the semiconductor substrate 18. The source layer 15 is also referred to as a channel formation layer. The region in the surface layer of the base layer 16 where the source layer 15 is not formed becomes a contact region.

[0043] A source electrode 80 is formed on the base layer 16, the source layer 15, and an interlayer insulating film 19 described later. In addition, a drain electrode 12 is formed on the side of the semiconductor substrate 18 opposite to the drift layer 14.

[0044] A plurality of trenches 10 are formed that penetrate the source layer 15 and the base layer 16 and reach the drift layer 14. The region between the plurality of trenches 10 is a mesa region 23. The base layer 16 and the source layer 15 are formed in the mesa region 23. Preferably, on the surface of the mesa region 23, the area of the contact region is smaller than the area of the source layer 15.

[0045] A gate insulating film 17, a gate electrode 13, and an interlayer insulating film 19 are buried in the trench 10. The gate insulating film 17 is formed on the side surface and the bottom surface of the trench 10. The gate electrode 13 is formed on the gate insulating film 17. Thus, the gate electrode 13 faces the base layer 16 via the gate insulating film 17.

[0046] In addition, a p-type electric field relaxation layer 20 is formed directly below the trench 10. By providing the electric field relaxation layer directly below the trench 10 that becomes the trench gate 4, the electric field applied to the gate insulating film 17 at the bottom of the trench 10 is relaxed, and the dielectric breakdown of the gate insulating film 17 during high voltage application is suppressed. In addition, providing the electric field relaxation layer 20 directly below all the trenches 10 has a better effect than providing the electric field relaxation layer 20 directly below only a part of the trenches 10. Especially in a trench-type MOSFET using silicon carbide that requires operation at a higher voltage than Si, providing the electric field relaxation layer 20 is effective in suppressing the dielectric breakdown of the gate insulating film 17. In addition, the electric field relaxation layer 20 can also be electrically connected to the source electrode 80 via the base layer 16. In this case, a connection layer of a second conductivity type that connects the electric field relaxation layer 20 and the base layer 16 can be provided in a part of the mesa region 23. Preferably, this connection layer is disposed directly below the contact region. It is also possible that the electric field relaxation layer 20 extends in the same direction as the extension direction of the trench 10 ( Figure 3 in the second direction D2), and is alternately provided with the drift layer 14 or an additional n-type column layer to form a superstructure. In addition, the peak concentration of impurities in the n-type column layer can also be higher than that of the drift layer 14.

[0047] <A-2. Manufacturing method>

[0048] Figure 6 This is a flowchart showing the manufacturing process of the semiconductor device 101 of Embodiment 1. Hereinafter, the manufacturing method of the semiconductor device 101 will be described according to Figure 6 the following process.

[0049] First, in step S101, on a semiconductor substrate 18 made of n-type and low-resistance silicon carbide and having a 4H polytype, a drift layer 14 made of silicon carbide is epitaxially grown by chemical vapor deposition (CVD method). Figure 7 This state is shown. The plane orientation of the main surface of the semiconductor substrate 18 on which the drift layer 14 is epitaxially grown is a (0001) plane with an inclination angle. The impurity concentration of the drift layer 14 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less. The thickness of the drift layer 14 is 5 μm or more and 50 μm or less.

[0050] Next, in step S102, a base layer 16 is formed on the drift layer 14. The process of this step is also called the base layer formation process. Specifically, Al, which is a p-type impurity, is ion-implanted into the surface of the drift layer 14. At this time, the depth of the Al ion implantation becomes about 0.5 μm or more and 10 μm or less that does not exceed the thickness of the drift layer 14. In addition, the impurity concentration of the ion-implanted Al is higher than that of the drift layer in the range of 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The region where Al ions are implanted by this process becomes the base layer 16 of the active region and the terminal well region 31 of the terminal region. Figure 8 This state is shown.

[0051] In addition, the base layer 16 can also be formed on the drift layer 14 by an epitaxial method. Further, it is also possible to form an implantation mask on the base layer 16 except for a predetermined place by a photoresist or the like, and ion-implant Al with an impurity concentration in the range of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less, which is higher than the impurity concentration of the base layer 16, and then remove the implantation mask. It is also possible that the p-type region in the region where Al is ion-implanted by this process is activated by a heat treatment described later, and thus becomes a p+-type contact layer.

[0052] Next, in step S103, a trench 10 that penetrates the base layer 16 and reaches the drift layer 14 is formed by dry etching. The process of this step is also referred to as the trench formation process. Figure 9 This state is shown. Specifically, an etching mask is deposited on the base layer 16 with a thickness of about 1 μm or more and 5 μm or less, and a resist mask made of a resist material is formed thereon. The resist mask is formed into a pattern of the formation region of the trench 10 by photolithography. When the trench 10 is stripe-shaped, the resist mask becomes a stripe-shaped pattern that is inverted. Then, through reactive ion etching (RIE: Reactive Ion Etching) using the resist mask as a mask, the trench 10 that penetrates the base layer 16 is formed.

[0053] The depth of the trench 10 is greater than the depth of the base layer 16 and is about 0.5 μm or more and 3 μm or less. In addition, when the trench 10 is formed, a terminal trench may be formed at the same time. Further, when the main surface plane orientation of the semiconductor substrate 18 on which the drift layer 14 is epitaxially grown is a (0001) plane having a tilt angle in the <11 - 20> direction, the trench 10 may be formed parallel to the <11 - 20> direction. In this way, the threshold voltage of the MOSFET of the trench gate 4 is not affected by the offset direction of the semiconductor substrate 18, and thus the non-uniformity of the threshold voltage of the MOSFET is reduced.

[0054] Next, in step S104A, ions of an n-type impurity such as nitrogen (N) are implanted from an inclined direction having an angle θ with respect to the sidewall of the trench 10. The ion implantation from such an inclined direction is referred to as inclined ion implantation. The process of this step is also referred to as the first inclined implantation process. Figure 10 This state is shown. The desired implantation energy is 10 keV or more and 150 keV or less. If the implantation energy exceeds 150 keV, the semiconductor wafer is likely to warp, and particularly if it exceeds 600 keV, it is more likely to warp.

[0055] The impurity concentration of the ions implanted in this process is 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The region indicating n-type in the region where the impurities are implanted in this process becomes the source layer 15. Through inclined ion implantation, the source layer 15 is formed on a part of the surface layer of the base layer 16 and the sidewall of the trench 10. Therefore, the source layer 15 becomes deeper as it goes from the central side of the mesa region 23 toward the sidewall of the trench 10. Thereby, a deeper source layer 15 can be formed at the portion in contact with the sidewall of the trench 10 with a smaller implantation energy. Therefore, the warping of the semiconductor wafer after ion implantation is suppressed.

[0056] Hereinafter, the angle θ formed by the ion implantation direction with respect to the sidewall of the trench 10 is referred to as the ion implantation angle θ. The relationship among the ion implantation angle θ, the width d of the trench 10, and the depth h of the source layer 15 in contact with the sidewall of the trench 10 is expressed by the following formula (1).

[0057] Formula (1)

[0058] d / h = tanθ …(1)

[0059] As can be seen from formula (1), if the ion implantation angle θ is constant for all the trenches 10 but the trench widths d are not consistent, the depth h of the source layer 15 will also be inconsistent. The depth h of the source layer 15 is the channel length Lch. Therefore, if the trench widths d are not consistent, the channel lengths Lch will be inconsistent. When arbitrarily selecting two trenches 10 from multiple trenches 10, setting the width of the first trench 10 as d1 and the width of the second trench 10 as d2, from the viewpoint of suppressing the inconsistency of the channel length Lch, it is desirable that d2 / d1 be 0.8 or more and 1.2 or less.

[0060] The ion implantation angle θ only needs to be greater than 0° and 70° or less. If the ion implantation angle θ exceeds 70°, a shadow is formed due to the upper corner of the trench 10, and thus the influence of the shadow that limits the irradiation range becomes large, so it is not preferred. In addition, it is also possible that through inclined implantation, the impurity concentration of the source layer 15 becomes lower as it goes from the sidewall side of the trench 10 toward the center side of the mesa region 23. By forming the source layer 15 in a direction different from the thickness direction of the semiconductor substrate 18, the warping of the semiconductor wafer is suppressed.

[0061] Hereinafter, three methods for suppressing the inconsistency of the channel length Lch will be further described. The first method is a method of adjusting the ion implantation angle θ in accordance with the width d of the trench 10. As described above, for the widths d1 and d2 of the two trenches 10, d2 / d1 is 0.8 or more and 1.2 or less. Let the ion implantation angle θ with respect to the trench 10 having the width d1 be θ1, and let the depth h of the source layer 15 formed adjacent to this trench 10 be h1. In addition, let the ion implantation angle θ with respect to the trench 10 having the width d2 be θ2, and let the depth h of the source layer 15 formed adjacent to this trench 10 be h2. Formula (1) is transformed to obtain the following formula (2).

[0062] Formula (2)

[0063]

[0064] In order to reduce the non-uniformity of the depth h of the source layer 15, that is, to make h2 / h1 = 1, it is sufficient to vary θ2 in such a way that tanθ2 / tanθ1 = d2 / d1 to match the variation in the non-uniformity of the width d of the trench 10, i.e., d2 / d1.

[0065] The second method is a method of adjusting the thickness of the oxide film mask during inclined ion implantation in accordance with the non-uniformity of the width d of the trench 10. In this method, after the base layer 16 is formed on the surface layer of the drift layer 14 and before the trench 10 is formed, the source layer 15 is formed on the surface layer of the base layer 16 by ion implantation using a mask. This process is also referred to as the ion implantation process. Thereafter, an oxide film mask 21 is formed on the source layer 15, and the trench 10 penetrating the base layer 16 is formed by dry etching using the oxide film mask 21.

[0066] Next, the thickness of the oxide film mask 21 is adjusted to Δh. This process is also referred to as the mask thickness adjustment process.

[0067] Thereafter, in a state where the oxide film mask 21 having a thickness of Δh remains, inclined ion implantation is performed at an implantation angle θ with respect to the side wall of the trench 10, and the source layer 15 is formed on the side wall of the trench 10. Figure 11 This state is shown. In addition, Figure 11 in, the illustration of the semiconductor substrate 18 is omitted, and this is the same in the Figure 12 following cross-sectional views. If inclined ion implantation is performed in a state where the oxide film mask 21 having a thickness of Δh remains, the depth h of the source layer 15 becomes smaller by only Δh compared to the inclined ion implantation without the oxide film mask 21. Therefore, it is possible to adjust the depth h of the source layer 15 by how much thickness of the oxide film mask 21 remains in the mask thickness adjustment process. That is, the thickness of the oxide film mask 21 adjusted in the mask thickness adjustment process is determined according to the width of the trench 10 adjacent to the oxide film mask 21. For example, when the width d of the trench 10 is larger than the reference value, the remaining thickness of the oxide film mask 21 is increased correspondingly, thereby suppressing the non-uniformity of the depth h of the source layer 15.

[0068] The third method is a method of adjusting the etching amount of the SiC surface before inclined ion implantation according to the width d of the trench 10. First, the base layer 16 is formed on the drift layer 14. Next, using an implantation mask, ion implantation is performed on the surface layer of the base layer 16 to form the source layer 15. Thereafter, the trench 10 penetrating the source layer 15 and the base layer 16 is formed by dry etching. Next, the following etching process is performed: the surface layer of the source layer 15, i.e., the SiC surface, is etched by only Δh to reduce the depth of the trench 10. The etching amount Δh of the source layer 15 is determined according to the width d of the trench 10 adjacent to the source layer 15.

[0069] Thereafter, a source layer 15 is formed on the sidewalls of the trench 10 by inclined ion implantation. Figure 12 This state is shown. The relationship between the width d of the trench and the depth of the source layer 15 is as shown in formula (1). Therefore, when there is a discrepancy in the width d of the trench, by adjusting the etching amount Δh of the SiC surface, the depth of the source layer 15 can be adjusted. If the etching amount of the SiC surface is Δh, the depth of the source layer 15 increases by Δh, and the discrepancy in the depth of the source layer 15 can be reduced.

[0070] After introducing various impurities by ion implantation as described above, an annealing process is performed in step S105 to diffuse and activate the impurities in the base layer 16, the source layer 15, etc. For example, using a heat treatment apparatus, the semiconductor substrate is annealed at a temperature of 1300°C to 1900°C for 30 seconds to 1 hour in an inert gas environment such as argon (Ar) gas. By this annealing, impurities such as N and Al implanted by ion implantation are made electroactive. In this embodiment, heat treatment is performed after all the impurities are implanted, but it is not limited thereto. For example, the implantation of impurities and the heat treatment for diffusion and activation can also be performed alternately.

[0071] Next, in step S106, an insulating film (not shown) serving as a field insulating film is formed on the surface side of the semiconductor substrate 18. The insulating film can be formed by thermal oxidation or the like, or can be formed by a deposition method. The thickness of the insulating film is determined in consideration of reduction during cleaning and etching processes in subsequent steps. For example, using the CVD method, photolithography technology, etc., a field insulating film made of silicon oxide is formed on regions other than the active region corresponding to the base layer (for example, the region of the gate pad, the region of the sense pad, the terminal region, etc.). The film thickness of the field insulating film is, for example, 0.5 μm to 2 μm, which is larger than the film thickness of the gate insulating film 17 described below.

[0072] Thereafter, in step S107, the trench 10 not covered by the field insulating film is thermally oxidized, and a silicon oxide film having a desired thickness is formed as the gate insulating film 17 on the inner sidewalls and bottom surface of the trench. In addition, the formation method and material of the gate insulating film 17 are not limited thereto. Thereafter, a conductive polysilicon film is formed on the gate insulating film 17 and the field insulating film by low-pressure CVD method, and it is patterned, whereby the gate electrode 13 is formed inside the trench 10. In addition, the formation method and material of the gate electrode 13 are not limited thereto.

[0073] Next, in step S108, by means of reduced-pressure CVD, an insulating film having a film thickness greater than that of the gate insulating film 17 and made of silicon oxide is formed as the interlayer insulating film 19 on the surface side of the semiconductor substrate 18. The interlayer insulating film may also be BPSG (Boro-Phospho Silicate Glass) containing B (boron) or P (phosphorus), or a stacked film of BPSG and impurity-free silicon oxide. Next, the deposited interlayer insulating film 19 is etched. As a result, the interlayer insulating film 19 remains on the gate electrode 13 formed in the trench 10 and does not remain on the mesa region 23 around the trench 10.

[0074] Next, in step S109, a silicide layer is formed over the entire surface side of the semiconductor substrate 18. Specifically, over the entire surface side of the semiconductor substrate 18, for example, by means of sputtering or the like, a metal film mainly composed of Ni (for example, Ni film) is formed. Thereafter, heat treatment is performed at a temperature of 600°C to 1100°C to cause the metal film mainly composed of Ni to react with the SiC-exposed semiconductor substrate without an insulating film, and a silicide layer is formed therebetween.

[0075] Thereafter, in step S110, the metal film mainly composed of Ni remaining on the interlayer insulating film 19 and the like is removed by wet etching using peroxydisulfuric acid or the like to form ohmic electrodes.

[0076] Then, in step S111, over the entire surface side of the semiconductor substrate 18, for example, a metal film containing Al or AlSi is formed by sputtering or the like, a mask having a mask pattern is formed using photolithography technology, and the deposited metal film is etched. As a result, a gate pad 81 and a gate wiring 82 that are in contact with the gate electrode, source electrodes, and various pads are formed.

[0077] Next, in step S112, a first metal film and a second metal film are formed. Specifically, an unillustrated polyimide film is formed on the source electrode 80, a mask having a mask pattern is formed using photolithography technology, and the polyimide film is etched. Then, a chemical plating film containing Ni or a Ni compound is formed as the first metal film on the source electrode 80 where the polyimide film is not provided. Finally, a chemical plating film containing Au for antioxidation of the first metal film is formed as the second metal film on the first metal film. In addition, the first metal film and the second metal film may also be formed by sputtering or the like instead of by chemical plating.

[0078] Thereafter, in step S113, in the same manner as the formation of the source electrode 80, a metal film containing Ni or Au is formed over the entire back side of the semiconductor substrate 18 by sputtering or the like, and a drain electrode 12 is formed.

[0079] <A-3. Comparative Example>

[0080] Figure 13 and Figure 14 is a cross-sectional view of a method for manufacturing a semiconductor device representing a comparative example. According to the manufacturing method of the comparative example, a drift layer 14 is formed on a semiconductor substrate 18. Further, a base layer 16 is formed on the surface layer of the drift layer 14 on the side opposite to the semiconductor substrate 18. Thereafter, as Figure 13 shown, N ions are implanted into the surface layer of the base layer 16 on the side opposite to the drift layer 14 to form a source layer 15.

[0081] Next, as Figure 14 shown, a trench 10 is formed that penetrates the source layer 15 and the base layer 16 from the upper surface of the source layer 15 and reaches the drift layer 14.

[0082] In the comparative example, the direction of ion implantation for forming the source layer 15 is the thickness direction of the semiconductor substrate 18, that is, the direction perpendicular to the main surface of the semiconductor substrate 18. Therefore, it is impossible to suppress the implantation region of the source layer 15 in the thickness direction of the semiconductor substrate 18. As a result, after ion implantation for forming the source layer 15, the semiconductor wafer warps.

[0083] Figure 15 is a diagram comparing the warpage amounts of semiconductor wafers before and after ion implantation for forming the source layer 15 in the manufacturing methods of the semiconductor devices of the comparative example and the present embodiment.

[0084] Figure 15 The circles in Figure 15 indicate the warpage amounts of semiconductor wafers produced by the manufacturing method of the comparative example, and the square marks indicate the warpage amounts of semiconductor wafers produced by the manufacturing method of the present embodiment. According to

[0085] <A-4. Effects>

[0086] As described above, the semiconductor device 101 of Embodiment 1 includes a drift layer 14, a base layer 16 of a second conductivity type, a channel formation layer of a first conductivity type, and a gate electrode 13. The base layer 16 is formed on a part of the surface layer of the drift layer 14. The channel formation layer is formed on a part of the surface layer of the base layer 16. The gate electrode 13 is provided via an insulating film in a plurality of trenches 10 that penetrate the channel formation layer and the base layer 16. The channel formation layer formed between the plurality of trenches 10 becomes shallower and has a lower impurity concentration as it is farther from the sidewalls of the plurality of trenches 10. Such a channel formation layer can be formed with a lower implantation energy by performing ion implantation from an inclined direction with respect to the sidewalls of the trenches 10. Therefore, warping of the semiconductor wafer can be suppressed after ion implantation for forming the channel formation layer. In addition, since warping of the semiconductor wafer can be suppressed and the channel formation layer can be formed to a deeper position, the thickness of the interlayer insulating film 19 buried in the trenches 10 can be increased. Therefore, the margin for the difference in depth between the interlayer insulating film 19 and the gate electrode 13 in the trenches 10 can be increased, and the reliability is improved.

[0087] In addition, the manufacturing method of the semiconductor device 101 of Embodiment 1 includes a base layer formation process, a trench formation process, and a first inclined implantation process. In the base layer formation process, impurity ions are implanted into the drift layer 14 to form a base layer 16 of a second conductivity type on the surface layer of the drift layer 14. In the trench formation process, a plurality of trenches 10 that penetrate the base layer 16 are formed. In the first inclined implantation process, impurity ions are implanted from an inclined direction at an angle θ with respect to the sidewalls of the plurality of trenches 10 to form a channel formation layer of a first conductivity type on the surface layer of the base layer 16. In the first inclined implantation process, since the channel formation layer is formed on the sidewalls of the trenches 10, the channel formation layer can be formed deeper even with a lower implantation energy. Therefore, warping of the semiconductor wafer after the first inclined implantation process can be suppressed. In addition, since warping of the semiconductor wafer can be suppressed and the channel formation layer can be formed to a deeper position, the thickness of the interlayer insulating film 19 buried in the trenches 10 can be increased. Therefore, the margin for the difference in depth between the interlayer insulating film 19 and the gate electrode 13 in the trenches 10 can be increased, and the reliability is improved.

[0088] <B. Embodiment 2>

[0089] Figure 16 FIG. is a cross-sectional view schematically showing the structure of the semiconductor device 102 of Embodiment 2. The semiconductor device 102 is different from the semiconductor device 101 of Embodiment 1 in that a P-type well layer 22 is provided in a region below the source layer 15 along the sidewalls of the trenches 10. The well layer 22 is also referred to as a well layer. The well layer 22 is adjacent to the source layer 15 from below and contacts the sidewalls of the trenches 10.

[0090] Figure 17It is a flowchart showing the manufacturing process of the semiconductor device 102. In the manufacturing method of the semiconductor device 102, after the tilted implantation of N ions for forming the source layer 15 (step S104A), the tilted implantation of Al ions for forming the well layer 22 is performed (step S104B). This tilted implantation process of Al ions is also referred to as the second tilted implantation process.

[0091] In the semiconductor device 101 of Embodiment 1 that does not have the well layer 22, if the width d of the trench 10 is inconsistent due to manufacturing errors or other reasons, when the ion implantation angle θ is the same, the depth h of the source layer 15 is inconsistent, and the channel length Lch is also inconsistent. However, in the semiconductor device 102 having the well layer 22 formed by the second ion implantation, the channel length Lch is fixed. Therefore, variations in electrical characteristics caused by inconsistencies in the channel length Lch are suppressed, and higher reliability is obtained.

[0092] <C. Embodiment 3>

[0093] This embodiment is a mode in which the semiconductor devices 101 and 102 of any of the above Embodiments 1 and 2 are applied to a power conversion device. The semiconductor devices 101 and 102 are not limited to applications to specific power conversion devices. Hereinafter, as Embodiment 3, the case where the semiconductor devices 101 and 102 are applied to a three-phase inverter will be described.

[0094] Figure 18 It is a block diagram showing the structure of a power conversion system of a power conversion device 200 to which this embodiment is applied. Figure 18 The power conversion system shown is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply that supplies DC power to the power conversion device 200. The power supply 100 can be configured in various structures. For example, the power supply 100 can also be composed of a DC system, a solar cell, or a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into predetermined power.

[0095] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power conversion device 200 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As Figure 18As shown, the power conversion device 200 includes a main conversion circuit 201, a drive circuit 202, and a control circuit 203. The main conversion circuit 201 converts DC power into AC power and outputs it. The drive circuit 202 outputs drive signals for driving the respective switching elements of the main conversion circuit 201. The control circuit 203 outputs control signals for controlling the drive circuit 202 to the drive circuit 202.

[0096] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. In addition, the load 300 is not limited to a specific use and is a motor mounted on various electrical devices, such as a motor for a hybrid electric vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioning device.

[0097] Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 of the present embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel with the respective switching elements. The above-described semiconductor devices 101 and 102 of any one of the first and second embodiments are applied to the respective switching elements of the main conversion circuit 201. The six switching elements are connected in series in pairs of two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the three output terminals of the main conversion circuit 201, which are the output terminals of each upper and lower arm, are connected to the load 300.

[0098] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs, to the control electrodes of the respective switching elements, drive signals that turn the switching elements on and drive signals that turn the switching elements off according to control signals from the control circuit 203 described later. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal becomes a voltage signal (off signal) that is lower than the threshold voltage of the switching element.

[0099] The control circuit 203 controls the switching elements of the main conversion circuit 201 in such a way as to supply the desired power to the load 300. Specifically, the control circuit 203 calculates the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on-state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the voltage to be output. Further, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that a conduction signal is output to the switching elements that should be in the on-state and a disconnection signal is output to the switching elements that should be in the off-state at each moment. The drive circuit 202 outputs a conduction signal or a disconnection signal to the control electrodes of the respective switching elements as a drive signal according to this control signal.

[0100] In the power conversion device of the present embodiment, as the switching elements of the main conversion circuit 201, the semiconductor devices 101 and 102 of any one of Embodiments 1 and 2 are applied. Therefore, the reliability can be improved by reducing the warpage of the semiconductor wafer.

[0101] In the present embodiment, an example in which the semiconductor devices 101 and 102 are applied to a two-level three-phase inverter has been described. However, the semiconductor devices 101 and 102 are not limited to this case and can be applied to various power conversion devices. In the present embodiment, it is a two-level power conversion device, but it may also be a three-level or multi-level power conversion device, and the semiconductor devices 101 and 102 can also be applied to a single-phase inverter when supplying power to a single-phase load. Further, the semiconductor devices 101 and 102 can also be applied to a DC / DC converter or an AC / DC converter when supplying power to a DC load or the like.

[0102] Further, the power conversion device to which the semiconductor devices 101 and 102 are applied is not limited to the case where the load is a motor as described above. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can further be used as a power conditioner for a solar power generation system or a power storage system.

[0103] As described above, the preferred embodiments and the like have been described in detail. However, it is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

[0104] Hereinafter, each aspect of the present disclosure will be collectively described as an appendix.

[0105] (Appendix 1)

[0106] A semiconductor device, comprising:

[0107] A drift layer;

[0108] A base layer of a second conductivity type, which is formed on a part of the surface layer of the drift layer;

[0109] A channel formation layer of a first conductivity type, which is formed on a part of the surface layer of the base layer; and

[0110] A gate electrode, which is disposed via a gate insulating film in a plurality of trenches penetrating the channel formation layer and the base layer,

[0111] The channel formation layer formed between the plurality of trenches becomes shallower and has a lower impurity concentration as it is farther from the side walls of the plurality of trenches.

[0112] (Supplementary Note 2)

[0113] In the semiconductor device described in Supplementary Note 1, wherein,

[0114] A well layer is further provided, which is adjacent to the channel formation layer from below and contacts the side walls of the plurality of trenches.

[0115] (Supplementary Note 3)

[0116] A method for manufacturing a semiconductor device, which includes:

[0117] A base layer formation process of implanting impurity ions into a drift layer to form a base layer of a second conductivity type in the drift layer;

[0118] A trench formation process of forming a plurality of trenches penetrating the base layer; and

[0119] A first inclined implantation process of implanting impurity ions from an inclined direction at an angle θ with respect to the side walls of the plurality of trenches to form a channel formation layer of a first conductivity type at least in a part of the base layer that contacts the side walls of the plurality of trenches.

[0120] (Supplementary Note 4)

[0121] In the method for manufacturing a semiconductor device described in Supplementary Note 3, wherein,

[0122] The implantation energy of the impurity ions in the first inclined implantation process is 10 keV or more and 150 keV or less.

[0123] (Supplementary Note 5)

[0124] In the method for manufacturing a semiconductor device described in Supplementary Note 3 or 4, wherein,

[0125] When the widths of a first trench and a second trench arbitrarily selected from the plurality of trenches are set as d1 and d2 respectively, d2 / d1 is 0.8 or more and 1.2 or less.

[0126] (Supplementary Note 6)

[0127] In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 5, wherein,

[0128] In the first inclined implantation step, the angle θ is 70° or less.

[0129] (Supplementary Note 7)

[0130] In the method for manufacturing a semiconductor device according to Supplementary Note 5, wherein,

[0131] In the first inclined implantation step, when the angles θ with respect to the first trench and the second trench are set to θ1 and θ2, respectively, tanθ2 / tanθ1 = d2 / d1.

[0132] (Supplementary Note 8)

[0133] In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 6, wherein,

[0134] The trench formation step is a step of forming the plurality of trenches using an oxide film mask,

[0135] Between the base layer formation step and the trench formation step, there is further provided: an ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation,

[0136] Between the trench formation step and the first inclined implantation step, there is further provided: a mask thickness adjustment step of adjusting the thickness of the oxide film mask,

[0137] The adjusted thickness of the oxide film mask is determined according to the widths of the plurality of trenches adjacent to the oxide film mask.

[0138] (Supplementary Note 9)

[0139] In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 6, wherein,

[0140] Between the base layer formation step and the trench formation step, there is provided: an ion implantation step of forming the channel formation layer on the surface layer of the base layer by ion implantation,

[0141] After the trench formation step, there is provided an etching step of etching the surface layer of the channel formation layer,

[0142] The etching amount of the channel formation layer in the etching step is determined according to the widths of the trenches adjacent to the channel formation layer.

[0143] (Supplementary Note 10)

[0144] In the method for manufacturing a semiconductor device according to any one of Supplementary Notes 3 to 9,

[0145] after the first inclined ion implantation step, a second inclined ion implantation step is further provided, that is, impurity ions are implanted from a direction inclined with respect to the side walls of the plurality of trenches, and a well layer of a second conductivity type is formed in a region of the base layer in contact with the plurality of trenches.

[0146] (Supplementary Note 11)

[0147] A power conversion device, comprising:

[0148] a main conversion circuit having the semiconductor device according to Supplementary Note 1 or 2, which converts and outputs the input power;

[0149] a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and

[0150] a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

Claims

1. A semiconductor device, characterized in that: have: drift layer; A base layer of a second conductivity type formed on a portion of a surface layer of the drift layer; a first conductivity type channel formation layer formed on a portion of a surface layer of the base layer; as well as a gate electrode provided in a plurality of grooves penetrating the channel formation layer and the base layer via a gate insulating film, The channel formation layer formed between the plurality of trenches is shallower and has a lower impurity concentration as it is farther away from the sidewalls of the plurality of trenches.

2. The semiconductor device according to claim 1, wherein: A well layer is further provided, which is adjacent to the channel formation layer from below and is in contact with the side walls of the plurality of trenches.

3. A method for manufacturing a semiconductor device, characterized in that: have: a base layer forming step of injecting impurity ions into the drift layer to form a base layer of the second conductivity type in the drift layer; a groove forming step of forming a plurality of grooves penetrating the base layer; and In the first oblique implantation step, impurity ions are implanted from an oblique direction at an angle θ with respect to the side walls of the plurality of trenches to form a first conductivity type channel formation layer at least in a portion of the base layer in contact with the side walls of the plurality of trenches.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The implantation energy of the impurity ions in the first oblique implantation step is greater than or equal to 10 keV and less than or equal to 150 keV.

5. The method for manufacturing a semiconductor device according to claim 3 or 4, characterized in that: When the widths of a first trench and a second trench arbitrarily selected from the plurality of trenches are d1 and d2, respectively, d2 / d1 is greater than or equal to 0.8 and less than or equal to 1.

2.

6. The method for manufacturing a semiconductor device according to any one of claims 3 to 5, characterized in that: In the first oblique implantation step, the angle θ is 70° or less.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: In the first oblique implantation step, when the angle θ with respect to the first trench and the second trench is respectively θ1 and θ2, tanθ2 / tanθ1=d2 / d1.

8. The method for manufacturing a semiconductor device according to any one of claims 3 to 6, wherein: The trench forming step is a step of forming the plurality of trenches using an oxide film mask. The method further comprises, between the base layer forming step and the groove forming step, an ion implantation step of forming the channel forming layer on the surface of the base layer by ion implantation. The method further comprises, between the trench forming step and the first tilted implantation step, a mask thickness adjustment step of adjusting the thickness of the oxide film mask. The adjusted thickness of the oxide film mask is determined according to the widths of the plurality of trenches adjacent to the oxide film mask.

9. The method for manufacturing a semiconductor device according to any one of claims 3 to 6, wherein: An ion implantation step of forming the channel formation layer on the surface of the base layer by ion implantation is provided between the base layer formation step and the groove formation step. After the trench forming step, an etching step of etching the surface layer of the channel forming layer is provided. The etching amount of the channel formation layer in the etching step is determined according to the width of the trench adjacent to the channel formation layer.

10. The method for manufacturing a semiconductor device according to any one of claims 3 to 9, characterized in that: A second oblique implantation step is further provided after the first oblique implantation step, namely, implanting impurity ions from a direction oblique to the sidewalls of the plurality of trenches to form a well layer of a second conductivity type in a region of the base layer contacting the plurality of trenches.

11. A power conversion device, characterized in that: have: A main conversion circuit, comprising the semiconductor device according to claim 1 or 2, which converts input power and outputs it; a driving circuit that outputs a driving signal for driving the semiconductor device to the semiconductor device; as well as A control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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