Structure for reducing ohmic contact resistance of base region of hot electron transistor and preparation method thereof

Abstract

The invention provides a structure for reducing ohmic contact resistance of a base region of a hot electron transistor and a preparation method thereof, and relates to the technical field of semiconductors. Comprising a substrate, a first unintentionally-doped GaN layer, a first N + GaN layer, a second unintentionally-doped GaN layer, an Al < 0.2 > Ga < 0.8 > N layer, a second N + GaN layer, an AlN layer, a third unintentionally-doped GaN layer and a third N + GaN layer which are sequentially arranged from bottom to top. The device further comprises a first step, a second step, emitter ohmic metal, collector ohmic metal and emitter ohmic metal. The groove extends downwards from the lower step surface of the first step and penetrates through the AlN layer into the second N + GaN layer, fourth N + GaN layers are arranged inside and outside the groove, and the fourth N + GaN layers make contact with the second N + GaN layer. According to the invention, extremely high requirements on etching precision and damage in the prior art are avoided, the etching precision and the etching damage sensitivity are reduced, and relatively low ohmic contact resistance can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a structure for reducing the base ohmic contact resistance of a hot electron transistor and a preparation method thereof. Background Art

[0002] Transistor devices are applied in aspects such as communication / 6G, radar, space exploration, security inspection, medical detection, imaging, etc., and there are higher requirements for the frequency of transistor devices in the above aspects. Compared with Si-based and GaAs-based microwave devices, GaN-based High Electron Mobility Transistor (HEMT) devices have higher power density and efficiency, and thus show great advantages in fields such as communication base stations, radar, satellite communication, and electronic warfare. GaN HEMT devices mainly reduce the transit delay by reducing the gate length, and thus achieve a higher cut-off frequency. Heterojunction Bipolar Transistor (HBT) can also achieve a high cut-off frequency. Different from HEMT devices that rely on the lateral drift diffusion of carriers, HBT devices are quasi-vertical devices. The high-frequency performance of HBT in the gallium nitride system has certain limitations. The key reason is that the base composed of Mg-doped p-GaN shows very low hole density and hole mobility. Mg has a very high activation energy (20 meV) and a very low ionization rate in GaN, resulting in a very large base sheet resistance. In addition, it is difficult to find a metal with a large enough work function in wide-bandgap GaN to fabricate a low-barrier p-type ohmic contact. Therefore, it is very difficult to realize III-nitride HBT devices.

[0003] In order to prepare gallium nitride-based transistors applicable to the terahertz band, domestic and foreign research has begun on quasi-vertical structure GaN-based Hot Electron Transistor (HET). The characteristic of the quasi-vertical structure GaN-based HET is to utilize the fact that its base thickness is less than the electron mean free path to achieve near-ballistic transport of carriers. When the base electrons cross the base, the degree of various scattering is reduced, and the base transit delay is extremely low, and thus a high cut-off frequency can be achieved. Whether the HET device can exhibit good electrical characteristics depends crucially on whether a good ohmic contact can be formed on the base.

[0004] When realizing the base ohmic contact in the prior art, generally, the emitter material above the base is etched away to expose the base mesa, and the base metal is deposited on the mesa. However, in the prior art, the base ohmic contact resistance is extremely sensitive to the etching depth and etching damage, and it is difficult to achieve a lower ohmic contact resistance through high-precision and low-damage etching. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a preparation method and device for reducing the base ohmic contact resistance of a hot electron transistor, so as to solve the problem that the prior art is extremely sensitive to etching depth and etching damage and it is difficult to achieve a lower base ohmic contact resistance.

[0006] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0007] The first aspect of the present invention provides a structure for reducing the base ohmic contact resistance of a hot electron transistor, including: a substrate, a first unintentionally doped GaN layer, a first N+ GaN layer, a second unintentionally doped GaN layer, Al 0.2 Ga 0.8 N layer, a second N+ GaN layer, an AlN layer, a third unintentionally doped GaN layer, and a third N+ GaN layer, which are arranged in sequence from bottom to top;

[0008] A first step, extending downward from one side area of the third N+ GaN layer, and sequentially penetrating through the third N+ GaN layer and the third unintentionally doped GaN layer to the upper surface of the AlN layer;

[0009] A second step, extending downward from one side area at the bottom of the first step, and sequentially penetrating through the AlN layer, the second N+ GaN layer, Al 0.2 Ga 0.8 N layer and the second unintentionally doped GaN layer to the upper surface of the first N+ GaN layer;

[0010] A trench, extending downward from the lower step surface of the first step and penetrating through the AlN layer into the second N+ GaN layer. A fourth N+ GaN layer is provided both inside and outside the trench, and the fourth N+ GaN layer is in contact with the second N+ GaN layer;

[0011] Base ohmic metal, formed on the fourth N+ GaN layer, emitter ohmic metal, formed on the third N+ GaN layer, collector ohmic metal, formed on the lower step surface of the second step.

[0012] In some alternative embodiments of the first aspect of the present invention, the structure for reducing the base ohmic contact resistance of a hot electron transistor further includes:

[0013] A third step, extending downward from one side area at the bottom of the second step, and sequentially penetrating through the first N+ GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate;

[0014] A fourth step, extending downward from the other side area of the third N+ GaN layer far from the third step, and sequentially penetrating through the third N+ GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+ GaN layer, Al 0.2 Ga 0.8The N layer, the second unintentionally doped GaN layer, the first N+ GaN layer, and the first unintentionally doped GaN layer, to the upper surface of the substrate;

[0015] A two-dimensional electron gas contact layer is formed in the contact region between the second N+ GaN layer and the AlN layer.

[0016] In some modified embodiments of the first aspect of the present invention, the doping ions of the first N+ GaN layer, the second N+ GaN layer, the third N+ GaN layer, and the fourth N+ GaN layer are all Si ions, and the doping concentration of the Si ions is 1×10 19 cm -3 .

[0017] In some modified embodiments of the first aspect of the present invention, the materials of the base ohmic metal, the emitter ohmic metal, and the collector ohmic metal are all Ti / Al / Ni / Au stacked layer materials, and the thickness of the Ti / Al / Ni / Au stacked layer materials is 20 / 160 / 55 / 45 nm.

[0018] In some modified embodiments of the first aspect of the present invention, the thicknesses of the first unintentionally doped GaN layer and the second unintentionally doped GaN layer are both 50 nm, and the thickness of the third unintentionally doped GaN layer is 80 nm.

[0019] In some modified embodiments of the first aspect of the present invention, the thickness of the first N+ GaN layer is 90 nm, the thickness of the second N+ GaN layer is 8 nm, and the thickness of the third N+ GaN layer is 20 nm.

[0020] In some modified embodiments of the first aspect of the present invention, Al 0.2 Ga 0.8 The thickness of the N layer is 30 nm, and the thickness of the AlN layer is 2 nm.

[0021] The second aspect of the present invention provides a preparation method for reducing the base ohmic contact resistance of a hot electron transistor, including:

[0022] Obtain a hot electron transistor epitaxial structure, which includes a substrate, a first unintentionally doped GaN layer, a first N+ GaN layer, a second unintentionally doped GaN layer, Al 0.2 Ga 0.8 The N layer, the second N+ GaN layer, the AlN layer, the third unintentionally doped GaN layer, and the third N+ GaN layer, which are arranged in sequence from bottom to top;

[0023] Etch a first step in a side region of the third N+ GaN layer, and the first step sequentially penetrates through the third N+ GaN layer and the third unintentionally doped GaN layer to the upper surface of the AlN layer;

[0024] Using plasma enhanced chemical vapor deposition, deposit a SiO2 layer on the etched third N+ GaN layer and the first step;

[0025] Etch trenches in the target SiO2 layer, the trenches sequentially penetrate the target SiO2 layer and the AlN layer into the second N+ GaN layer, and the target SiO2 layer is the SiO2 layer on the lower step surface of the first step;

[0026] Grow a preset N+ GaN layer on the etched SiO2 layer and in the trenches;

[0027] Remove the etched SiO2 layer and the preset N+ GaN layer on the etched SiO2 layer to generate a fourth N+ GaN layer, and the fourth N+ GaN layer is in contact with the second N+ GaN layer;

[0028] Deposit a metal stack and perform annealing treatment on the metal stack to form a base ohmic metal on the fourth N+ GaN layer;

[0029] Etch a second step in a side area at the bottom of the first step, the second step sequentially penetrates the AlN layer, the second N+ GaN layer, Al 0.2 Ga 0.8 N layer and the second unintentionally doped GaN layer to the upper surface of the first N+ GaN layer;

[0030] Deposit a metal stack and perform annealing treatment on the metal stack to form a collector ohmic metal on the lower step surface of the second step and an emitter ohmic metal on the third N+ GaN layer.

[0031] In some modified embodiments of the second aspect of the present invention, after depositing a metal stack and performing annealing treatment on the metal stack to form a collector ohmic metal on the lower step surface of the second step and an emitter ohmic metal on the third N+ GaN layer, the preparation method further includes:

[0032] Etch a third step in a side area at the bottom of the second step, the third step sequentially penetrates the first N+ GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate;

[0033] Etch a fourth step in the other side area of the third N+ GaN layer far from the third step, the fourth step sequentially penetrates the third N+ GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+ GaN layer, Al 0.2 Ga 0.8 N layer, the second unintentionally doped GaN layer, the first N+ GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate.

[0034] In some modified embodiments of the second aspect of the present invention, the process conditions for the fourth N+GaN layer are as follows: the growth temperature is 650°C - 750°C, the plasma power is 250W - 400W, the nitrogen flow rate is 2.5 sccm - 3.5 sccm, and the Ga beam current is 1×10 -7 -2×10 -6 Torr, and the Si beam current is 8×10 -9 -4×10 -8 Torr. Alternatively, the process conditions for the fourth N+GaN layer are as follows: the growth temperature is 800°C - 1000°C, the flow rate of NH3 is 25 slm - 35 slm, the flow rate of TMGa is 19 sccm - 23 sccm, and the flow rate of SiH4 is 6 sccm - 12 sccm.

[0035] Compared with the prior art, the structure for reducing the ohmic contact resistance of the base region of a hot electron transistor and its preparation method provided by the present invention. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor includes: a substrate, a first unintentionally doped GaN layer, a first N+GaN layer, a second unintentionally doped GaN layer, an Al 0.2 Ga 0.8 N layer, a second N+GaN layer, an AlN layer, a third unintentionally doped GaN layer, and a third N+GaN layer, which are arranged in sequence from bottom to top; a first step that extends downward from a side region of the third N+GaN layer and sequentially penetrates through the third N+GaN layer and the third unintentionally doped GaN layer to the upper surface of the AlN layer; a second step that extends downward from a side region at the bottom of the first step and sequentially penetrates through the AlN layer, the second N+GaN layer, the Al 0.2 Ga 0.8 N layer, and the second unintentionally doped GaN layer to the upper surface of the first N+GaN layer; a trench that extends downward from the lower step surface of the first step and penetrates through the AlN layer into the second N+GaN layer. The fourth N+GaN layer is provided both inside and outside the trench, and the fourth N+GaN layer is in contact with the second N+GaN layer; a base ohmic metal is formed on the fourth N+GaN layer, an emitter ohmic metal is formed on the third N+GaN layer, and a collector ohmic metal is formed on the lower step surface of the second step. In this way, by bringing the fourth N+GaN layer into contact with the second N+GaN layer, the sensitivity to etching accuracy and etching damage is reduced, and a lower ohmic contact resistance can be achieved with a lower etching accuracy and etching damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present invention will become readily understood. In the drawings, several embodiments of the present invention are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, where:

[0037] Figure 1 A schematic diagram showing a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor;

[0038] Figure 2 A flowchart of a preparation method for a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor;

[0039] Figure 3 A schematic diagram showing an epitaxial structure of a hot electron transistor;

[0040] Figure 4 A process diagram of a preparation process for a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor.

[0041] Description of reference numerals

[0042] 1. Substrate; 2. First unintentionally doped GaN layer; 3. First N+ GaN layer; 4. Second unintentionally doped GaN layer; 5. Al 0.2 Ga 0.8 GaN layer; 6. Second N+ GaN layer; 7. AlN layer; 8. Third unintentionally doped GaN layer; 9. Third N+ GaN layer; 10. First step; 11. Second step; 12. Trench; 13. Base ohmic metal; 14. Emitter ohmic metal; 15. Collector ohmic metal; 16. Third step; 17. Fourth step; 18. Two-dimensional electron gas contact layer; 19. Fourth N+ GaN layer. Detailed implementation manners

[0043] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be completely conveyed to those skilled in the art.

[0044] It should be noted that: unless otherwise specified, the technical terms or scientific terms used in the present invention should have the ordinary meaning understood by those skilled in the art to which the present invention belongs.

[0045] The methods in the embodiments of the present invention will be described in detail below.

[0046] Figure 1 A schematic diagram showing a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor, and the structure for reducing the ohmic contact resistance of the base region of a hot electron transistor includes: a substrate 1, a first unintentionally doped GaN layer 2, a first N+ GaN layer 3, a second unintentionally doped GaN layer 4, and Al arranged in sequence from bottom to top0.2 Ga 0.8 an N layer 5, a second N+GaN layer 6, an AlN layer 7, a third unintentionally doped GaN layer 8, and a third N+GaN layer 9;

[0047] A first step 10 extends downward from a side region of the third N+GaN layer 9 and sequentially penetrates through the third N+GaN layer 9 and the third unintentionally doped GaN layer 8 to the upper surface of the AlN layer 7;

[0048] A second step 11 extends downward from a side region at the bottom of the first step 10 and sequentially penetrates through the AlN layer 7, the second N+GaN layer 6, Al 0.2 Ga 0.8 the N layer 5, and the second unintentionally doped GaN layer 4 to the upper surface of the first N+GaN layer 3;

[0049] A trench 12 extends downward from the lower step surface of the first step 10 and penetrates through the AlN layer 7 into the second N+GaN layer 6. A fourth N+GaN layer 19 is provided both inside and outside the trench 12, and the fourth N+GaN layer 19 is in contact with the second N+GaN layer 6;

[0050] A base ohmic metal 13 is formed on the fourth N+GaN layer 19, an emitter ohmic metal 14 is formed on the third N+GaN layer 9, and a collector ohmic metal 15 is formed on the lower step surface of the second step 11.

[0051] In this embodiment, the structure for reducing the base ohmic contact resistance of the hot electron transistor further includes:

[0052] A third step 16 extends downward from a side region at the bottom of the second step 11 and sequentially penetrates through the first N+GaN layer 3 and the first unintentionally doped GaN layer 2 to the upper surface of the substrate 1;

[0053] A fourth step 17 extends downward from the other side region of the third N+GaN layer 9 away from the third step 16 and sequentially penetrates through the third N+GaN layer 9, the third unintentionally doped GaN layer 8, the AlN layer 7, the second N+GaN layer 6, Al 0.2 Ga 0.8 the N layer 5, the second unintentionally doped GaN layer 4, the first N+GaN layer 3, and the first unintentionally doped GaN layer 2 to the upper surface of the substrate 1;

[0054] A two-dimensional electron gas contact layer 18 is formed in the contact region between the second N+GaN layer 6 and the AlN layer 7.

[0055] The contact between the second N+GaN layer 6 and the AlN layer 7 can generate the two-dimensional electron gas contact layer 18.

[0056] In this embodiment, the doping ions of the first N+ GaN layer 3, the second N+ GaN layer 6, the third N+ GaN layer 9, and the fourth N+ GaN layer 19 are all Si ions, and the doping concentration of the Si ions is 1×10 19 cm -3 .

[0057] In this embodiment, the materials of the base ohmic metal 13, the emitter ohmic metal 14, and the collector ohmic metal 15 are all Ti / Al / Ni / Au stacked layer materials, and the thickness of the Ti / Al / Ni / Au stacked layer materials is 20 / 160 / 55 / 45 nm.

[0058] In this embodiment, the thicknesses of the first unintentionally doped GaN layer 2 and the second unintentionally doped GaN layer 4 are both 50 nm, and the thickness of the third unintentionally doped GaN layer 8 is 80 nm.

[0059] In this embodiment, the thickness of the first N+ GaN layer 3 is 90 nm, the thickness of the second N+ GaN layer 6 is 8 nm, and the thickness of the third N+ GaN layer 9 is 20 nm.

[0060] In this embodiment, the thickness of the Al 0.2 Ga 0.8 N layer 5 is 30 nm, and the thickness of the AlN layer 7 is 2 nm.

[0061] Based on the above Figure 1 implementation method, it can be seen that the structure for reducing the base ohmic contact resistance of the hot electron transistor in the embodiment of the present invention includes: a substrate 1, a first unintentionally doped GaN layer 2, a first N+ GaN layer 3, a second unintentionally doped GaN layer 4, Al 0.2 Ga 0.8 N layer 5, a second N+ GaN layer 6, an AlN layer 7, a third unintentionally doped GaN layer 8, and a third N+ GaN layer 9, which are arranged in sequence from bottom to top; a first step 10, extending downward from a side region of the third N+ GaN layer 9 and sequentially penetrating through the third N+ GaN layer 9 and the third unintentionally doped GaN layer 8 to the upper surface of the AlN layer 7; a second step 11, extending downward from a side region at the bottom of the first step 10 and sequentially penetrating through the AlN layer 7, the second N+ GaN layer 6, Al 0.2 Ga 0.8The N-layer 5 and the second unintentionally doped GaN layer 4 are up to the upper surface of the first N+GaN layer 3; the trench 12 extends downward from the lower step surface of the first step 10 and penetrates through the AlN layer 7 into the second N+GaN layer 6. The fourth N+GaN layer 19 is provided both inside and outside the trench 12, and the fourth N+GaN layer 19 is in contact with the second N+GaN layer 6; the base ohmic metal 13 is formed on the fourth N+GaN layer 19, the emitter ohmic metal 14 is formed on the third N+GaN layer 9, and the collector ohmic metal 15 is formed on the lower step surface of the second step 11. In this way, by contacting the fourth N+GaN layer 19 with the second N+GaN layer 6, the sensitivity to etching accuracy and etching damage is reduced, and a lower ohmic contact resistance can be achieved with a lower etching accuracy and etching damage with lower sensitivity.

[0062] Figure 2 Schematically shows a flowchart of a preparation method of a structure for reducing the base ohmic contact resistance of a hot electron transistor in an embodiment of the present invention. Refer to Figure 2 As shown, the preparation method of the structure for reducing the base ohmic contact resistance of the hot electron transistor may include:

[0063] S201. Obtain a hot electron transistor epitaxial structure.

[0064] Among them, Figure 3 Schematically shows a schematic diagram of a hot electron transistor epitaxial structure. Refer to Figure 3 As shown, the HET epitaxial structure includes a substrate 1, a first unintentionally doped GaN layer 2, a first N+GaN layer 3, a second unintentionally doped GaN layer 4, Al 0.2 Ga 0.8 N layer 5, a second N+GaN layer 6, an AlN layer 7, a third unintentionally doped GaN layer 8, and a third N+GaN layer 9 arranged in sequence from bottom to top.

[0065] The contact area between the second N+GaN layer 6 and the AlN layer 7 forms a two-dimensional electron gas contact layer 18.

[0066] The thicknesses of the first unintentionally doped GaN layer 2 and the second unintentionally doped GaN layer 4 are both 50 nm, and the thickness of the third unintentionally doped GaN layer 8 is 80 nm. The thickness of the first N+GaN layer 3 is 90 nm, the thickness of the second N+GaN layer 6 is 8 nm, and the thickness of the third N+GaN layer 9 is 20 nm. Al 0.2 Ga 0.8 N layer 5 has a thickness of 30 nm, and the AlN layer 7 has a thickness of 2 nm. The doping ions of the first N+GaN layer 3, the second N+GaN layer 6, and the third N+GaN layer 9 are all Si ions, and the doping concentration of the Si ions is 1×10 19 cm -3 .

[0067] Figure 4 Schematically shows the manufacturing process diagram of the structure for reducing the ohmic contact resistance of the base region of a hot electron transistor. Figure 4 In (a), it is the manufacturing process diagram for cleaning the HET epitaxial structure. After obtaining the HET epitaxial structure, it is necessary to clean the HET epitaxial structure, successively through acetone, stripping solution, acetone, isopropyl alcohol, and ultrapure water, and finally dried with N2 to remove surface impurities and organic substances.

[0068] S202. Etch a first step 10 in a side region of the third N+GaN layer 9, and the first step 10 successively penetrates through the third N+GaN layer 9 and the third unintentionally doped GaN layer 8 to the upper surface of the AlN layer 7.

[0069] Specifically, Figure 4 Schematically shows the manufacturing process diagram of the structure for reducing the ohmic contact resistance of the base region of a hot electron transistor. Figure 4 In (b), it is the manufacturing process diagram for etching the first step 10. Use inductively coupled plasma (ICP) to etch the first step 10 of the HET epitaxial structure. The etching gas is BCl3 / Cl2, the upper / lower electrode power is 20W / 8W, the etching rate is 4nm / min, and the etching depth is 100nm. After etching, perform conventional etching cleaning to remove the photoresist residues on the surface.

[0070] S203. Use plasma enhanced chemical vapor deposition to deposit a SiO2 layer on the etched third N+GaN layer 9 and the first step 10.

[0071] Specifically, Figure 4 Schematically shows the manufacturing process diagram of the structure for reducing the ohmic contact resistance of the base region of a hot electron transistor. Figure 4 In (c), it is the manufacturing process diagram for depositing the SiO2 layer. Use plasma enhanced chemical vapor deposition (PECVD) to deposit a SiO2 layer with a thickness of 110 - 130nm.

[0072] The function of the SiO2 layer is to isolate the etched first step 10 to prevent electrode short - circuit leakage.

[0073] S204. Etch a trench 12 in the target SiO2 layer, and the trench 12 successively penetrates through the target SiO2 layer and the AlN layer 7 into the second N+GaN layer 6.

[0074] Among them, the target SiO2 layer is the SiO2 layer on the lower step surface of the first step 10.

[0075] Specifically, Figure 4 schematically shows a preparation process diagram of a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor. Figure 4 In (d), it is a preparation process diagram for etching out trench 12. To etch out trench 12, an F-based etching is used to remove the target SiO2 layer until the thickness of the target SiO2 layer is completely etched. After the etching of the target SiO2 layer, the AlN layer 7 is etched. The etching of the AlN layer 7 uses Cl-based atomic layer etching technology (Atomic Layer Etching, AlE) to etch away the AlN layer 7 to 4 - 8 nm below the two-dimensional electron gas contact layer 18, so as to etch out trench 12. After etching out trench 12, trimethylammonium hydroxide (TMAH) or ammonia water solution is selected for surface treatment before secondary epitaxy to remove the Cl-based etching derivatives and dangling bonds of GaN etching, and to improve the interface between the subsequent regrown GaN layer, i.e., the preset N+GaN layer, and the base GaN layer, i.e., the second N+GaN layer 6.

[0076] S205. Grow the preset N+GaN layer on the etched SiO2 layer and in trench 12.

[0077] Specifically, Figure 4 schematically shows a preparation process diagram of a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor. Figure 4 In (e), it is a preparation process diagram for growing the preset N+GaN layer. The preset N+GaN layer is grown on the etched SiO2 layer and in trench 12. The thickness of the preset N+GaN layer on the etched SiO2 layer is 40 - 60 nm. Before regrowing the GaN layer, the surface of the sample after etching out trench 12 needs to be subjected to surface cleaning treatment to remove etching derivatives, impurities, dangling bonds, etc. The doping ions of the preset N+GaN layer are all Si ions, and the doping concentration of Si ions is 1×10 19 cm -3 . The process conditions for growing the preset N+GaN layer are: the growth temperature is 650°C - 750°C, the plasma power is 250W - 400W, the nitrogen flow rate is 2.5 sccm - 3.5 sccm, the Ga beam current is 1×10 -7 -2×10 -6 Torr, and the Si beam current is 8×10 -9 -4×10 -8 Torr.

[0078] Another implementation method for growing the preset N+ GaN layer is to use Metal Organic Chemical Vapor Deposition (MOCVD) to grow the preset N+ GaN layer on the etched SiO2 layer and in the trench 12. The thickness of the preset N+ GaN layer on the etched SiO2 layer is 40 - 60 nm. Before growing the GaN layer, the surface of the sample after etching the trench 12 needs to be surface cleaned to remove etching derivatives, impurities, dangling bonds, etc. The doping ions of the preset N+ GaN layer are all Si ions, and the doping concentration of Si ions is 1×10 19 cm -3 . The process conditions for growing the preset N+ GaN layer are: the growth temperature is 800°C - 1000°C, H2 is used as the carrier gas, the flow rate of NH3 is 25 slm - 35 slm, the flow rate of TMGa is controlled at 19 sccm - 23 sccm, and the flow rate of SiH4 is 6 sccm - 12 sccm.

[0079] S206. Remove the etched SiO2 layer and the preset N+ GaN layer on the etched SiO2 layer to generate the fourth N+ GaN layer 19.

[0080] Among them, the fourth N+ GaN layer 19 is in contact with the second N+ GaN layer 6.

[0081] Specifically, the process conditions for the fourth N+ GaN layer 19 are: the growth temperature is 650°C - 750°C, the plasma power is 250 W - 400 W, the nitrogen flow rate is 2.5 sccm - 3.5 sccm, the Ga beam current is 1×10 -7 -2×10 -6 Torr, and the Si beam current is 8×10 -9 -4×10 -8 Torr. Or, the process conditions for the fourth N+ GaN layer 19 are: the growth temperature is 800°C - 1000°C, the flow rate of NH3 is 25 slm - 35 slm, the flow rate of TMGa is 19 sccm - 23 sccm, and the flow rate of SiH4 is 6 sccm - 12 sccm.

[0082] Specifically, Figure 4 Schematically shows the manufacturing process diagram of the structure for reducing the base ohmic contact resistance of a hot electron transistor. Figure 4In (f), it is the preparation process diagram for generating the fourth N+GaN layer 19. SiO2 can react with hydrofluoric acid (HF). The sample for growing the preset N+GaN layer is immersed in the HF acid solution, and the etched SiO2 layer and the preset N+GaN layer on the etched SiO2 layer are removed. Since AlN and GaN do not react with HF acid, no other impurities will be introduced into the sample for growing the preset N+GaN layer. Then, the possible residual polycrystalline N+GaN on the surface of the sample for growing the preset N+GaN layer is removed by using the blue film mechanical peeling method.

[0083] S207. Deposit a metal stack and anneal the metal stack to form the base ohmic metal 13 on the fourth N+GaN layer 19.

[0084] Specifically, Figure 4 It schematically shows the preparation process diagram of the structure for reducing the base ohmic contact resistance of the hot electron transistor. Figure 4 In (g), it is the preparation process diagram for forming the base ohmic metal 13. Using the electron beam evaporation process, align the lithography machine with the metal stack mark, and then use the evaporation platform for evaporation. The metal stack is Ti / Al / Ni / Au = 20 / 160 / 55 / 45 nm, and the annealing temperature is 400 - 800 °C.

[0085] The base ohmic metal 13 contacts the fourth N+GaN layer 19 and the two-dimensional electron gas contact layer 18, and the base ohmic metal 13 can form a good ohmic contact.

[0086] S208. Etch out the second step 11 in a side area at the bottom of the first step 10. The second step 11 sequentially penetrates through the AlN layer 7, the second N+GaN layer 6, the Al 0.2 Ga 0.8 N layer 5 and the second unintentionally doped GaN layer 4 to the upper surface of the first N+GaN layer 3.

[0087] Specifically, Figure 4 It schematically shows the preparation process diagram of the structure for reducing the base ohmic contact resistance of the hot electron transistor. Figure 4 In (h), it is the preparation process diagram for etching out the second step 11. The ICP-based Cl-based etching is adopted, the process gas is BCl3 / Cl2, the upper / lower electrode power is 51 W / 14 W, and the etching rate is 19 - 22 nm / min.

[0088] S209. Deposit a metal stack and anneal the metal stack to form the collector ohmic metal 15 on the lower step surface of the second step 11 and form the emitter ohmic metal 14 on the third N+GaN layer 9.

[0089] Specifically, Figure 4A preparation process diagram of a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor is schematically shown. Figure 4 In (i) of Figure 4 , it is a preparation process diagram for forming the collector ohmic metal 15 and the emitter ohmic metal 14. Using the electron beam evaporation process, the lithography machine is aligned with the metal stack mark, and then evaporated using an evaporation platform. The metal stack is Ti / Al / Ni / Au = 20 / 160 / 55 / 45 nm, the annealing temperature is 700 - 900 °C, the metal stack is in direct contact with the fourth N+ GaN layer 19, and an ohmic contact is formed between the electrodes.

[0090] Specifically, after depositing the metal stack and annealing the metal stack to form the collector ohmic metal 15 on the lower step surface of the second step 11 and the emitter ohmic metal 14 on the third N+ GaN layer 9, the preparation method for reducing the ohmic contact resistance of the base region of the hot electron transistor further includes:

[0091] Etch out the third step 16 in a side region at the bottom of the second step 11. The third step 16 sequentially penetrates through the first N+ GaN layer 3 and the first unintentionally doped GaN layer 2 to the upper surface of the substrate 1.

[0092] Etch out the fourth step 17 in the other side region of the third N+ GaN layer 9 away from the third step 16. The fourth step 17 sequentially penetrates through the third N+ GaN layer 9, the third unintentionally doped GaN layer 8, the AlN layer 7, the second N+ GaN layer 6, the Al 0.2 Ga 0.8 N layer 5, the second unintentionally doped GaN layer 4, the first N+ GaN layer 3 and the first unintentionally doped GaN layer 2 to the upper surface of the substrate 1.

[0093] Specifically, Figure 4 A preparation process diagram of a structure for reducing the ohmic contact resistance of the base region of a hot electron transistor is schematically shown. Figure 4 In (j) of Figure 4 , it is a preparation process diagram for etching out the third step 16 and the fourth step 17. ICP-based Cl-based etching is used, the process gas is BCl3 / Cl2, the upper / lower electrode power is 51 W / 14 W, the etching rate is 19 - 22 nm / min, and the etching depth reaches the buffer layer, i.e., the substrate 1, to reduce the leakage current of adjacent active region devices.

[0094] The present invention proposes a base regrowth process. Using silicon oxide as a hard mask material, the emitter on the base contact layer is etched away to expose the heavily doped GaN base, i.e., the second N+ GaN layer 6. On the second N+ GaN layer 6 and the two-dimensional electron gas contact layer 18, a highly conductive Si-doped GaN layer, i.e., the fourth N+ GaN layer 19, is regrown. The Si-doped GaN, i.e., the fourth N+ GaN layer 19, is in direct contact with the two-dimensional electron gas contact layer 18, greatly reducing the base ohmic contact resistance. In the present invention, even if there is a certain etching depth deviation, the regrown fourth N+ GaN layer 19 can still form a good ohmic contact with the second N+ GaN layer 6 and its two-dimensional electron gas contact layer 18. The reason is that the contact in the core region of the present invention is a contact between n-type GaN and n-type GaN. Therefore, the present invention can solve the problem that the prior art is extremely sensitive to etching depth and etching damage and it is difficult to achieve a low base ohmic contact resistance, providing an important process method for realizing good HET device characteristics.

[0095] The present invention proposes a way to regrow the GaN layer to achieve a low ohmic contact resistance of the base ohmic metal 13, changing the ohmic contact connection mode of the base ohmic metal 13, that is, the contact mode between n-type GaN and n-type GaN. That is to say, the fourth N+ GaN layer 19 is in contact with the second N+ GaN layer 6, reducing the etching accuracy and the sensitivity to etching damage. The present invention can achieve a low contact resistance and sheet resistance, greatly enhancing the lateral mobility of base electrons and the control ability of the base over the hot electrons of the emitter, laying a foundation for achieving high current gain, good three-terminal characteristics, and ultra-high frequency characteristics.

[0096] It should be pointed out here that: The description of the embodiments of the preparation method for reducing the base ohmic contact resistance of the hot electron transistor above is similar to the description of the embodiments of the structure for reducing the base ohmic contact resistance of the hot electron transistor, and has beneficial effects similar to those of the embodiments of the structure for reducing the base ohmic contact resistance of the hot electron transistor. For the technical details not disclosed in the embodiments of the preparation method for reducing the base ohmic contact resistance of the hot electron transistor in the embodiments of the present invention, please refer to the description of the embodiments of the structure for reducing the base ohmic contact resistance of the hot electron transistor of the present invention for understanding.

[0097] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A structure for reducing the ohmic contact resistance of a base region of a hot electron transistor, characterized in that: include: The substrate, the first unintentionally doped GaN layer, the first N+GaN layer, the second unintentionally doped GaN layer, the Al 0.2 Ga 0.8 N layer, a second N+GaN layer, an AlN layer, a third unintentionally doped GaN layer and a third N+GaN layer; A first step extends downward from a side region of the third N+GaN layer and sequentially penetrates the third N+GaN layer and the third unintentionally doped GaN layer to an upper surface of the AlN layer; The second step extends downward from a side area of ​​the bottom of the first step and sequentially passes through the AlN layer, the second N+GaN layer, the Al 0.2 Ga 0.8 N layer and the second unintentionally doped GaN layer to the upper surface of the first N+GaN layer; A groove extending downward from a lower step surface of the first step and penetrating the AlN layer into the second N+GaN layer, wherein a fourth N+GaN layer is disposed inside and outside the groove, and the fourth N+GaN layer is in contact with the second N+GaN layer; The base ohmic metal is formed on the fourth N+GaN layer, the emitter ohmic metal is formed on the third N+GaN layer, and the collector ohmic metal is formed on the lower step surface of the second step.

2. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 1, characterized in that: The structure for reducing the ohmic contact resistance of the base region of the hot electron transistor further comprises: A third step extends downward from a side area of ​​the bottom of the second step and sequentially penetrates the first N+GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate; The fourth step extends downward from the other side of the third N+GaN layer away from the third step, and sequentially passes through the third N+GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+GaN layer, the AlN layer, the second N+GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+GaN layer, the third unintentionally doped GaN layer, the third ... N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N+GaN layer, the third N 0.2 Ga 0.8 N layer, the second unintentionally doped GaN layer, the first N+GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate; A two-dimensional electron gas contact layer is formed in a contact region between the second N+GaN layer and the AlN layer.

3. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 2, characterized in that: The doping ions of the first N+GaN layer, the second N+GaN layer, the third N+GaN layer and the fourth N+GaN layer are all Si ions, and the doping concentration of the Si ions is 1×10 19 cm -3 .

4. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 1, characterized in that: The materials of the base ohmic metal, the emitter ohmic metal and the collector ohmic metal are all Ti / Al / Ni / Au stacked layer materials, and the thickness of the Ti / Al / Ni / Au stacked layer material is 20 / 160 / 55 / 45 nm.

5. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 1, characterized in that: The thickness of the first unintentionally doped GaN layer and the second unintentionally doped GaN layer are both 50 nm, and the thickness of the third unintentionally doped GaN layer is 80 nm.

6. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 1, characterized in that: The thickness of the first N+GaN layer is 90 nm, the thickness of the second N+GaN layer is 8 nm, and the thickness of the third N+GaN layer is 20 nm.

7. The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 1, characterized in that: The Al 0.2 Ga 0.8 The thickness of the N layer is 30 nm, and the thickness of the AlN layer is 2 nm.

8. A method for reducing the ohmic contact resistance of a base region of a hot electron transistor, characterized in that: The structure for reducing the ohmic contact resistance of the base region of a hot electron transistor according to any one of claims 1 to 7 comprises: A hot electron transistor epitaxial structure is obtained, wherein the hot electron transistor epitaxial structure includes a substrate, a first unintentionally doped GaN layer, a first N+GaN layer, a second unintentionally doped GaN layer, an Al 0.2 Ga 0.8 N layer, a second N+GaN layer, an AlN layer, a third unintentionally doped GaN layer and a third N+GaN layer; Etching a first step in a side region of the third N+GaN layer, wherein the first step sequentially penetrates the third N+GaN layer and the third unintentionally doped GaN layer to the upper surface of the AlN layer; Depositing a SiO2 layer on the etched third N+GaN layer and the first step by plasma enhanced chemical vapor deposition; Etching a groove in the target SiO2 layer, the groove sequentially passing through the target SiO2 layer and the AlN layer to the second N+GaN layer, the target SiO2 layer being the SiO2 layer on the lower step surface of the first step; Growing a preset N+GaN layer on the etched SiO2 layer and in the groove; Removing the etched SiO2 layer and the preset N+GaN layer on the etched SiO2 layer to generate a fourth N+GaN layer, wherein the fourth N+GaN layer is in contact with the second N+GaN layer; Depositing a metal stack and annealing the metal stack to form a base ohmic metal on the fourth N+GaN layer; A second step is etched in a side area of ​​the bottom of the first step, and the second step sequentially passes through the AlN layer, the second N+GaN layer, the Al 0.2 Ga 0.8 N layer and the second unintentionally doped GaN layer to the upper surface of the first N+GaN layer; The metal stack is deposited and annealed to form a collector ohmic metal on a lower step surface of the second step and an emitter ohmic metal on the third N+GaN layer.

9. The method for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 8, characterized in that: After depositing the metal stack and annealing the metal stack to form a collector ohmic metal on the lower step surface of the second step and an emitter ohmic metal on the third N+GaN layer, the preparation method further includes: Etching a third step in a side area of ​​the bottom of the second step, wherein the third step sequentially penetrates the first N+GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate; A fourth step is etched in the other side region of the third N+GaN layer away from the third step, wherein the fourth step sequentially passes through the third N+GaN layer, the third unintentionally doped GaN layer, the AlN layer, the second N+GaN layer, the Al 0.2 Ga 0.8 N layer, the second unintentionally doped GaN layer, the first N+GaN layer and the first unintentionally doped GaN layer to the upper surface of the substrate.

10. The method for reducing the ohmic contact resistance of the base region of a hot electron transistor according to claim 8, characterized in that: The process conditions of the fourth N+GaN layer are: growth temperature of 650°C-750°C, plasma power of 250W-400W, nitrogen flow rate of 2.5sccm-3.5sccm, Ga beam current of 1×10 -7 -2×10 -6 Torr, Si beam current is 8×10 -9 -4×10 - 8 Torr, or, the process conditions of the fourth N+GaN layer are: growth temperature of 800°C-1000°C, flow rate of NH3 of 25slm-35slm, flow rate of TMGa of 19sccm-23sccm, and flow rate of SiH4 of 6sccm-12sccm.

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