Transistor circuit with independently biased field plates

Abstract

Improved transistor performance for RF switching and amplification may be achieved by providing a transistor, such as an electron mobility transistor, having one or more field plate electrodes coupled to a channel of the transistor, which may be biased independently of a gate electrode and a current terminal of the transistor. For example, when the field plate electrode is biased to at least partially deplete a channel near the field plate electrode, a breakdown voltage characteristic of the transistor may be improved. In RF applications, circuitry that biases the field plate electrode may be powered by RF signals already present in the circuitry incorporating the transistor, thereby eliminating the need to provide a separate bias voltage source for the field plate electrode.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate to transistors and transistor circuits. Background Art

[0002] High electron mobility transistors (HEMTs) typically operate in depletion mode, in which the transistor channel is conductive when no bias voltage is applied to the gate. The channel conductivity is controlled by applying a negative bias voltage to the gate. Such depletion mode transistors are typically used in applications that require high power handling and large drain-to-source breakdown voltages. In such devices, one or more additional electrodes ("field plates") are typically present above the channel between the gate and drain ends to reduce large potential gradients that may occur near the edges of the gate electrode, thereby improving the breakdown voltage of the device. These field plates are typically electrically coupled to the source end of the transistor. Summary of the Invention

[0003] In an example embodiment, an electronic device includes an input node, an output node, a transistor, and a field plate biasing circuitry. The transistor includes: a first current terminal coupled to the output node; a second current terminal; a semiconducting channel region disposed between the first current terminal and the second current terminal; a gate electrode electrically coupled to the semiconducting channel region and coupled to the input node; and a field plate electrode electrically coupled to the semiconducting channel region and disposed adjacent to the gate electrode. The field plate biasing circuitry is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode, the field plate bias voltage at least partially depleting a channel region of charge carriers near the field plate electrode.

[0004] In another example embodiment, an amplifier device further includes an input node, an output node, a transistor; and a field plate biasing circuitry. The input node is configured to receive a radio frequency (RF) input signal, and the output node is configured to output an amplified signal corresponding to the RF input signal. The transistor is configured to amplify the RF input signal, and the transistor includes: a first current terminal; a second current terminal; a semiconducting channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconducting channel. The gate electrode is configured to modulate an output of the transistor in response to the RF input signal; and the transistor further includes a field plate electrode adjacent to the gate electrode and also coupled to the semiconducting channel. The field plate biasing circuitry is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode, the field plate bias voltage at least partially depleting a channel region of charge carriers near the field plate electrode.

[0005] In another example embodiment, a Doherty amplifier includes: an input node configured to receive a radio frequency (RF) input signal; an output node configured to output an amplified signal corresponding to the RF input signal; a carrier amplifier signal path; a peak amplifier signal path; and a field plate biasing circuitry. The carrier amplifier signal path includes a first transistor configured to amplify the RF input signal within a first input power range of the RF input signal. The peak amplifier signal path includes a second transistor configured to further amplify the RF input signal within a second input power range of the RF input signal.

[0006] The first transistor includes a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconductive channel and configured to modulate an output of the transistor in response to the RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconductive channel.

[0007] The second transistor includes a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconductive channel and configured to modulate an output of the transistor in response to the RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconductive channel.

[0008] The field plate biasing circuitry is coupled to the field plate electrodes of the first transistor and the second transistor and is configured to apply a desired first field plate voltage to the field plate electrode of the first transistor and a desired second field plate voltage to the field plate electrode of the second transistor. The desired first field plate voltage and the desired second field plate voltage are configured to at least partially deplete charge carriers in channel regions of the first transistor and the second transistor near the field plate electrodes of the first transistor and the second transistor, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is illustrated by way of examples, embodiments, etc., and is not limited by the drawings, in which like reference numerals indicate like elements. For simplicity and clarity, the elements in the figures are shown, and these elements are not necessarily drawn to scale. The drawings are incorporated with the detailed description and form a part of the specification and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages in accordance with the present disclosure, wherein:

[0010] Figure 1 is a circuit diagram of an integrated circuit according to one or more embodiments herein.

[0011] Figure 2 is a schematic cross-sectional view of a transistor suitable for use in one or more embodiments.

[0012] Figure 3 is a top plan view of a transistor with integrated field plate bias circuitry according to one or more embodiments.

[0013] Figure 4 is a block level schematic diagram of a Doherty amplifier circuit including field plate bias circuitry according to one or more embodiments. DETAILED DESCRIPTION

[0014] The following detailed description provides examples for the purpose of understanding and is not intended to limit the invention or the application and use of the invention. In addition, it is not intended to be bound by any express or implied theory presented in the previous technical field, background technology or the following detailed description.

[0015] For simplicity and clarity of explanation, the drawings show the general construction mode, and the description and details of well-known features and technologies may be omitted so as not to unnecessarily obscure the present invention. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the sizes of some elements or regions in the drawings may be exaggerated relative to other elements or regions to help improve the understanding of the embodiments of the present invention.

[0016] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims can be used to distinguish similar elements and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this way are interchangeable in appropriate circumstances, so that the embodiments of the present invention described herein (for example) can operate in a sequence other than the sequence described or otherwise described herein. In addition, the terms "including", "having" and any variants thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device including a series of elements is not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such processes, methods, articles or devices. The term "coupled" as used herein is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practicable manner, and minor defects (if any) are not important for the stated purpose.

[0017] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are made for illustrative purposes with reference to the orientation of one or more corresponding figures.

[0018] It should be understood that the steps of the various processes described herein are non-limiting examples of suitable processes according to the embodiments and are for illustrative purposes. The systems and devices according to the embodiments herein can use any suitable process, including processes that omit the steps described above, processes that perform those steps and similar steps in a different order, and the like. It should also be understood that well-known features may be omitted for clarity.

[0019] It should be understood that the references herein to radio frequency (RF) signals and RF devices are not intended to limit the embodiments herein to operating at any particular frequency or frequency range. For example, as used herein, radio frequency can refer to a time-varying signal in any suitable frequency band, including (but not limited to) microwave frequencies (~300 MHz - 300 GHz), millimeter wave frequencies (i.e., 30 - 300 GHz), etc.

[0020] It should be understood that although the current terminals of the transistors described herein may be referred to by conventional names associated with field effect transistors, etc. (such as "source" and "drain"), the embodiments herein can employ any suitable transistor technology, including those in which the terms "source" and "drain" are not used. It will be further understood that the source terminal and the drain terminal can be interchangeable, depending on how the transistor is connected within a larger circuit.

[0021] RF power transistors and other high-frequency power transistors used in amplifier applications typically use a source-connected field plate to modify the field between the gate and the drain. For GaN high electron mobility transistors (HEMTs), an important function of this field plate is to deplete the channel adjacent to the gate to reduce the gate-drain capacitance (C GD ); such depletion and the associated C GD reduction are necessary for achieving competitive gain. The design of the field plate inherently involves many trade-offs between performance, reproducibility, manufacturability, and the gate-drain and gate-source capacitances.

[0022] As an example of a trade-off, the ability of the field plate to deplete the channel between the gate and the drain depends on the thickness of the dielectric between the field plate and the channel. Reducing the dielectric thickness improves the ability to deplete the channel, but it also increases the unwanted drain-source capacitance (C DS ); and in most GaN HEMT process flows, it also introduces additional unwanted gate-source capacitance (C GS)。The C can be alleviated to some extent by reducing the length of the field plate as the dielectric thickness decreases DS trade-off; however, as the field plate length decreases, manufacturability and reproducibility become more challenging. If another degree of freedom can be introduced into the design to alleviate such fundamental trade-offs, then by reducing the C DS and C GS channel depletion under the field plate can be achieved, thereby providing significantly improved performance. The ability to independently control the potential of the field plate electrode can introduce an additional degree of freedom, which can achieve various advantages described further below. However, previous circuit designs may have drawbacks that must be overcome. First, existing circuit designs typically do not include connections for supplying a field plate voltage different from the source, gate, and drain voltages. In addition, providing a different potential for the field plate externally (i.e., from outside the package) would require a separate lead in the product package. In addition, high-power HEMTs typically employ multiple parallel "fingers" to support large currents. If there are more than two such fingers, it may not be practical to uniformly distribute this different potential to all individual field plate fingers of the device across the entire die in typical compound semiconductor technologies (such as GaN and GaAs) that typically have only one or two levels of interconnect metal. In such technologies, the distribution of different field plate potentials would require signal crossovers, which would introduce undesirable parasitic capacitances and complex feedback paths. One solution is to add another layer of interconnect metal. This would reduce the undesirable parasitic capacitances, but the process cost and complexity would increase.

[0023] Although it is possible to have additional input connections to support a circuit for controlling the field plate voltage, such a circuit would introduce increased complexity for the circuit designer and the end user. One solution to this problem is to include another bias generation circuit in the packaged device, which can use a charge pump driven by an oscillator circuit to generate the negative voltage required to drive the independent field plate. However, the charge pump inevitably introduces noise at its operating frequency, and steps must be taken to filter this noise, thereby increasing even more cost and complexity. In addition, this method also does not solve the problem of uniformly distributing the negative potential across the entire power transistor die, which typically does not include multiple interconnect layers.

[0024] Thus, the devices and methods according to embodiments herein allow radio frequency, microwave, and other high-frequency transistor circuits (including HEMT-based circuits) that utilize the time-varying output voltage present during the operation of RF amplifier and switch circuits to power a negative voltage supply suitable for controlling the field plate without introducing excessive noise or requiring excessive power consumption.

[0025] Figure 1is a circuit diagram of an example circuit including a self - biasing field plate according to one or more embodiments. Circuit 100 is configured to operate as a radio frequency (RF) amplifier circuit and includes an input port 110 (labeled "RF IN") configured to receive a time - varying input signal and an output port 190 (labeled "RF OUT") configured to output an amplified signal corresponding to the input signal. Circuit 100 also includes a gate bias input 112 and a drain bias input 114. Circuit 100 includes a transistor 120, which includes a first current terminal (i.e., drain 124) and a second current terminal (i.e., source terminal 122) separated by a semiconductive channel region 123. Resistor R D represents the output resistance of transistor 120. Transistor 120 has a first control terminal electrically coupled to the semiconductive channel region 123 (i.e., gate 125) and a second control terminal (i.e., field plate 127) also electrically coupled to the semiconductive channel region 123 and disposed between the gate 125 and the drain 124.

[0026] The gate 125 of transistor 120 is configured to receive a gate bias ("V GS ") via the gate bias input 112. A radio frequency (RF) input signal (represented as "V RF ") can be superimposed on the gate bias. As shown, the signals received at inputs 110, 112 can be combined via a coupling circuitry 113 (e.g., a bias tee circuit), which can form part of circuit 100 or can be external to circuit 100. A DC drain bias voltage ("V DS ") can be applied to the drain 124 of transistor 120 via the drain bias input 114. As shown, a coupling circuitry 115 (e.g., a bias tee circuit) can be used to apply the drain bias V DS to the drain bias input 114 without affecting the output port 190, which can form part of circuit 100 or can be external to circuit 100.

[0027] In Figure 1 the example, transistor 120 operates in a common - source configuration, in which the source terminal is grounded. Thus, a voltage described as negative in connection with circuit 100 is a voltage less than the potential of the source terminal 122. It should be understood that nothing herein is intended to require an absolute reference potential value. It will also be understood that nothing herein is intended to limit the embodiments herein to transistors operating in a common - source configuration or a similar configuration.

[0028] The circuit 100 further includes a field plate bias circuit system 150 coupled between the drain 124 of the transistor 120 (which is coupled to the output port 190 of the circuit 100) and the field plate 127. The field plate bias circuit system 150 is capacitively coupled to the output of the transistor 120 at the input node 152 of the field plate bias circuit system 150. The output node 155 of the field plate bias circuit system 150 is coupled to the field plate 127 of the transistor 120. The field plate bias circuit system 150 is configured to "harvest" electrical energy from the time-varying output of the transistor 120 and use the energy to generate a constant negative voltage sufficient to bias the field plate 127 at the output node 155 of the field plate bias circuit system 150, provided that the signal amplitude at the output node 190 of the circuit is large enough.

[0029] Figure 1 The field plate bias circuit system 150 is a non-limiting example of a circuit system suitable for use as a field plate bias circuit. It should be understood that any suitable circuit system or other device may be used in the embodiments herein. In this example, the input capacitor ("C IN ") is coupled to the output capacitor ("C OUT ") through voltage rectifying elements (diodes D1 and D2 in this example) in a charge pump configuration. When the AC-coupled voltage at node 153 is negative with respect to the reference potential ("ground"), current flows out of C OUT via D2, resulting in a negative voltage being generated across C OUT . At the same time, when the AC-coupled voltage at node 153 is positive with respect to the reference potential, the current is diverted to ground via D1 and D2 is turned off, thus preventing C OUT from discharging. The overvoltage regulating element 154 is configured to partially discharge C OUT to ground in the case where the negative voltage across C OUT becomes more negative than the desired negative voltage at the output node 155 of the field plate bias circuit system 150. In this example, the overvoltage regulating element 154 is a set of N diodes connected in series. If the forward turn-on voltage of each diode is V F , the negative voltage at the output node 155 with respect to the reference potential will not become more negative than -(N × V F ).

[0030] A field plate biasing circuit system (such as field plate biasing circuit system 150) can operate using a small portion of the RF power generated at the output node 190 of a circuit (such as circuit 100). For example, in a representative GaN HEMT with a 1 mm gate perimeter operating at 48 V, the RF output power can be 5 W, the RF input power is 50 mW, and the average drain current is 170 mA, corresponding to a power added efficiency ("PAE") of 60.66%. At the same time, the additional current consumption of an integrated field plate biasing circuit system such as field plate biasing circuit system 150 can be much lower than 0.1 mA. In this example, if the worst-case value is assumed to be 0.1 mA, the PAE will decrease from 60.66% to 60.63%, which is a negligible decrease for many applications.

[0031] It should be understood that the simple voltage regulation method shown in Figure 1 can be modified to allow control of the desired output voltage at output node 155. For example, a switching element can be applied to bypass one or more diodes of the overvoltage regulation element 154 of the field plate biasing circuit system 150, thereby allowing adjustment of the desired negative output voltage in increments of V F . It will be further understood that any other suitable circuits and techniques can be used in the embodiments herein to provide a variable negative voltage at the output node 155 of the field plate biasing circuit system 150.

[0032] As a non-limiting example, the desired output voltage of a field plate control circuit system (such as field plate biasing circuit system 150) can be changed based on the amplitude of the RF output signal at the output of a transistor circuit (such as circuit 100) or by an externally supplied control signal. In these embodiments, the field plate potential can be used to dynamically modify the operating characteristics of a transistor such as transistor 120 during the operation of circuit 100 to achieve the desired operating characteristics for different scenarios. For example, in certain applications, it may be necessary to flatten the gain curve of a transistor such as transistor 120, or to tune the response of the output phase modulation of the transistor to the input amplitude modulation (AM-PM) characteristics to achieve improved output power linearity over a given range of output power levels. As another example, in certain applications, it may be necessary to increase the transistor output gain under low drain bias voltage (V DD ) conditions to support drain modulation and thereby improve efficiency, and so on.

[0033] In one or more embodiments, a transistor such as transistor 120 is a high electron mobility transistor (HEMT), where a two-dimensional electron gas ("2DEG") forms a conductive channel controlled by a first control terminal (such as gate 125 or gate electrode 125) and a second control terminal (i.e., field plate 127 or field plate electrode 127). Figure 2It is a simplified cross-sectional view of the HEMT 220. The cross-section shown passes through the drain electrode 224, the gate electrode 225, the field plate electrode 227, and the source electrode 222. As shown, the field plate electrode is configured to receive a bias voltage input from a field plate bias circuit system (such as the field plate bias circuit system 150). In one or more embodiments, another electrode or other conductive feature forms part of a field plate control circuit system such as the field plate bias circuit system 150. In Figure 2 the example of, an electrode 252 separated from the source electrode 222 by a dielectric material forms a capacitor (e.g., the capacitance C of the field plate bias circuit system 150 OUT ).

[0034] In this simplified example, the channel region 250 is formed on or within the substrate 295 by a semiconductor heterostructure including three layers, which will be described as an example in the context of a GaN HEMT. The channel region 250 is formed by a nucleation layer 250a (e.g., an aluminum nitride layer), followed by a buffer layer 250b (e.g., an epitaxial layer or multiple epitaxial layers of gallium nitride) and a barrier layer 250c (e.g., an insulating aluminum nitride / gallium nitride alloy). The 2DEG 223 is formed at the interface between the buffer layer 250b and the barrier layer 250c. Generally, for a GaN HEMT device, the substrate 295 can be silicon, silicon carbide, sapphire, or any other suitable material. In regions where the conductive 2DEG is not desired, one or more layers of the channel region 250 can be modified to prevent the formation of the 2DEG, thereby making the region highly resistive or electrically insulating using any suitable method (as non-limiting examples, including photolithographic patterning, doping, and / or disrupting the interface via ion implantation).

[0035] In one or more embodiments, additional circuit elements (e.g., all or part of a field plate bias circuit such as the field plate bias circuit 150) are integrally formed within the same substrate as a transistor such as the transistor 220 (e.g., the transistor 120). For example, it should be understood that capacitors and diodes can be formed by selectively patterning one or more layers formed on or within a substrate such as the substrate 295 to form capacitors, diodes, etc. It should be further understood that such structures can also be formed from any suitable combination of semiconductor materials and metals. For example, a Schottky diode can be formed at a suitable metal-semiconductor interface.

[0036] Figure 3is a top plan view of an example integrated circuit in accordance with one or more embodiments, where transistors are provided with an integrated field plate biasing circuit (e.g., field plate biasing circuit 150). The integrated circuit 300 is formed on a substrate 395 that is wholly or partially composed of a semiconductor material (e.g., silicon, silicon carbide (SiC), or other suitable semiconductor material). In one or more other embodiments, a substrate such as substrate 395 includes other materials such as sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), diamond, boron nitride (BN), polycrystalline SiC, silicon-on-insulator, gallium arsenide (GaAs), indium phosphide (InP), and / or other generally insulating or high resistivity materials.

[0037] The integrated circuit 300 includes transistors 320 (e.g., transistor 120 or 220). As shown, the transistor 320 is a field effect transistor (FET) defined by multiple segments (“fingers”) that form the ends of the device. The transistor 320 has source fingers 322 (‘S’), drain fingers 324 (‘D’), gate fingers 325 (‘G’), and field plate fingers 327 (‘F’). Each of the source fingers 322, drain fingers 324, gate fingers 325, and field plate fingers 327 is formed of a conductive material (e.g., gold, copper, titanium, aluminum, nickel, etc.) disposed at a first surface of the substrate 395. The drain fingers 324 of the transistor 320 are electrically coupled to a drain pad 314 (e.g., a drain bond pad) and the gate fingers 325 are electrically coupled to a gate pad 315 (e.g., a gate bond pad). It should be understood that these fingers are coupled to the corresponding portions of the transistor 320 that operate as a source, gate, field plate, and drain.

[0038] In this example, the source fingers 322 of the transistor 320 are electrically coupled to a conductive material layer (“reference plane”, not shown) disposed at a second surface of the substrate 395 and configured to be biased to a reference potential (“ground”) during operation. The source fingers 322 of the transistor 320 are electrically coupled to the reference plane through a through-substrate via (TSV) 392. Each TSV 392 corresponds to an opening (e.g., a hole) in the substrate 395 that extends between one of the source fingers 322 and the reference plane and includes a conductive material that provides an electrical connection between the source finger 322 and the reference plane.

[0039] The transistor 320 also includes discrete field plate biasing circuits 350 (e.g., field plate biasing circuit 150) distributed across the substrate 395, where each field plate biasing circuit 350 is coupled to a pair of adjacent field plate fingers 327 or a single field plate finger 327. Using individual field plate biasing circuits 350 each coupled to a small number of field plate fingers 327 (or one such finger) can help reduce the likelihood that the field plate fingers are unevenly biased across the substrate 395. As Figure 3 shown, field plate biasing circuits such as field plate biasing circuit 350 can be integrated into existing transistor designs without increasing the total footprint of the transistors on the substrate. It should be understood that the circuits according to embodiments herein can have any suitable number of source, drain, gate, and field plate fingers. Along these lines, individual field plate biasing circuits according to embodiments herein can be coupled to any suitable number of field plate fingers, subject to design rules and desired performance characteristics.

[0040] In one or more embodiments, a field plate biasing circuit system (e.g., field plate biasing circuit system 150 and / or field plate biasing circuit 350) is capacitively coupled to the output of a transistor such as transistor 120, 220, or 320. In the example of a GaN HEMT such as transistor 220 or 320, the conductive material under a portion of the drain finger (e.g., drain finger 324) or drain pad (e.g., drain pad 314) can form an input capacitance (e.g., input capacitance C of the field plate biasing circuit system 150) for the field plate biasing circuit system. IN ) for the field plate biasing circuit system. Along these lines, diodes (e.g., diodes D1 and D2 of the field plate biasing circuit system 150) and separate capacitors can be connected to the conductive material forming a part of the input capacitance such that the time-varying potential on the drain pad (e.g., drain pad 314 during normal RF operation of the transistor 320) causes a negative potential across the output capacitance (i.e., in this example, output capacitance C of the field plate biasing circuit system 150). OUT ) of the field plate biasing circuit system. The negative voltage across the output capacitance is in turn supplied to a second part of one or more circuits (e.g., overvoltage regulating element 154 of the field plate biasing circuit system 150, represented by a string of diodes in Figure 1 ) which regulates the negative voltage to a desired level and supplies the desired negative field plate biasing voltage to one or more field plates (e.g., field plate 127, field plate 227, or one or more field plate fingers 327).

[0041] It should be understood that a transistor circuit having an integrated field plate control circuit system (e.g., field plate bias circuit systems 150, 350) according to embodiments herein can have various desirable characteristics and advantages over prior methods that require a dedicated oscillator circuit and / or those that require an externally supplied field plate bias signal. For example, since the field plates in embodiments herein do not have a DC connection to the current-carrying portions of devices such as circuit 100 or circuit 300, such field plates only require a DC current amount sufficient to cancel out the leakage current within the input capacitance of the field plate bias circuit system (e.g., the input capacitance C IN )). When the input capacitance is implemented as a metal-insulator-metal capacitor (e.g., as described for circuit 300 above in connection with Figure 3 ), these currents can be safely assumed to be in the μA / mm range as long as the field plate potential remains well below the breakdown voltage of the input capacitance (typically > 100V). Since this current is many orders of magnitude lower than the RF drain current in a power FET (e.g., transistor 120, 220, or 320), but at the same frequency, the additional noise attributable to this current is not significant compared to the existing noise present at the output during operation.

[0042] Incorporating the output capacitance of the field plate bias circuit system (C OUT ) into one or more source fingers of a circuit (e.g., circuit 300) means that no additional inductance is added to any field plate compared to prior methods that lack a field plate bias circuit system (e.g., field plate bias circuit systems 150 or 350). Furthermore, the lack of this additional inductance makes this method more attractive than a field plate of circuit 300 controlled by an externally supplied voltage, since additional inductance would otherwise be introduced by the presence of additional leads and signal lines.

[0043] The transistor and field plate bias circuit system according to embodiments herein are applicable to various circuits, including both single-path amplifier circuits and Doherty amplifier circuits, which include a carrier amplifier path and a peak amplifier path, the carrier amplifier path being configured to amplify an RF input signal when the input signal is within a first power range, and the peak amplifier path being configured to amplify the input signal when the input power increases beyond the first power range. Figure 4A simplified block diagram of a Doherty amplifier circuit 400 is shown, the Doherty amplifier circuit 400 including an RF input 410 and an RF output 490. The RF input signal is coupled to a carrier amplifier 420A and a peak amplifier 420B via an input splitter 415. The output of the carrier amplifier 420A and the output of the peak amplifier 420B are coupled to the RF output 190 via a power combiner 430. In this example, the carrier amplifier 420A and the peak amplifier 420B include transistors (e.g., transistors 120, 220, or 320) according to embodiments herein that are provided with field plates (e.g., field plates 127, 227, and / or field plate fingers 327). A field plate biasing circuitry 450A (e.g., field plate biasing circuitry 150 or 350) is coupled to the output node of the carrier amplifier 420A and provides a negative field plate bias voltage to the transistors of the carrier amplifier 420A. A field plate biasing circuitry 450B (e.g., field plate biasing circuitry 150 or 350) is coupled to the output node of the peak amplifier 420B and provides a negative field plate bias voltage to the transistors of the peak amplifier 420B.

[0044] Embodiments herein can be applied to both single-ended amplifier devices and Doherty amplifier devices (e.g., Doherty amplifier circuit 400), even in cases where back-off operation is typical. As an example, a representative carrier amplifier of the carrier amplifier 420A biased at V DD = 48V can produce a peak-to-valley voltage swing of approximately 28V at 10 dB below saturation. Since the charge pump is capable of delivering a potential shift equal to the amplitude of the peak-to-valley swing minus any applicable diode voltage drop, a target potential of up to -25V can be achieved under back-off operation of a carrier device such as the carrier amplifier 420A. This is because the input capacitance of the field plate biasing circuitry (e.g., field plate biasing circuitry 150, 350, 450) can be configured to hold the desired negative voltage output during a period when the output power can be significantly below 10 dB below saturation, limited only by the leakage of its input capacitance.

[0045] Embodiments herein are also suitable for use with peak amplifier devices such as the peak amplifier 420B, which can have improved C due to the negatively biased field plates DSto achieve improved bandwidth. Although the peak amplifier in the Doherty amplifier is often turned off, the output of the Doherty amplifier is coupled to the outputs of both the carrier amplifier and the peak amplifier (see carrier amplifier 420A and peak amplifier 420B coupled to power combiner 430). Thus, when a field plate biasing circuit system, such as field plate biasing circuit systems 150, 350, 450A, 450B, etc., is coupled to the output node of the Doherty amplifier, even when the input signal lacks the amplitude required to turn on the peak amplifier, the field plate biasing circuit system can use the output power generated by the carrier amplifier to provide a suitable negative bias voltage to the transistors used in the peak amplifier.

[0046] Accordingly, it should be understood that a Doherty amplifier according to an embodiment of the present disclosure may include one or more transistors having a field plate biasing circuit system (e.g., field plate biasing circuit system 150, 350, or 450) in the peak signal path, the carrier signal path, or both signal paths (e.g., the Doherty amplifier can be modified to omit field plate biasing circuit 450A or omit field plate biasing circuit system 450B). Such a field plate biasing circuit system can be powered by any suitable power source. For example, in one or more embodiments, the field plate biasing circuit system is directly powered by the RF output of the transistor to which it is coupled. At the same time, in one or more other embodiments, the field plate biasing circuit system is powered by another RF output signal. For example, Doherty amplifier 400 can be modified to couple field plate biasing circuit system 450A to RF output node 490 instead of directly coupling it to the output of carrier amplifier 420A. For example, Doherty amplifier 400 can be modified to couple field plate biasing circuit system 450B to RF output node 490 instead of directly coupling it to the output of carrier amplifier 420B.

[0047] It should be understood that although embodiments herein may be described with reference to a particular transistor circuit or a particular transistor type (e.g., a common-source transistor circuit and an n-type HEMT operating as a depletion-mode device, where the channel region is conductive unless a suitable bias is applied to deplete the channel), nothing herein is intended to limit the embodiments to any particular circuit topology or transistor type. For example, in one or more embodiments, a p-type depletion-mode transistor is used instead of an n-type device, and it should be understood that in such embodiments, the voltages applied to the gate electrode of the transistor and the field plate electrode of the transistor will conventionally be described as positive with respect to the potential of the source terminal or other reference potential. Similarly, in one or more embodiments, the transistor operates as an enhancement-mode device rather than a depletion-mode device. In such embodiments, it should be understood that the bias voltage applied to the gate of the transistor will have a polarity opposite to that of the field plate electrode, since the total conductivity of the channel is modulated by the gate voltage, which is configured to increase the carrier concentration in the channel, while the field plate electrode should be biased to reduce the carrier concentration near the field plate electrode (i.e., at least partially deplete the channel) in order to achieve improved breakdown voltage characteristics of the device).

[0048] It will be further understood that the field plate electrode according to embodiments herein can be biased by any suitable bias source. For example, the field plate bias circuit system according to an embodiment can include any suitable DC voltage source. As another example, the field plate bias circuit system according to an embodiment can be powered by an external RF signal, or by an RF signal generated by a transistor or other device directly coupled to the source rather than the field plate bias circuit system.

[0049] Various examples

[0050] The features of the embodiments can be understood by one or more of the following examples: After the claims are approved, a formal claim summary will be inserted here.

[0051] Example 1: An apparatus or a method of manufacturing an apparatus, the apparatus including: an input node and an output node; a transistor and a field plate bias circuit system. The transistor includes: a first current terminal coupled to the output node; a second current terminal; a semiconducting channel region disposed between the first current terminal and the second current terminal; a gate electrode electrically coupled to the semiconducting channel region and coupled to the input node; and a field plate electrode electrically coupled to the semiconducting channel region and disposed adjacent to the gate electrode. The field plate bias circuit system is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode, the field plate bias voltage at least partially depleting the channel region of charge carriers near the field plate electrode.

[0052] Example 2: The apparatus or method according to Example 1, wherein the field plate electrode is disposed between the gate electrode and the first current terminal.

[0053] Example 3: The apparatus or method according to Example 1 or Example 2, wherein the field plate biasing circuit system is coupled between the second current terminal and the output node, and the field plate biasing circuit system is configured to generate a field plate biasing voltage to the field plate electrode in response to a time-varying voltage at the output node.

[0054] Example 4: The apparatus or method according to any one of Examples 1-3, wherein the field plate biasing circuit system includes a charge pump circuit, the charge pump circuit being powered by the time-varying voltage at the output node and being configured to generate the desired field plate biasing voltage.

[0055] Example 5: The apparatus or method according to any one of Examples 1-4, wherein at least a portion of the transistor and the field plate biasing circuit system are integrally formed within the semiconductor material of a single semiconductor substrate.

[0056] Example 6: The apparatus or method according to any one of Examples 1-5, wherein the field plate biasing voltage is generated by the field plate biasing circuit system in response to the time-varying voltage at the output node having at least a predetermined minimum amplitude.

[0057] Example 7: The apparatus or method according to any one of Examples 1-6, wherein the transistor includes at least a first drain finger and a second drain finger coupled to the first current terminal; a first source finger and a second source finger coupled to the second current terminal; a first gate finger and a second gate finger coupled to the first control terminal; and a first field plate finger and a second field plate finger; and wherein the field plate biasing circuit system includes: a first field plate biasing circuit coupled to the first field plate finger and configured to supply a first predetermined field plate finger biasing voltage to the first field plate finger; and a second field plate biasing circuit coupled to the second field plate finger and configured to supply a second field plate finger biasing voltage to the second field plate finger.

[0058] Example 8: The apparatus or method according to any one of Examples 1-7, wherein the first field plate finger biasing voltage is equal to the second field plate finger biasing voltage.

[0059] Example 9: The apparatus or method according to any one of Examples 1-8, wherein the first field plate biasing circuit includes an input capacitance that couples the first drain finger to the first field plate biasing circuit.

[0060] Example 10: The apparatus or method according to any one of Examples 1-9, wherein the first field plate biasing circuit includes an output capacitance coupled between a first source finger and a first field plate finger; wherein the output capacitance of the first field plate biasing circuit has a first capacitor terminal formed by at least a portion of the first source finger.

[0061] Example 11: The apparatus or method according to any one of Examples 1-10, wherein the transistor is a high electron mobility transistor (HEMT), and the channel region includes a semiconductor heterostructure configured to form a two-dimensional electron gas (2DEG) at a buried semiconductor heterojunction within the semiconductor heterostructure.

[0062] Example 12: The apparatus or method according to any one of Examples 1-11, wherein the field plate biasing circuit system includes: an input capacitance and an output capacitance; wherein the input capacitance is coupled between the first current terminal and the output capacitance; wherein the output capacitance is coupled between an output node of the field plate biasing circuit system and a reference potential node.

[0063] Example 13: The apparatus or method according to any one of Examples 1-12, wherein the field plate biasing circuit system further includes: a voltage regulation circuit system configured to prevent the magnitude of the voltage across the output capacitance from exceeding a desired field plate biasing voltage.

[0064] Example 14: The apparatus or method according to any one of Examples 1-13, wherein the field plate biasing circuit system is configured to make the potential of the field plate electrode lower than the respective potentials of the first current terminal, the second current terminal, and the gate electrode.

[0065] Example 15: An apparatus or a method of forming an apparatus, the apparatus including: an input node configured to receive a radio frequency (RF) input signal; an output node configured to output an amplified signal corresponding to the RF input signal; a carrier amplifier signal path; a peak amplifier signal path; and a field plate biasing circuit system. The carrier amplifier signal path includes a first transistor configured to amplify the RF input signal within a first input power range of the RF input signal. The peak amplifier signal path includes a second transistor configured to further amplify the RF input signal within a second input power range of the RF input signal.

[0066] The first transistor includes a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconductive channel, and configured to modulate the output of the transistor in response to an RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconductive channel.

[0067] The second transistor includes a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconductive channel, and configured to modulate the output of the transistor in response to an RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconductive channel.

[0068] A field plate biasing circuit system is coupled to the field plate electrodes of the first and second transistors, and is configured to apply a desired first field plate voltage to the field plate electrode of the first transistor and a desired second field plate voltage to the field plate electrode of the second transistor. The desired first field plate voltage and the desired second field plate voltage are configured to at least partially deplete the channel regions of the first and second transistors of charge carriers near the field plate electrodes of the first and second transistors, respectively.

[0069] Example 16: The apparatus or method according to Example 15, wherein the field plate biasing circuit system is powered by an amplified signal at an output node of the apparatus.

[0070] Example 17: An apparatus or a method of forming an apparatus, the apparatus including: an input node configured to receive a radio frequency (RF) input signal; an output node configured to output an amplified signal corresponding to the RF input signal; a transistor configured to amplify the RF input signal; and a field plate biasing circuit system.

[0071] The transistor includes a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconductive channel, and configured to modulate the output of the transistor in response to an RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconductive channel.

[0072] The field plate bias circuit system is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode, the field plate bias voltage at least partially depleting a channel region of charge carriers near the field plate electrode.

[0073] Example 18: The apparatus or method according to Example 17, wherein the second current terminal is coupled to a reference potential node (“ground node”), and the transistor is a depletion mode transistor configured to operate in an “on” state when the gate electrode is biased to a gate potential that is negative with respect to the ground node. The field plate bias circuit system is configured to bias the field plate electrode to a field plate potential that is negative with respect to the potential of the ground node and different from the gate potential.

[0074] Example 19: The apparatus or method according to Example 18, wherein the field plate potential is more negative than the gate potential with respect to the potential of the ground node.

[0075] Example 20: The apparatus or method according to Example 17, wherein the second current terminal is coupled to a reference potential node (“ground node”), and the transistor is a depletion mode transistor configured to operate in an “on” state when the gate electrode is biased to a gate potential that is positive with respect to the ground node. The field plate bias circuit system is configured to bias the field plate electrode to a field plate potential that is positive with respect to the potential of the ground node and different from the gate potential.

[0076] Example 21: The apparatus or method according to Example 20, wherein the field plate potential is more positive than the gate potential with respect to the potential of the ground node.

[0077] Example 22: The apparatus or method according to Example 17, wherein the second current terminal is coupled to a reference potential node (“ground node”). The transistor is an enhancement mode transistor configured to operate in an “on” state when the gate electrode is biased to a gate potential that is positive with respect to the ground node; and the field plate bias circuit system is configured to bias the field plate electrode to a field plate potential that is negative with respect to the potential of the ground node.

[0078] Example 23: The apparatus or method according to Example 17, wherein the second current terminal is coupled to a reference potential node (“ground node”). The transistor is an enhancement mode transistor configured to operate in an “on” state when the gate electrode is biased to a gate potential that is negative with respect to the ground node; and the field plate bias circuit system is configured to bias the field plate electrode to a field plate potential that is positive with respect to the potential of the ground node.

[0079] The foregoing detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration". Any embodiment described herein as exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background technology, or detailed description.

[0080] It should be understood that the application of the present invention is not limited to the details of the construction and arrangement of the components set forth in the foregoing description or shown in the accompanying drawings. The present invention can have other embodiments and can be practiced or executed in various ways. And, it should be understood that the words and terms used herein are for the purpose of description and should not be considered as restrictive. The use of "including" or "having" and its variations herein is intended to cover the items listed thereafter and their equivalents and additional items. Unless otherwise specified or limited, the terms "install", "connect", "support" and "couple" and their variations are used in a broad sense and cover direct and indirect installation, connection, support and coupling. In addition, "connect" and "couple" are not limited to physical or mechanical connections or couplings.

[0081] The previous discussion is presented to enable those skilled in the art to make and use embodiments of the present invention. Various modifications to the illustrated embodiments will be apparent to those skilled in the art, and the general principles herein may be applied to other embodiments and applications without departing from embodiments of the present invention. Therefore, embodiments of the present invention are not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed herein. Previous specific embodiments should be read with reference to the drawings, in which similar elements in different figures have similar reference numerals. The drawings, which are not necessarily drawn to scale, depict selected embodiments, and do not wish to limit the scope of embodiments of the present invention. Those skilled in the art will recognize that the examples provided herein have many useful alternatives and fall within the scope of embodiments of the present invention.

[0082] The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the subject matter. In addition, certain terms may also be used herein only for reference purposes, and therefore do not wish to be restrictive, and unless the context clearly indicates, the terms "first", "second" and other such numerical terms referring to structures do not imply a sequence or order.

[0083] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that an element is directly joined to another element (or directly in communication with another element) and need not be mechanical. Similarly, unless otherwise expressly stated, "coupled" means that an element is directly or indirectly joined to another element (or directly or indirectly in electrical or other communication with another element) and need not be mechanical. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in one or more embodiments of the subject matter depicted.

Claims

1. An electronic device, characterized in that: include: Input nodes and output nodes; A transistor, the transistor comprising: a first current terminal coupled to the output node; a second current terminal; a semiconductive channel region disposed between the first current end and the second current end; a gate electrode electrically coupled to the semiconducting channel region and to the input node; a field plate electrode electrically coupled to the semiconducting channel region and disposed adjacent to the gate electrode; and Field plate bias circuitry is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode that at least partially depletes the channel region of charge carriers proximate the field plate electrode.

2. The device according to claim 1, characterized in that The field plate electrode is disposed between the gate electrode and the first current terminal.

3. The device according to claim 1, characterized in that The field plate bias circuitry is coupled between the second current terminal and the output node; The field plate bias circuitry is configured to generate the field plate bias voltage to the field plate electrode in response to a time varying voltage at the output node.

4. The device according to claim 3, characterized in that The field plate bias circuitry includes a charge pump circuit powered by the time-varying voltage at the output node and configured to generate the desired field plate bias voltage.

5. The device according to claim 3, characterized in that The transistor and at least a portion of the field plate bias circuitry are integrally formed within semiconductor material of a single semiconductor substrate.

6. The device according to claim 3, characterized in that The field plate bias voltage is generated by the field plate bias circuitry in response to the time varying voltage at the output node having at least a predetermined minimum amplitude.

7. The device according to claim 1, characterized in that The transistor comprises at least: a first drain finger and a second drain finger coupled to the first current terminal; a first source finger and a second source finger coupled to the second current terminal; first and second gate fingers coupled to the first control terminal; and a first field plate finger and a second field plate finger; and The field plate bias circuit system comprises: a first field plate bias circuit coupled to the first field plate fingers and configured to supply a first predetermined field plate finger bias voltage to the first field plate fingers; and A second field plate bias circuit is coupled to the second field plate fingers and is configured to supply a second field plate finger bias voltage to the second field plate fingers.

8. The device according to claim 1, characterized in that The transistor is a high electron mobility transistor (HEMT), and the channel region includes a semiconductor heterostructure configured to form a two-dimensional electron gas (2DEG) at a buried semiconductor heterojunction within the semiconductor heterostructure.

9. An amplifier device, characterized in that: include: an input node configured to receive a radio frequency (RF) input signal; an output node configured to output an amplified signal corresponding to the RF input signal; a transistor configured to amplify the RF input signal, wherein the transistor comprises: a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconducting channel and configured to modulate an output of the transistor in response to the RF input signal; and a field plate electrode adjacent to the gate electrode and also coupled to the semiconducting channel; and Field plate bias circuitry is coupled to the field plate electrode and is configured to apply a desired field plate bias voltage to the field plate electrode that at least partially depletes the channel region of charge carriers proximate the field plate electrode.

10. A Doherty amplifier, characterized in that: include: an input node configured to receive a radio frequency (RF) input signal; an output node configured to output an amplified signal corresponding to the RF input signal; A carrier amplifier signal path, the carrier amplifier signal path comprising: a first transistor configured to amplify the RF input signal within a first input power range of the RF input signal, wherein the transistor comprises: a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconducting channel and configured to modulate an output of the transistor in response to the RF input signal; a field plate electrode adjacent to the gate electrode and also coupled to the semiconducting channel; and A peaking amplifier signal path, the peaking amplifier signal path comprising: a second transistor configured to further amplify the RF input signal within a second input power range of the RF input signal, wherein the second transistor comprises: a first current terminal; a second current terminal; a semiconductive channel coupled between the first current terminal and the second current terminal; a gate electrode disposed between the first current terminal and the second current terminal and coupled to the semiconducting channel and configured to modulate an output of the transistor in response to the RF input signal; a field plate electrode adjacent to the gate electrode and also coupled to the semiconducting channel; and field plate bias circuitry coupled to the field plate electrodes of the first transistor and the second transistor; wherein the field plate bias circuitry is configured to apply a desired first field plate voltage to the field plate electrode of the first transistor and to apply a desired second field plate voltage to the field plate electrode of the second transistor; and Wherein the desired first field plate voltage and the desired second field plate voltage are configured to at least partially deplete the channel regions of the first transistor and the second transistor of charge carriers proximate the field plate electrodes of the first transistor and the second transistor, respectively.

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