NMOS (N-channel metal oxide semiconductor) structure uniformly opened by substrate triggering

Abstract

The invention discloses an NMOS (N-channel Metal Oxide Semiconductor) structure uniformly opened by substrate triggering. The NMOS structure comprises a P-type substrate, a first P-type well doped type well region, a plurality of N-type heavily doped active regions, a polysilicon gate, an edge P-type heavily doped active region, a second P-type well doped type well region, a P-type high-voltage doped well region and a P-type deep doped well region, the edge P-type heavily-doped active region, the second P-type well doped well region and the P-type high-voltage doped well region are sequentially injected into the P-type substrate from top to bottom and are all arranged in an annular structure, and the edge P-type heavily-doped active region surrounds the annular N-type heavily-doped active region; the P-type deep doped well region is injected into the P-type substrate, and the edge of the P-type deep doped well region extends to the bottom end of the P-type high-voltage doped well region. Through the specific doping structure and resistance network distribution, the problem that an existing multi-finger GGNMOS structure is uneven in conduction is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and particularly to an NMOS structure with substrate-triggered uniform turn-on. Background Art

[0002] With the progress of semiconductor process technology, the feature size of CMOS devices has been continuously reduced to improve the chip integration and operating speed. However, the miniaturization of device size leads to a decrease in its electrostatic discharge (ESD) resistance. Therefore, on-chip ESD protection devices need to be integrated in integrated circuits to ensure reliability. Gate-grounded NMOS (GGNMOS) has become one of the widely adopted ESD protection schemes due to its simple structure and compatibility with standard CMOS processes. Traditional GGNMOS usually adopts a multi-finger layout structure to reduce the silicon area occupation, and at the same time utilizes the avalanche breakdown characteristics of parasitic bipolar junction transistors (BJTs) to achieve ESD current discharge.

[0003] In the prior art, there is a problem of non-uniform conduction in the multi-finger structure of GGNMOS in practical applications. Specifically, due to the differences in the base resistances of each finger in the multi-finger GGNMOS surrounded by the P+ protection ring, the finger located in the middle position (the middle finger) has a higher base resistance, and its parasitic NPN transistor will be triggered preferentially under ESD stress. Once the middle finger is triggered, the ESD voltage will be clamped to the holding voltage, resulting in subsequent ESD current being concentrated and discharged through this local area, while other fingers cannot effectively share the current. This non-uniform conduction phenomenon not only reduces the overall ESD protection ability of GGNMOS, but also may cause thermal failure due to excessive local current density, seriously affecting the reliability of the device.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an NMOS structure with substrate-triggered uniform turn-on to at least solve the problem of non-uniform conduction of existing multi-finger GGNMOS.

[0006] Embodiments of the present invention provide the following technical solutions: Embodiments of the present invention provide an NMOS structure with substrate-triggered uniform turn-on, including a P-type substrate, a first P-type well-doped type well region, a plurality of N-type heavily doped active regions, and a polysilicon gate. The first P-type well-doped type well region is implanted into the P-type substrate. The plurality of N-type heavily doped active regions are implanted into the first P-type well-doped type well region at intervals. The plurality of polysilicon gates are disposed on the first P-type well-doped type well region, and their sides are staggered with the plurality of strip-shaped N-type heavily doped active regions. It also includes an edge P-type heavily doped active region, a second P-type well-doped type well region, a P-type high-voltage doped well region, and a P-type deeply doped well region; The edge P-type heavily doped active region, the second P-type well-doped type well region, and the P-type high-voltage doped well region are sequentially implanted into the P-type substrate from top to bottom, and are all arranged in an annular structure. The edge P-type heavily doped active region surrounds the annular N-type heavily doped active region. Among them, the edge P-type heavily doped active region and the annular N-type heavily doped active region are isolated; The P-type deeply doped well region is implanted into the P-type substrate, and its edge extends to the bottom end of the P-type high-voltage doped well region.

[0007] Furthermore, the edge P-type heavily doped active region is electrically connected out and grounded.

[0008] Furthermore, the width of the second P-type well-doped type well region is greater than the width of the edge P-type heavily doped active region; and / or the width of the second P-type well-doped type well region is greater than the width of the P-type high-voltage doped well region.

[0009] Furthermore, the P-type deeply doped well region is a planar structure, and its edges all extend to the bottom end of the P-type high-voltage doped well region.

[0010] Furthermore, it also includes an intermediate P-type heavily doped active region. The intermediate P-type heavily doped active region is implanted at the middle position of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate, and is isolated from the N-type heavily doped active region.

[0011] Furthermore, the intermediate P-type heavily doped active region is isolated from the N-type heavily doped active region through an annular STI region.

[0012] Furthermore, the intermediate P-type heavily doped active region is electrically connected out and grounded.

[0013] Furthermore, the edge P-type heavily doped active region is isolated from the N-type heavily doped active region through an STI region.

[0014] Furthermore, both ends of the polysilicon gate are isolated from the first P-type well-doped type well region through an STI region.

[0015] Furthermore, the two segments of the STI region between the polysilicon gate and the first P-type well-doped type well region extend to the inner side edges of the edge P-type heavily doped active region.

[0016] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present invention at least include: A NMOS structure with substrate-triggered uniform turn-on, in the present invention, by setting an annular edge P-type heavily doped active region, a second P-type well-doped well region, and a P-type high-voltage doped well region at the edge of the P-type substrate, and by setting a P-type deeply doped well region inside the P-type substrate, thus through a specific doping structure and resistance network distribution, the GGNMOS device is uniformly turned on in a multi-finger structure, solving the problem of non-uniform conduction in the existing multi-finger GGNMOS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a top view of a NMOS structure with substrate-triggered uniform turn-on according to an embodiment of the present invention; Figure 2 It is a partial enlarged view of a substrate-triggered uniform turn-on according to an embodiment of the present invention; Figure 3 It is a cross-sectional view along Figure 1 AA' in Figure 4 It is a cross-sectional view along Figure 1 BB' in Figure 5 It is a cross-sectional view along Figure 1 CC' in

[0019] The reference numerals of the present invention are as follows: 10, P-type substrate; 20, first P-type well-doped well region; 30, N-type heavily doped active region; 40, polysilicon gate; 50, edge P-type heavily doped active region; 60, second P-type well-doped well region; 70, P-type high-voltage doped well region; 80, P-type deeply doped well region; 90, intermediate P-type heavily doped active region; 100, STI region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The embodiments of the present application will be described in detail below with reference to the drawings.

[0021] The following describes the embodiments of the present application through specific specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0022] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0023] It should also be noted that the drawings provided in the following embodiments only schematically illustrate the basic concept of the present application. The drawings only show the components related to the present application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0024] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0025] In the existing multi-finger GGNMOS ESD structure, when an ESD high-voltage pulse is applied at T1, its N+ (N-type heavily doped active area) / Pwell (P-type well doped type well area) will first undergo avalanche breakdown, forming an avalanche current. Among them, holes will flow through Pwell through P+ (P-type heavily doped active area) to T2. Due to the parasitic resistance of Pwell, a potential difference will be generated between Pwell and T1. When the potential is higher than 0.7V, Pwell and N+ at T2 will be forward-conducted, and NPN will be turned on. At this time, the drift current will replace the avalanche current, and more holes will flow into T1. The conductive mechanism will greatly reduce the bias voltage to maintain the same current, and the device will have a negative resistance characteristic. When the voltage is reduced and the current is increased, the current in the device is basically provided by the drift current, and the negative resistance characteristic ends. As the voltage and current increase, the entire device will undergo a secondary breakdown, and the critical burnout point of the device will be reached at this time.

[0026] In the multi-finger GGNMOS structure, the base parasitic resistance of the NPN at the edge of the structure is relatively low. From the above principle analysis, it can be seen that when an ESD pulse is generated, it requires a lower voltage to cause avalanche breakdown. When the ESD voltage is gradually increased, avalanche breakdown occurs in the middle position. Since the NPN in the middle position of the structure has a larger parasitic base resistance (R1+R2+R3...; R4+R5+R6...), the NPN is easier to turn on. Then the voltage in the middle position is quickly clamped to the holding voltage, causing the edge position to be unable to turn on. Macroscopically, the multi-finger NMOS structure produces an edge avalanche breakdown first, and then drives the current uneven distribution of the NPN in the middle position to turn on.

[0027] More specifically, after the edge of the structure is broken down by an avalanche, the avalanche current generated by it flows toward the middle position. The base resistance of the parasitic NPN in the middle position is larger, resulting in a larger potential difference at the base NPN in the middle position, causing the potential difference at the base NPN in the middle position to reach 0.7V earlier, and ultimately causing the parasitic NPN in the middle position to be turned on first.

[0028] In view of this, the inventor has conducted in-depth research and improvement exploration on the base resistance, avalanche current, and the doping method of the edge P-type heavily doped active region 50 at the substrate edge, and found that: doping the edge P-type heavily doped active region 50 at the substrate edge, and successively doping the second P-type well-doped well region 60, P-type high-voltage doped well region 70 below the edge P-type heavily doped active region 50, and doping the P-type deeply doped well region 80 in the P-type substrate 10, so that the resistance value of the longitudinal resistance (the region with relatively low doping concentration) of the P-type deeply doped well region 80 is relatively large, and the resistance value of the lateral resistance of the edge P-type heavily doped active region 50 (due to high-concentration doping) is relatively small. By adjusting the doping concentration, the longitudinal resistance of the P-type deeply doped well region 80 is much larger than the lateral resistance of the edge P-type heavily doped active region 50, so that the total resistance values of each part tend to be close, ensuring uniform distribution of the base potential of the parasitic NPN triode, and finally enabling all finger structures to reach the turn-on voltage simultaneously.

[0029] Based on this, an embodiment of this specification proposes a processing solution: as Figures 1 - 2 shown, a NMOS structure with uniform substrate-triggered turn-on of the present invention, by successively injecting an edge P-type heavily doped active region 50, a second P-type well-doped well region 60, and a P-type high-voltage doped well region 70 at the substrate edge of the existing annular multi-finger GGNMOS structure, and injecting a P-type deeply doped well region 80 into the P-type substrate 10, can enable the GGNMOS device to be uniformly turned on in the multi-finger structure; Specifically, as Figure 4 shown, in the resistance network distribution formed by a specific doping structure, Rp1 / Rp2 / Rp3 represent the longitudinal resistance of the P-type deeply doped well region 80 (high-voltage well), which are regions with relatively low doping concentration and relatively large resistance values, and R1 / R2 / R3 represent the lateral resistance of the edge P-type heavily doped active region 50, which have relatively small resistance values due to high-concentration doping; for the finger structure in the middle position, the base region substrate resistance path = Rp3 (longitudinal) + R1 + R2 + R3 (lateral); for the finger structure at the edge position, the base region substrate resistance path = Rp1 (longitudinal) + R1 (lateral). Since the resistance values of the Rp series resistors (longitudinal) are much larger than the resistance values of the R series resistors (lateral), the resistance value of each finger structure is mainly determined by the longitudinal resistance, and the difference in the lateral resistance R is greatly weakened. Finally, the total resistance values of each path are close (Rp3≈Rp1), ensuring uniform distribution of the base potential of the parasitic NPN triode, enabling all finger structures to reach the turn-on voltage simultaneously, avoiding local current aggregation, and also preventing current concentration and hot spot formation caused by premature conduction in a certain region.

[0030] The following will describe the technical solutions provided by the embodiments of this application with reference to the accompanying drawings.

[0031] like Figures 1 - 5 As shown, the present invention provides a substrate-triggered uniformly turned-on NMOS structure, comprising a P-type substrate 10, a first P-type well-doped type well region 20, a plurality of N-type heavily doped active regions 30 and a polysilicon gate 40, wherein the first P-type well-doped type well region 20 is implanted into the P-type substrate 10, a plurality of N-type heavily doped active regions 30 are implanted into the first P-type well-doped type well region 20 at intervals, a plurality of polysilicon gates 40 are arranged on the first P-type well-doped type well region 20, and the sides thereof are staggered with a plurality of strip-shaped N-type heavily doped active regions 30.

[0032] Among them, the P-type substrate 10 is used to provide basic semiconductor materials as a support for the entire NMOS structure; the first P-type well-doped type well region 20 forms the body region of the NMOS, which is used to isolate the N-type active region and affect the triggering characteristics of the parasitic BJT.

[0033] The P-type substrate 10 is provided with an implantation region for implanting the first P-type well doping type well region 20 by ion implantation. The first P-type well doping type well region 20 is provided with an implantation region for implanting a plurality of N-type heavily doped active regions 30 .

[0034] The plurality of N-type heavily doped active regions 30 include strip-type N-type heavily doped active regions and annular N-type heavily doped active regions that are arranged at intervals, wherein the annular N-type heavily doped active region surrounds the plurality of N-type heavily doped active regions.

[0035] The multiple N-type heavily doped active regions 30 serve as the source and drain of the NMOS, and form the emitter and collector of the parasitic NPN in an ESD event.

[0036] Among them, the polysilicon gate 40 is a ring structure, with its two long sides located between two adjacent strip-shaped N-type heavily doped active areas 30, and its two short sides are isolated by the STI region 100 and the first P-type well-doped type well area 20; positions for connecting metal contact holes are provided on the two short sides of the polysilicon gate 40.

[0037] The polysilicon gate 40 is used to control the conduction of the NMOS and is usually grounded during an ESD event to keep it in an off state.

[0038] The two long sides and the two short sides of the polysilicon gate 40 form a ring structure and surround a strip-shaped N-type heavily doped active region 30 .

[0039] The NMOS structure with substrate-triggered uniform turn-on further includes an edge P-type heavily doped active region 50, a second P-type well-doped type well region 60, a P-type high-voltage doped well region 70, and a P-type deeply doped well region 80; the edge P-type heavily doped active region 50, the second P-type well-doped type well region 60, and the P-type high-voltage doped well region 70 are sequentially implanted into the P-type substrate 10 from top to bottom, and are all arranged in an annular structure. The edge P-type heavily doped active region 50 surrounds the annular N-type heavily doped active region 30. Among them, the edge P-type heavily doped active region 50 and the annular N-type heavily doped active region 30 are isolated; the P-type deeply doped well region 80 is implanted into the P-type substrate 10, and its edge extends to the bottom end of the P-type high-voltage doped well region 70.

[0040] Among them, the edge P-type heavily doped active region 50 is electrically connected and grounded to ensure that the edge P-type heavily doped active region 50 can be effectively grounded, so as to provide an effective current discharge path during an ESD event.

[0041] Among them, the edge P-type heavily doped active region 50 is arranged around the N-type heavily doped active region 30 to form a low-resistance path, promote multi-finger uniform conduction, and after grounding, ensure that the edge P-type heavily doped active region 50 can quickly discharge current during an ESD event and avoid local current concentration.

[0042] Among them, the second P-type well-doped type well region 60 is located below the edge P-type heavily doped active region 50, and is used to provide additional P-type doping, optimize the well region resistance distribution, and improve the uniformity of the ESD current.

[0043] Further, by setting the width of the second P-type well-doped type well region 60 to be greater than the width of the edge P-type heavily doped active region 50, the protection of the N-type heavily doped active region 30 can be enhanced to prevent premature breakdown.

[0044] Among them, the P-type high-voltage doped well region 70 can improve the breakdown voltage resistance of the well region, prevent premature breakdown under ESD stress, and at the same time optimize the triggering characteristics of the parasitic NPN.

[0045] Among them, the P-type deeply doped well region 80 extends to the bottom of the P-type high-voltage doped well region 70, which can reduce the substrate resistance, balance the current distribution between fingers, and avoid local overheating.

[0046] Among them, by setting the P-type deeply doped well region 80 as a planar structure, its uniform coverage can be ensured and the stability of the structure can be improved.

[0047] The present application forms an optimized structural layout by introducing an edge P-type heavily doped active region 50, a second P-type well doped type well region 60, a P-type high-voltage doped well region 70, and a P-type deeply doped well region 80. And through the setting of the P-type deeply doped well region 80, it helps to balance the substrate resistance inside and outside the structure, enabling the entire multi-finger GGNMOS structure to turn on simultaneously under ESD stress.

[0048] Furthermore, the width of the second P-type well doped type well region 60 is greater than the width of the P-type high-voltage doped well region 70 to improve the robustness of the structure and the ESD protection performance.

[0049] In some of the embodiments, the NMOS structure that triggers uniform turn-on of the substrate further includes an intermediate P-type heavily doped active region 90. The intermediate P-type heavily doped active region 90 is implanted at the middle position of the strip-shaped N-type heavily doped active region 30 surrounded by the polysilicon gate 40 and is isolated from the N-type heavily doped active region 30 to further optimize the current distribution and improve the conduction uniformity.

[0050] Preferably, the intermediate P-type heavily doped active region 90 is isolated from the N-type heavily doped active region 30 by an annular STI region 100.

[0051] Furthermore, the intermediate P-type heavily doped active region 90 is electrically connected out and grounded.

[0052] The present invention dopes the edge P-type heavily doped active region 50 in the middle of the strip-shaped N-type heavily doped active region 30 surrounded by the polysilicon gate 40, which helps to disperse the current during an ESD event, prevent local overheating and damage, and enhance its current discharge ability.

[0053] Furthermore, the edge P-type heavily doped active region 50 is isolated from the N-type heavily doped active region 30 by the STI region 100 to prevent the direct contact between the P+ and N+ regions, avoid leakage, and at the same time optimize the triggering path of the parasitic BJT.

[0054] Furthermore, both ends of the polysilicon gate 40 are isolated from the first P-type well doped type well region 20 by the STI region 100 to prevent the gate from short-circuiting with the well region and ensure that the ESD current is mainly discharged through the parasitic BJT.

[0055] Furthermore, the two segments of the STI region 100 between the polysilicon gate 40 and the first P-type well doped type well region 20 extend to the inner sides of the edge P-type heavily doped active region 50 to enhance the isolation effect and optimize the current distribution.

[0056] Among them, the STI region 100 is used to provide effective electrical isolation to prevent interference between different doped regions. Moreover, the isolation between the polysilicon gate 40 and the first P-type well doped type well region 20 enhances the structural integrity and ESD protection performance. The STI region 100 extending to the inner side of the edge P-type heavily doped active region 50 further enhances the structural stability and uniformity.

[0057] By adopting an annular polysilicon gate structure, the present invention makes the area utilization efficiency of the NMOS higher, thereby improving the overall current discharge capacity. In addition, a P-type deep doped well region 80 is implanted in the substrate at the bottom of its structure, and the P-type high-voltage doped well region 70, the second P-type well doped type well region 60, and the edge P-type heavily doped active region 50 are sequentially arranged around the edge of the structure substrate and connected to the ground (GND), so that the substrate resistance of the base region of a certain parasitic NPN structure in the middle of the multi-finger GGNMOS is Rp3 + R1 + R2 + R3, and the substrate resistance of the base region of a certain parasitic NPN structure at its edge is Rp1 + R1.

[0058] Since Rp1, Rp2, Rp3... are much larger than R1, R2, R3..., the effective substrate resistance at the position around the GGNMOS structure and in the middle of the GGNMOS structure can be maintained at the same level through this specific doping structure, so that the entire multi-finger GGNMOS circuit is turned on simultaneously, avoiding premature damage due to excessive current caused by the premature turn-on of a certain area with too large resistance.

[0059] Furthermore, the edge P-type heavily doped active region 50 is inserted at the drain end of the same annular GGNMOS and connected to the T2 ground terminal. When an ESD pulse occurs, the parasitic resistance of the reverse PN junction path of the N-type heavily doped active region 30 / the second P-type well doped type well region 60 / the middle P-type heavily doped active region 90 is smaller than that at other positions, and avalanche breakdown will occur first, which can improve the response speed of the GGNMOS and avoid the problem of difficult turn-on caused by the overall increase in the resistance from the substrate to the edge P-type heavily doped active region 50 due to the change of the overall structure.

[0060] In this specification, the same or similar parts between various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the partial descriptions of the system embodiments.

[0061] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An NMOS structure with substrate-triggered uniform turn-on, comprising a P-type substrate, a first P-type well-doped well region, a plurality of N-type heavily doped active regions, and polysilicon gates. The first P-type well-doped well region is implanted into the P-type substrate. The plurality of N-type heavily doped active regions are implanted into the first P-type well-doped well region at intervals. A plurality of the polysilicon gates are disposed on the first P-type well-doped well region, and their sides are staggered with the plurality of strip-shaped N-type heavily doped active regions. It is characterized in that, It also includes an edge P-type heavily doped active region, a second P-type well-doped type well region, a P-type high-voltage doped well region, and a P-type deeply doped well region; The edge P-type heavily doped active region, the second P-type well-doped type well region, and the P-type high-voltage doped well region are sequentially implanted into the P-type substrate from top to bottom, and are all arranged in a ring structure. The edge P-type heavily doped active region surrounds the annular N-type heavily doped active region. Among them, the edge P-type heavily doped active region and the annular N-type heavily doped active region are isolated; The P-type deeply doped well region is implanted into the P-type substrate, and its edge extends to the bottom end of the P-type high-voltage doped well region.

2. The NMOS structure with substrate-triggered uniform turn-on according to claim 1, wherein The edge P-type heavily doped active region is electrically connected out and grounded.

3. The NMOS structure with substrate-triggered uniform turn-on according to claim 2, characterized in that, The width of the second P-type well-doped type well region is greater than the width of the edge P-type heavily doped active region; and / or the width of the second P-type well-doped type well region is greater than the width of the P-type high-voltage doped well region.

4. The NMOS structure with substrate-triggered uniform turn-on according to claim 2, wherein The P-type deeply doped well region is a planar structure, and its edges all extend to the bottom end of the P-type high-voltage doped well region.

5. The NMOS structure with substrate-triggered uniform turn-on according to claim 1, characterized in that It also includes an intermediate P-type heavily doped active region, which is implanted at the middle position of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate and is isolated from the N-type heavily doped active region.

6. The NMOS structure with substrate-triggered uniform turn-on according to claim 5, characterized in that, The intermediate P-type heavily doped active region is isolated from the N-type heavily doped active region by an annular STI region.

7. The NMOS structure with substrate-triggered uniform turn-on according to claim 5, characterized in that The intermediate P-type heavily doped active region is electrically connected out and grounded.

8. The NMOS structure with substrate-triggered uniform turn-on according to claim 1, characterized in that, The edge P-type heavily doped active region is isolated from the N-type heavily doped active region by an STI region.

9. The NMOS structure with substrate-triggered uniform turn-on according to claim 1, characterized in that Both ends of the polysilicon gate are isolated from the first P-type well-doped type well region by an STI region.

10. The NMOS structure with substrate-triggered uniform turn-on according to claim 9, characterized in that, Two sections of the STI region between the polysilicon gate and the first P-type well-doped type well region extend to the inner side edges of the edge P-type heavily doped active region.

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