Ultra-low leakage current VDMOS switch element and manufacturing method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses an ultra-low leakage current VDMOS switch element and a manufacturing method thereof, the ultra-low leakage current VDMOS switch element comprises a metal drain electrode, a metal source electrode, a semiconductor epitaxial layer and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, and a connecting layer is arranged between the metal source electrode and the N well layer. According to the invention, TiSi, CoSi or highly-doped polycrystalline silicon is adopted as the material of the connecting layer between the metal source electrode and the N well layer, so that the interface contact resistance is obviously reduced, and the materials have excellent conductivity and low interface potential barrier characteristics, so that efficient ohmic contact can be realized, scattering and energy loss of carriers at the interface are reduced, and the performance of the device is improved. According to the design, Joule heat accumulation caused by poor contact is directly inhibited, so that leakage current is effectively reduced, and meanwhile, the conduction efficiency and the thermal stability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to an ultra-low leakage current VDMOS switching element and a manufacturing method thereof. Background Art

[0002] The vertical double-diffused metal oxide semiconductor (VDMOS) switching element, as a core component of power semiconductor devices, is widely used in fields such as power management, motor drive, and high-frequency switching. Traditional VDMOS devices are usually composed of a metal drain, a source, a gate, and a multi-layer semiconductor epitaxial structure, and their performance is limited by factors such as interface contact resistance, leakage current, and parasitic effects. The conventional uniformly doped structure is prone to form a conduction path of a parasitic bipolar transistor, further exacerbating the leakage current and latch-up risk. These problems not only limit the device conduction efficiency and thermal stability but also restrict its application in high-frequency and high-integration scenarios. Therefore, it is urgent to achieve an efficient and reliable design of an ultra-low leakage current VDMOS switching element through material optimization, structural innovation, and process improvement.

[0003] A prior patent discloses a vertical double-diffused metal oxide semiconductor field effect transistor (publication number CN104112773A), which includes a side insulation layer located on the side of the drift region, extending longitudinally, and having different lateral widths in the extending direction. In this prior art, ordinary metal or polysilicon is often used as the contact material between the metal source and the N-well layer, resulting in a high interface barrier, large contact resistance, causing Joule heat accumulation and increased leakage current; the edge of the gate is prone to leakage due to electric field concentration, reducing the breakdown voltage of the device. Summary of the Invention

[0004] The present invention provides an ultra-low leakage current VDMOS switching element and a manufacturing method thereof to solve the existing technical problems and solve the problems in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an ultra-low leakage current VDMOS switching element includes a metal drain, a metal source, a semiconductor epitaxial layer, and a gate. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, a P+ layer, a P-well layer, and an N-well layer. A connection layer is provided between the metal source and the N-well layer; wherein the connection layer is in ohmic contact with the metal source and contacts the N-well layer.

[0006] Furthermore, the material of the connection layer is one of TiSi2, CoSi2, or highly doped polysilicon.

[0007] Furthermore, high-K dielectric layers are deposited on both the left and right sides of the gate, and the bottom cross-sectional height of the high-K dielectric layer is the same as the bottom cross-sectional height of the connection layer.

[0008] Further, the connection layer further includes a doping increasing layer, and the doping concentration inside the doping increasing layer increases step by step from the outside to the inside.

[0009] Further, polysilicon layers are deposited on both the left and right sides of the gate.

[0010] Further, an N-doped layer is formed by ion implantation at the center inside the P-well layer.

[0011] Further, the connection layer includes an N+ layer and a P- layer, and the P- layer is located between the N+ layer and the gate.

[0012] A manufacturing method of an ultra-low leakage current VDMOS switching element includes: S1. An N-drift layer is formed on the surface of an N-substrate layer by epitaxial growth; S2. P-type impurity ions are implanted on the surface of the N-drift layer to form a P+ layer, and a P-well layer is formed on the P+ layer by photolithography and ion implantation, and N-type impurities are implanted in the central region of the P-well layer to form an N-doped layer; S3. N-type impurity ions are implanted in the peripheral region of the P-well layer to form an N-well layer; S4. A high-K dielectric layer is deposited on the semiconductor surface, and symmetric high-K dielectric layers are formed on both sides of the gate region by photolithography and etching, and the height of its bottom end is controlled to be aligned with the subsequent connection layer; S5. A connection layer is formed between the metal source electrode and the N-well layer by chemical vapor deposition; S6. The connection layer is gradient-doped to form a doping increasing layer, and the doping concentration increases step by step from the outside to the inside through multiple ion implantations; S7. An N+ layer and a P- layer are formed step by step in the connection layer to ensure that the P- layer is located between the N+ layer and the gate; S8. A metal source electrode is prepared on the surface of the connection layer, ohmic contact is achieved through an annealing process, and a metal drain electrode is prepared on the back of the substrate.

[0013] An ultra-low leakage current VDMOS switching element and its manufacturing method provided by the present invention, compared with the prior art, the effects obtained by this method are: 1. By using TiSi2, CoSi2 or highly doped polysilicon as the connection layer material between the metal source electrode and the N-well layer, the present invention significantly reduces the interface contact resistance. These materials have excellent conductivity and low interface barrier characteristics, can achieve efficient ohmic contact, reduce the scattering and energy loss of carriers at the interface. This design directly suppresses the Joule heat accumulation caused by poor contact, thereby effectively reducing the leakage current, and at the same time improving the on-state efficiency and thermal stability of the device.

[0014] 2. The present invention optimizes the electric field distribution in the gate region by symmetrically depositing high-K dielectric layers on both sides of the gate and precisely controlling the height of its bottom end to align with the connection layer. The high dielectric constant of the high-K dielectric significantly enhances the gate capacitance, reduces the peak value of the electric field intensity at the gate edge, and reduces the electric field concentration effect. This improvement not only reduces the gate leakage current, but also improves the breakdown voltage and reliability of the device, while supporting smaller device sizes to achieve high integration.

[0015] 3. The present invention introduces a doping increasing layer in the connection layer, and forms a doping concentration gradient that gradually increases from the outside to the inside through multiple ion implantations. This gradient design smooths the migration path of carriers from the metal source to the N-well layer, reduces the carrier accumulation and recombination probability at the interface. In addition, the concentration gradient also balances the conductivity distribution, avoids the generation of local high-resistance regions, further suppresses the leakage current, and improves the current conduction uniformity.

[0016] 4. The present invention extends the effective control range of the gate by depositing polysilicon layers on both sides of the gate. The polysilicon layer not only enhances the gate's ability to regulate the channel electric field, but also improves the uniformity of the electric field distribution, reducing the leakage risk at the gate edge. This design reduces the leakage current while enhancing the switching speed and dynamic response characteristics of the device, especially suitable for high-frequency application scenarios.

[0017] 5. The present invention constructs a local reverse doping structure by implanting N-type impurities in the central region of the P-well layer to form an N-doped layer. This structure effectively suppresses the conduction effect of the parasitic bipolar transistor and blocks the leakage current caused by the parasitic path. At the same time, the reverse doping optimizes the carrier distribution in the P-well region, improves the breakdown voltage and anti-latch-up ability of the device, and enhances the overall reliability.

[0018] 6. The present invention forms an N+ layer and a P- layer step by step in the connection layer, and places the P- layer between the N+ layer and the gate. The depletion region formed by the P- layer effectively blocks the lateral diffusion of the leakage current, while the N+ layer provides a low-resistance conduction path. This composite structure suppresses the leakage current while ensuring efficient carrier transport between the source and the drift region, achieving the coordinated optimization of low leakage and high conduction performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic structural diagram of the first embodiment in the present invention; Figure 2 It is a schematic structural diagram of the second embodiment in the present invention; Figure 3 It is a schematic structural diagram of the third embodiment in the present invention; Figure 4 It is a schematic structural diagram of the fourth embodiment in the present invention; Figure 5Schematic diagram of Embodiment 5 in the present invention; Figure 6 Schematic diagram of Embodiment 6 in the present invention.

[0020] In the figure: 1, metal drain; 2, metal source; 3, gate; 4, N substrate layer; 5, N drift layer; 6, P+ layer; 7, P well layer; 8, N well layer; 9, connection layer; 10, high-K dielectric layer; 11, polysilicon layer; 12, N-doped layer; 91, doping increasing layer; 92, N+ layer; 93, P- layer. Specific embodiments

[0021] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As Figure 1-6 shown, according to one aspect of the present invention, a manufacturing method of an ultra-low leakage current VDMOS switching element includes: Step 1: An N drift layer 5 is formed on the surface of the N substrate layer 4 by epitaxial growth; the N drift layer 5 is epitaxially grown on the N substrate layer 4, and a drift region with low defects and high uniformity is formed by precisely controlling the epitaxial process, providing an ideal carrier migration channel for the subsequent structure and reducing the leakage current caused by lattice defects.

[0023] Step 2: P-type impurity ions are implanted on the surface of the N drift layer 5 to form a P+ layer 6, and a P well layer 7 is formed on the P+ layer 6 by photolithography and ion implantation, and N-type impurities are implanted in the central region of the P well layer 7 to form an N-doped layer 12; P-type impurities are implanted on the surface of the N drift layer 5 to form a P+ layer 6 and a P well layer 7, and N-type impurities are implanted in the center of the P well layer to form an N-doped layer 12. This operation weakens the conduction effect of the parasitic bipolar transistor through local reverse doping (embedding an N-type region in the P well), and suppresses the leakage current caused by the parasitic path.

[0024] Step 3: N-type impurity ions are implanted in the peripheral region of the P well layer 7 to form an N well layer 8; N-type impurities are implanted in the periphery of the P well layer 7 to form an N well layer 8, optimizing the connection between the source and the drift region, reducing the contact resistance, and at the same time balancing the lateral electric field distribution of the device.

[0025] Step 4: A high-K dielectric layer 10 is deposited on the semiconductor surface, and symmetric high-K dielectric layers 10 are formed on both sides of the gate region 3 by photolithography and etching, controlling the height of its bottom end to be aligned with the subsequent connection layer 9; high-K dielectric layers 10 are deposited on both sides of the gate 3, and by precisely aligning the height of its bottom end with the connection layer 9, the gate capacitance is enhanced, the electric field concentration at the gate edge is reduced, thereby reducing the gate leakage current. The introduction of the high-K dielectric also improves the device integration and reliability.

[0026] Step Five: A connection layer 9 is formed between the metal source electrode 2 and the N-well layer 8 by chemical vapor deposition; the connection layer 9 is formed between the metal source electrode 2 and the N-well layer 8 by chemical vapor deposition, and a low-resistance material such as TiSi2 is used to form an ohmic contact, significantly reducing the interface resistance and avoiding Joule heat and leakage current caused by poor contact.

[0027] Step Six: The connection layer 9 is subjected to gradient doping to form a doping-increasing layer 91, and the doping concentration is gradually increased from the outside to the inside through multiple ion implantations; the connection layer 9 is subjected to gradient doping to form a doping-increasing layer 91, and the concentration is increased from the outside to the inside through multiple ion implantations, smoothing the carrier migration path, reducing the carrier accumulation and recombination at the interface, and further suppressing the leakage current.

[0028] Step Seven: An N+ layer 92 and a P- layer 93 are formed step by step in the connection layer 9, ensuring that the P- layer 93 is located between the N+ layer 92 and the gate 3; an N+ layer 92 and a P- layer 93 are formed step by step in the connection layer 9, making the P- layer 93 located between the N+ layer and the gate 3. The depletion region formed by the P- layer effectively blocks the lateral diffusion of the leakage current, while the N+ layer provides a low-resistance conduction path, taking into account both low leakage and high conduction performance.

[0029] Step Eight: A metal source electrode 2 is prepared on the surface of the connection layer 9, and an ohmic contact is achieved through an annealing process, and a metal drain electrode 1 is prepared on the back of the substrate. An ohmic contact between the metal source electrode 2 and the connection layer 9 is achieved through an annealing process, and a metal drain electrode 1 is prepared on the back of the substrate, ensuring the low-resistance connection and thermal stability of the overall structure, and finally realizing the high-efficiency switching characteristics of the device.

[0030] Example 1 As Figure 1 shown, an ultra-low leakage current VDMOS switching element includes a metal drain electrode 1, a metal source electrode 2, a semiconductor epitaxial layer, and a gate 3. The semiconductor epitaxial layer includes an N-substrate layer 4, an N-drift layer 5, a P+ layer 6, a P-well layer 7, and an N-well layer 8, and is characterized in that: a connection layer 9 is provided between the metal source electrode 2 and the N-well layer 8; wherein the connection layer 9 is in ohmic contact with the metal source electrode 2, and the connection layer 9 is in contact with the N-well layer 8. The material of the connection layer 9 is one of TiSi2, CoSi2, or highly doped polysilicon. Using TiSi2, CoSi2, or highly doped polysilicon as the material of the connection layer 9, its excellent conductivity and low interface barrier characteristics achieve an efficient ohmic contact between the metal source electrode 2 and the N-well layer 8, significantly reducing the contact resistance, thereby suppressing the generation of leakage current.

[0031] Example 2 As Figure 2As shown, high-K dielectric layers 10 are deposited on both the left and right sides of the gate 3, where the bottom cross-sectional height of the high-K dielectric layer 10 is the same as that of the connection layer 9. By symmetrically depositing the high-K dielectric layers 10 on both sides of the gate 3 and controlling its bottom height to align with the connection layer 9, the electric field distribution in the gate region is optimized. The high dielectric constant of the high-K dielectric enhances the gate capacitance, reduces the electric field concentration effect at the gate edge, and effectively reduces the gate leakage current.

[0032] Embodiment 3 As Figure 3 shown, the connection layer 9 further includes a doping-increasing layer 91, and the doping concentration inside the doping-increasing layer 91 increases step by step from the outside to the inside. By introducing the doping-increasing layer 91 into the connection layer 9, a doping concentration gradient that increases step by step from the outside to the inside is formed through multiple ion implantations. This gradient design smoothes the carrier migration path, reduces the carrier accumulation and recombination at the interface, and further suppresses the leakage current.

[0033] Embodiment 4 As Figure 4 shown, polysilicon layers 11 are deposited on both the left and right sides of the gate 3. By depositing the polysilicon layers 11 on both sides of the gate 3, the effective control area of the gate is expanded, the uniformity of the electric field distribution is improved, and the leakage risk at the gate edge is reduced.

[0034] Embodiment 5 As Figure 5 shown, an N-doped layer 12 is formed by ion implantation at the inner center of the P-well layer 7. By implanting N-type impurities at the center of the P-well layer 7 to form the N-doped layer 12, a local reverse doping structure is constructed. This structure weakens the conduction effect of the parasitic bipolar transistor and avoids the leakage current path caused by the parasitic effect.

[0035] Embodiment 6 As Figure 6 shown, the connection layer 9 includes an N+ layer 92 and a P- layer 93, where the P- layer 93 is located between the N+ layer 92 and the gate 3. The N+ layer 92 and the P- layer 93 are formed step by step in the connection layer 9, and the P- layer 93 is placed between the N+ layer 92 and the gate 3. This design blocks the lateral diffusion path of the leakage current through the depletion region formed by the P- layer, while the N+ layer provides a low-resistance connection, comprehensively optimizing the leakage and conduction performance.

[0036] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. An ultra-low leakage current VDMOS switching element, comprising a metal drain (1), a metal source (2), a semiconductor epitaxial layer, and a gate (3), wherein the semiconductor epitaxial layer includes an N substrate layer (4), an N drift layer (5), a P+ layer (6), a P well layer (7), and an N well layer (8), and is characterized in that: A connection layer (9) is provided between the metal source electrode (2) and the N-well layer (8); wherein the connection layer (9) is in ohmic contact with the metal source electrode (2), and the connection layer (9) is in contact with the N-well layer (8).

2. The ultra-low leakage current VDMOS switching element according to claim 1, characterized in that: The material of the connection layer (9) is one of TiSi2, CoSi2 or highly doped polysilicon.

3. The ultra-low leakage current VDMOS switching element according to claim 1, wherein: High-k dielectric layers (10) are deposited on both the left and right sides of the gate electrode (3), and the bottom cross-sectional height of the high-k dielectric layer (10) is the same as the bottom cross-sectional height of the connection layer (9).

4. The ultra-low leakage current VDMOS switching element according to claim 1, characterized in that: The connection layer (9) further includes a doping increasing layer (91), and the doping concentration inside the doping increasing layer (91) increases step by step from the outside to the inside.

5. The ultra-low leakage current VDMOS switching element according to claim 1, characterized in that: Polysilicon layers (11) are deposited on both the left and right sides of the gate electrode (3).

6. The ultra-low leakage current VDMOS switching element according to claim 1, wherein: An N-doped layer (12) is formed by ion implantation at the center inside the P-well layer (7).

7. The ultra-low leakage current VDMOS switching element according to claim 1, characterized in that: The connection layer (9) includes an N+ layer (92) and a P- layer (93), wherein the P- layer (93) is located between the N+ layer (92) and the gate electrode (3).

8. A manufacturing method of an ultra-low leakage current VDMOS switching element, characterized in that, Applied to the VDMOS switching element according to any one of claims 1-7, the manufacturing method includes:[[]]END]] S1. An N-drift layer (5) is formed on the surface of the N-substrate layer (4) by epitaxial growth. S2. P-type impurity ions are implanted on the surface of the N-drift layer (5) to form a P+ layer (6), and a P-well layer (7) is formed on the P+ layer (6) by photolithography and ion implantation, and N-type impurities are implanted in the central region of the P-well layer (7) to form an N-doped layer (12). S3. N-type impurity ions are implanted in the peripheral region of the P-well layer (7) to form an N-well layer (8). S4. A high-k dielectric layer (10) is deposited on the semiconductor surface, and symmetric high-k dielectric layers (10) are formed on both sides of the gate region (3) by photolithography and etching, and its bottom height is controlled to be aligned with the subsequent connection layer (9). S5. A connection layer (9) is formed between the metal source electrode (2) and the N-well layer (8) by chemical vapor deposition. S6. The connection layer (9) is subjected to gradient doping to form a doping increasing layer (91), and the doping concentration is increased step by step from the outside to the inside by multiple ion implantations. S7. An N+ layer (92) and a P- layer (93) are formed step by step in the connection layer (9) to ensure that the P- layer (93) is located between the N+ layer (92) and the gate electrode (3). S8. A metal source electrode (2) is prepared on the surface of the connection layer (9), and ohmic contact is achieved through an annealing process, and a metal drain electrode (1) is prepared on the back of the substrate.

Images