Method for generating random number sequence based on ferroelectric latch

Abstract

The invention discloses a method for generating a random number sequence based on a ferroelectric latch, and belongs to the technical field of novel circuit design and calculation. The process mismatch of the CMOS circuit is compensated by using the ferroelectric capacitor, the generation process of the random number sequence is the power-on process of the ferroelectric latch, the random number sequence is generated based on the ferroelectric latch, and working in a TRNG mode and an adjustable RNG mode can be realized. Compared with a traditional RNG which needs a complex entropy source calibration or extraction circuit, the method has the advantages that the hardware overhead is greatly reduced, the random number generation speed is high, the power consumption is very low, and the programming erasing process of a device does not exist in the random number generation process, so that the reliability problems of insufficient durability and the like of a novel device are solved, and the reliability of the device is improved. And the reliability is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of novel circuit design and computing, and particularly relates to a method for generating a random number sequence based on a ferroelectric latch. Background Art

[0002] A random number generator (RNG) is used to generate a random number sequence with uncertainty and unpredictability, and has important applications in many fields such as data encryption, statistical analysis, privacy computing, and combinatorial optimization solving. According to the source of the generated random numbers, random number generators can be divided into two categories: pseudo-random number generators (PRNGs) and true random number generators (TRNGs). PRNGs are generated based on deterministic algorithms, and their sequences are theoretically predictable, while TRNGs are random numbers generated based on physical entropy sources such as electronic noise and photon scattering, and their sequences have a high degree of unpredictability and are commonly used in application scenarios with high security requirements. On the other hand, through algorithms or circuit design, it is possible to control the RNG to generate a random number sequence with adjustable 0 / 1 probabilities, called an adjustable RNG, which can adjust the probability distribution characteristics of the output random numbers according to requirements. Due to the characteristic of adjustable probability, adjustable RNGs have greater advantages in application scenarios that require control of random characteristics, such as simulated annealing, Ising machine solving, Monte Carlo simulation, machine learning, and artificial intelligence, and promote the development of new computing architectures.

[0003] Currently, the main implementation methods of TRNGs are as follows: TRNGs based on noise and amplifiers, TRNGs based on ring oscillators, and TRNGs based on CMOS latches. TRNGs based on noise and amplifiers utilize thermal noise or flicker noise and high-gain high-speed operational amplifiers to ensure the speed of generating random number sequences, resulting in large hardware overhead and power consumption. TRNGs based on ring oscillators utilize the jitter of high-frequency clocks and use low-frequency clocks to generate random number sequences, but multiple oscillators are required and the frequency is limited by the low-frequency clock. TRNGs based on CMOS latches require complex calibration circuits to compensate for the mismatch caused by the process, enabling the CMOS latches to work at the metastable point to generate random number sequences. However, the hardware overhead of the compensation circuit is usually much larger than the latch itself, resulting in large area overhead and power consumption. The above TRNG hardware implementations mainly consist of an entropy source generation circuit and an entropy source extraction or calibration circuit. The complex extraction or calibration circuit limits the speed, area, and energy efficiency of the TRNG. Recently, some work has proposed a TRNG based on a new resistive switching device, which generates random number sequences using the periodic fluctuations of the device programming voltage, and can reduce the overhead of the entropy source extraction circuit. However, it generates random numbers through the programming process of the resistive switching device, facing problems such as limited speed and durability. In addition, generating 0 / 1 random numbers by setting thresholds is affected by device-to-device fluctuations, and it will have a greater impact when further implementing the function of an adjustable RNG. Therefore, currently, TRNGs and adjustable RNGs face trade-offs among performance such as hardware overhead, power consumption, and speed, and further optimized designs are needed. Summary of the Invention

[0004] Aiming at the problems existing in the above prior art, the present invention proposes a method for generating a random number sequence based on a ferroelectric latch, which utilizes ferroelectric polarization to compensate for the process mismatch of the CMOS latch, has the advantages of low hardware overhead, low power consumption, high speed, and high reliability, and has the function of adjustable probability.

[0005] The technical solution of the present invention is as follows:

[0006] A method for generating a random number sequence based on a ferroelectric latch, the steps of which include:

[0007] 1) Use an n-type FeFET and a p-type FeFET to form two inverters respectively. A switch is connected in series at the input end of each inverter and is connected to the output end of the other inverter;

[0008] 2) Disconnect the above two switches to form two independent inverters, program the ferroelectric polarization states in the two inverters, so that the switching voltages of the two inverters are modulated to VDD / 2;

[0009] 3) Close the above two switches. The two inverters form a latch structure. After multiple power - ons, the ferroelectric latch generates a random number sequence.

[0010] Further, adjust the ferroelectric polarization state so that there is a difference ΔV between the switching voltages of the two inverters S , and the magnitude of the ΔV S is less than the magnitude of the thermal noise; when ΔV S <0, the probability P0 of generating 0 in the random number sequence is greater than the probability P1 of 1; when ΔV S >0, the probability P1 of generating 1 in the random number sequence is greater than the probability P0 of 0.

[0011] The method for generating a random number sequence based on a ferroelectric latch proposed by the present invention, wherein the ferroelectric materials of the n - type FeFET and p - type FeFET are various HfO2 - doped multi - domain ferroelectric materials such as HfO2 doped with Zr (HZO), HfO2 doped with Al (HfAlO), etc. The switch can be a MOSFET, a transmission gate, or other types of mechanical switches. The gate stack of the FeFET device can be based on various structures such as MFMIS, MFIS, MFS, etc.

[0012] The technical effects of the present invention are as follows:

[0013] 1. The method for generating a random number sequence based on a ferroelectric latch proposed by the present invention uses ferroelectric polarization to compensate for the process mismatch of the CMOS latch, and can realize the functions of TRNG and adjustable RNG. Compared with traditional RNGs that require complex entropy source calibration or extraction circuits, the hardware cost is greatly reduced.

[0014] 2. The method for generating a random number sequence based on a ferroelectric latch proposed by the present invention generates a random number sequence through the power - on process of the ferroelectric latch, and does not require additional amplification or extraction circuits. Therefore, it has a very fast random number generation speed and very low power consumption, and the power consumption can be further reduced by further reducing VDD.

[0015] 3. The method for generating a random number sequence based on a ferroelectric latch proposed by the present invention, compared with other adjustable RNGs based on new devices, does not have the device programming and erasing process during the random number generation process, thus avoiding reliability problems such as insufficient durability of new devices and has high reliability. Description of the Drawings

[0016] Figure 1 is a schematic structural diagram of the ferroelectric latch of the present invention;

[0017] Figure 2 is a schematic principle diagram of generating a random number sequence based on a ferroelectric latch and a CMOS latch of the present invention;

[0018] In the figure: 1 - Schematic diagram of the principle that a CMOS latch generates deterministic 0 / 1 during the power - on process due to process mismatch; 2 - Schematic diagram of the principle that the ferroelectric latch of the present invention completely compensates for process mismatch and generates random 0 / 1 during the power - on process;

[0019] Figure 3 It is a schematic diagram of the principle for adjusting and generating the probability of the random number sequence 0 / 1 in the present invention. Detailed implementation manners

[0020] The following further clearly and completely elaborates the present invention through specific embodiments in conjunction with the accompanying drawings.

[0021] The structure of the ferroelectric latch of the present invention, as Figure 1 shown, consists of two inverters respectively composed of an n - type FeFET and a p - type FeFET, and two switches. The input terminal of one inverter is connected in series with a switch to the output terminal of the other inverter. When the switch is closed, a latch structure is formed, which is called a ferroelectric latch. The output terminals of the two cross - coupled inverters are the output data Q and QB of the latch. There are process mismatches in CMOS circuits, such as the gate width (W) of transistors, the effective gate length (L eff ), and the threshold voltage (V TH ), etc. There is a certain difference in the switching voltages of the two CMOS inverters. The ferroelectric latch proposed by the present invention can utilize ferroelectric polarization to compensate for process mismatch.

[0022] As Figure 2 shown, due to process mismatch, the butterfly curve of the CMOS latch will deviate towards the 1 region or the 0 region, which is called 1 - skewed or 0 - skewed, and the amplitude of the offset ΔV S is usually greater than the amplitude of the noise. During the power - on process, the CMOS latch in the 1 - skewed or 0 - skewed state will generate a definite 1 or 0. The present invention proposes a principle for generating a random number sequence based on a ferroelectric latch. By using ferroelectric polarization to compensate for process mismatch, the two switches are disconnected, the connection of the two inverters is disconnected, and the ferroelectric polarization state is adjusted, so that the threshold voltages of the n - type FeFET and p - type FeFET in the inverter are modulated simultaneously, and then the switching voltage of the inverter is modulated. By precisely programming the ferroelectric polarization states in the two inverters respectively, the switching voltages of the two inverters can be precisely modulated to VDD / 2, completing the compensation for process mismatch. Then the two switches are closed to form a ferroelectric latch. Its butterfly curve will not shift and is in the metastable state point. Under the influence of thermal noise during the power - on process, the ferroelectric latch will generate a random 0 or 1. Each power - on can generate a random number, and multiple power - ons can generate a random number sequence, and the probabilities of 0 and 1 in the random number sequence are close to 50%, that is, the function of the TRNG is realized.

[0023] The present invention is based on the fact that a ferroelectric latch can adjust the probability of generating a random number sequence 0 / 1, and its principle is as follows Figure 3 shown. By adjusting the ferroelectric polarization state, a slight difference (ΔV S ) is created between the switching voltages of two inverters. The amplitude of ΔV S is less than the amplitude of thermal noise, which can make the ferroelectric latch be in the pseudo metastable state point 0 or the stable metastable state point 1. When powered on, under the influence of thermal noise, the ferroelectric latch will generate 0 or 1 with a greater probability. By precisely controlling the magnitude of ΔV S , P0 (P1) can be changed from 0% (100%) to 100% (0%), and random number sequences with different probabilities can be generated according to actual requirements.

[0024] This embodiment fully and detailedly elaborates on generating a random number sequence based on a ferroelectric latch. By using a ferroelectric capacitor to compensate for the process mismatch of a CMOS circuit, it can operate in the TRNG mode and the adjustable RNG mode, greatly reducing the hardware overhead compared to traditional RNGs that require complex entropy source calibration or extraction circuits. The generation process of the random number sequence is the power-on process of the ferroelectric latch, with a very fast random number generation speed and very low power consumption. During the random number generation process, there is no programming and erasing process of the device, thus avoiding reliability problems such as insufficient durability of new devices and having high reliability.

[0025] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection required by the present invention is defined by the scope of the claims.

Claims

1. A method for generating a random number sequence based on a ferroelectric latch, the steps comprising: 1) Two inverters are formed using n-type FeFET and p-type FeFET respectively, and a switch is connected in series to the input of each inverter and connected to the output of the other inverter; 2) disconnecting the above two switches to form two independent inverters, and programming the ferroelectric polarization states in the two inverters so that the flip voltages of the two inverters are modulated at VDD / 2; 3) The two switches are closed, and the two inverters form a latch structure. After multiple power-ups, the ferroelectric latch generates a random number sequence.

2. The method for generating a random number sequence based on a ferroelectric latch according to claim 1, characterized in that: The ferroelectric polarization state is adjusted so that there is a difference ΔV between the switching voltages of the two inverters. S , the ΔV S The amplitude is smaller than the thermal noise.

3. The method for generating a random number sequence based on a ferroelectric latch as claimed in claim 2, characterized in that: When ΔV S <0, the probability P0 of generating 0 in the random number sequence is greater than the probability P1 of 1; when ΔV S >0, the probability P1 of generating 1 in the random number sequence is greater than the probability P0 of 0.

4. The method for generating a random number sequence based on a ferroelectric latch according to claim 1, characterized in that: The ferroelectric material of the FeFET is HfO2 doped with Zr or HfO2 doped with Al.

5. The method for generating a random number sequence based on a ferroelectric latch according to claim 1, characterized in that: The FeFET device is based on MFMIS, MFIS or MFS structure.

6. The method for generating a random number sequence based on a ferroelectric latch according to claim 1, characterized in that: The switch is a MOSFET, a transmission gate or a mechanical switch.

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