Broadcasting circuit of fuse array and broadcasting method of fuse array
By designing a fuse array broadcast circuit of multiple sub-broadcast circuits and latch circuits in the memory device, the problem of mismatch between data and clock signals during fuse broadcasting is solved, and the reliability of fuse array broadcasting is improved.
Patent Information
- Application Number
- CN202311804385.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-25
- Publication Date
- 2025-06-27
AI Technical Summary
Since the local register setting positions in the memory device are relatively dispersed, it is easy to cause mismatch between broadcast data and broadcast clock signals during fuse broadcasting, resulting in errors in data transmitted to local registers, which reduces the reliability of fuse array broadcasting.
A broadcast circuit of a fuse array is designed, including a broadcast address detector and N sub-broadcast circuits, each sub-broadcast circuit comprising a gate circuit, a broadcast bus and a latch circuit. N enable signals are generated by the broadcast address detector. The sub-broadcast circuit outputs the gated broadcast clock signal and broadcast data when the enable signal is valid, and transmits it to the latch circuit through the broadcast bus.
Data transmission is carried out through the dispersed sub-broadcast circuit, which reduces the winding length of the broadcast bus, reduces the risk of data and clock signals mismatch, and improves the reliability of fuse array broadcasting.
Smart Images
Figure CN120220772A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a broadcast circuit for a fuse array and a broadcast method for a fuse array. Background Art
[0002] A memory device may include a storage array and a fuse array. Among them, the fuse array can store repair information or other operation information related to the storage array. After the memory device is powered on, fuse broadcasting is required to transmit the data stored in the fuse array to each local register of the memory device through a broadcast circuit. However, since the setting positions of the local registers in the memory device are relatively scattered, the fuse broadcast process is prone to a situation where the broadcast data is mismatched with the broadcast clock signal, resulting in errors in the data finally transmitted to the local registers. Therefore, how to improve the reliability of fuse broadcasting has become an urgent problem to be solved at present. Summary of the Invention
[0003] In view of this, embodiments of the present disclosure provide a broadcast circuit for a fuse array and a broadcast method for a fuse array to solve at least one problem existing in the prior art.
[0004] To achieve the above object, the technical solutions of the embodiments of the present disclosure are implemented as follows:
[0005] In a first aspect, an embodiment of the present disclosure provides a broadcast circuit for a fuse array, including:
[0006] A broadcast address detector configured to: receive a broadcast fuse address count to generate N enable signals; where N is a positive integer greater than 1;
[0007] N sub-broadcast circuits; each of the sub-broadcast circuits includes:
[0008] A gating circuit connected to the fuse array and the broadcast address detector, and configured to: receive one of the enable signals, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid;
[0009] A broadcast bus and a latch circuit, the broadcast bus is connected to the gating circuit and the latch circuit; the broadcast bus is configured to: transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.
[0010] In an optional implementation manner, the broadcast circuit of the fuse array further includes:
[0011] A broadcast clock signal generation circuit configured to: generate the broadcast clock signal in response to a fuse broadcast command;
[0012] The broadcast address counting circuit is configured to: receive the broadcast clock signal and generate the broadcast fuse address count; the fuse array is configured to: receive the broadcast fuse address count and output the broadcast data.
[0013] In an alternative embodiment, the broadcast address detector is specifically configured to:
[0014] Receive the broadcast fuse address count to generate the number of fuses broadcast;
[0015] Compare the number of fuses broadcast with the preset numbers in the preset list to generate the N enable signals; the preset list includes N of the preset numbers; at most one of the N enable signals is valid.
[0016] In an alternative embodiment, the gating circuit includes:
[0017] A clock gating circuit configured to: perform a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal;
[0018] A data gating circuit configured to: perform a logical operation on the enable signal and the broadcast data to generate the gated broadcast data.
[0019] In an alternative embodiment, both the clock gating circuit and the data gating circuit include a NAND gate and a NOT gate; the output terminal of the NAND gate is connected to the input terminal of the NOT gate; wherein,
[0020] The NAND gate of the clock gating circuit is configured to: receive the enable signal and the broadcast clock signal and output an intermediate broadcast clock signal;
[0021] The NOT gate of the clock gating circuit is configured to: receive the intermediate broadcast clock signal and output the gated broadcast clock signal;
[0022] The NAND gate of the data gating circuit is configured to: receive the enable signal and the broadcast data and output intermediate broadcast data;
[0023] The NOT gate of the data gating circuit is configured to: receive the intermediate broadcast data and output the gated broadcast data.
[0024] In an alternative embodiment, the latching circuit includes M flip-flops and M latches; the control terminal of each latch is connected to the output terminal of one of the flip-flops; M is a positive integer greater than 1; wherein,
[0025] The M flip - flops are configured to: receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid;
[0026] The latch is configured to: receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.
[0027] In an alternative embodiment, the M flip - flops are connected in series; the first flip - flop among the M flip - flops includes:
[0028] A first data input terminal, configured to: receive a ground voltage;
[0029] A first clock input terminal, configured to: receive the gated broadcast clock signal;
[0030] A set terminal, configured to: receive the enable signal;
[0031] The flip - flops among the M flip - flops other than the first flip - flop include:
[0032] A second data input terminal, connected to the output terminal of the previous flip - flop;
[0033] A second clock input terminal, configured to: receive the gated broadcast clock signal;
[0034] A reset terminal, configured to: receive the enable signal.
[0035] In a second aspect, an embodiment of the present disclosure provides a broadcast method for a fuse array, including:
[0036] A broadcast address detector receives a broadcast fuse address count to generate N enable signals; the N is a positive integer greater than 1;
[0037] The gating circuit of one of the N sub - broadcast circuits receives one of the enable signals, a broadcast clock signal, and broadcast data, and outputs a gated broadcast clock signal and gated broadcast data when the enable signal is valid;
[0038] The broadcast bus of the one sub - broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to a latch circuit.
[0039] In an alternative embodiment, the broadcast address detector receives a broadcast fuse address count to generate N enable signals, including:
[0040] The broadcast address detector receives the broadcast fuse address count to generate the number of fuses that have been broadcast;
[0041] Compare the number of fuses that have been broadcast with a preset number in a preset list to generate the N enable signals; the preset list includes N of the preset numbers; at most one of the N enable signals is valid.
[0042] In an alternative embodiment, the gating circuit of one of the N sub-broadcast circuits receives one of the enable signals, a broadcast clock signal, and broadcast data, and outputs a gated broadcast clock signal and gated broadcast data when the enable signal is valid, including:
[0043] The clock gating circuit performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal;
[0044] The data gating circuit performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data.
[0045] In an alternative embodiment, the clock gating circuit performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal, including:
[0046] The NAND gate of the clock gating circuit receives the enable signal and the broadcast clock signal and outputs an intermediate broadcast clock signal;
[0047] The NOT gate of the clock gating circuit receives the intermediate broadcast clock signal and outputs the gated broadcast clock signal;
[0048] The data gating circuit performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data, including:
[0049] The NAND gate of the data gating circuit receives the enable signal and the broadcast data and outputs intermediate broadcast data;
[0050] The NOT gate of the data gating circuit receives the intermediate broadcast data and outputs the gated broadcast data.
[0051] In an alternative embodiment, the broadcast method of the fuse array further includes:
[0052] M flip-flops in the latch circuit receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; M is a positive integer greater than 1;
[0053] The latch in the latch circuit receives the selection control signal and the gated broadcast data, and latches and outputs the gated broadcast data when the selection control signal is valid.
[0054] In the technical solution provided by the present disclosure, the broadcast address detector can generate N enable signals. Each of the N sub-broadcast circuits in the N sub-broadcast circuits can receive an enable signal. The gating circuit in the sub-broadcast circuit can output the gated broadcast data and the gated broadcast clock signal when the enable signal is valid. The broadcast bus in the sub-broadcast circuit can transmit the gated broadcast data and the gated broadcast clock signal to the latch circuit. The latch circuit can receive the gated broadcast data when the enable signal is valid. At most one of the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively. The length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, through the broadcast circuit of the fuse array provided by the present disclosure, the wiring length of the broadcast bus can be reduced, and the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast of the fuse array can be reduced, thereby improving the reliability of the broadcast of the fuse array. Description of the Drawings
[0055] Figure 1 Schematic diagram of the broadcast circuit of the fuse array provided by the embodiment of the present disclosure;
[0056] Figure 2 Schematic diagram of the composition of the gating circuit provided by the embodiment of the present disclosure;
[0057] Figure 3 Circuit diagram of the gating circuit provided by the embodiment of the present disclosure;
[0058] Figure 4 Circuit diagram of the latch circuit provided by the embodiment of the present disclosure;
[0059] Figure 5 Arrangement schematic of the broadcast circuit of the fuse array provided by the embodiment of the present disclosure Figure 1 ;
[0060] Figure 6 Arrangement schematic of the broadcast circuit of the fuse array provided by the embodiment of the present disclosure Figure 2 ;
[0061] Figure 7 Flow chart of the broadcast method of the fuse array provided by the embodiment of the present disclosure. Detailed Embodiments
[0062] Exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.
[0063] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.
[0064] In the drawings, the same reference numerals throughout the drawings denote the same elements.
[0065] It should be understood that the spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "upper", etc. are used herein for convenience of description to describe the relationship of one element or feature shown in the drawings with other elements or features. It should be understood that, in addition to the orientation shown in the drawings, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial description terms used herein are to be interpreted accordingly.
[0066] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0067] A memory device may include a storage array and a fuse array. The storage array is configured to store user data, and the fuse array is configured to store repair information related to the storage array, such as row repair information, column repair information, etc., as well as other operation information. After the memory device is powered on, fuse broadcasting is required to transmit the data stored in the fuse array to each local register of the memory device through a broadcast circuit, so that the memory device can read the data stored in the fuse array when performing operations such as reading and writing. However, since the setting positions of the local registers in the memory device are relatively scattered, the broadcast bus needs to pass through all the local registers, so the routing of the broadcast bus is relatively long, and it is easy to generate a mismatch between the broadcast data and the broadcast clock signal during the fuse broadcasting process, resulting in incorrect data transmitted to the local registers eventually, and the reliability of the fuse broadcasting is reduced.
[0068] Therefore, how to improve the reliability of fuse broadcasting has become an urgent problem to be solved at present. In this regard, the present disclosure proposes the following embodiments.
[0069] The present disclosure provides a broadcast circuit for a fuse array, including: a broadcast address detector configured to receive a broadcast fuse address count to generate N enable signals; N is a positive integer greater than 1; N sub-broadcast circuits; each sub-broadcast circuit includes: a gating circuit connected to the fuse array and the broadcast address detector, and configured to receive an enable signal, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid; a broadcast bus and a latch circuit, the broadcast bus is connected to the gating circuit and the latch circuit; the broadcast bus is configured to transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.
[0070] In an embodiment of the present disclosure, the broadcast circuit of the fuse array includes N sub-broadcast circuits, and the data stored in the fuse array can be broadcasted via the N sub-broadcast circuits respectively. Hereinafter, the broadcast circuit of the fuse array provided by the present disclosure will be described in detail by taking N equal to 2 as an example.
[0071] Figure 1 is a schematic diagram of the broadcast circuit of the fuse array provided by an embodiment of the present disclosure. As Figure 1 shown, the broadcast circuit of the fuse array includes: a broadcast address detector 101 and two sub-broadcast circuits. Each sub-broadcast circuit includes a gating circuit, a broadcast bus, and a latch circuit. Among them, the first sub-broadcast circuit 200 includes a gating circuit 201, a broadcast bus 202, and a latch circuit 203, and the second sub-broadcast circuit 300 includes a gating circuit 301, a broadcast bus 302, and a latch circuit 303.
[0072] In some embodiments, the broadcast circuit of the fuse array further includes: a broadcast address counting circuit 102 and a broadcast clock signal generating circuit 103. The broadcast circuit of the fuse array can be enabled in response to a fuse broadcast command. The broadcast clock signal generating circuit 103 can generate a broadcast clock signal, and the broadcast address counting circuit 102 can receive the broadcast clock signal and generate a broadcast fuse address count based on the broadcast clock signal.
[0073] In some specific examples, the fuse array 100 can include multiple regions, and each region includes multiple fuse storage units arranged in an array. The broadcast address counting circuit 102 can sequentially send multiple groups of broadcast fuse address counts to the fuse array 100 and the broadcast address detector 101. A group of broadcast fuse address counts can include a region count, a row address count, and a column address count, and corresponds to a fuse storage unit in the fuse array 100. The fuse array 100 can output the data stored in a fuse storage unit corresponding to the broadcast fuse address count after receiving the broadcast fuse address count. The data output by the fuse array 100 is the broadcast data.
[0074] In some embodiments, the broadcast address detector 101 is specifically configured to: receive the broadcast fuse address count to generate the number of fuses that have been broadcast; compare the number of fuses that have been broadcast with a preset number in a preset list to generate N enable signals.
[0075] In the embodiments of the present disclosure, the broadcast progress of the fuse array can be controlled by the broadcast address detector 101. The broadcast address detector 101 can include a preset list, and the preset list includes N preset numbers. Taking N as 2 as an example, the number of fuses that the first sub-broadcast circuit 200 can broadcast is X, and the number of fuses that the second sub-broadcast circuit 300 can broadcast is Y. Then the preset list can include two preset numbers. The first preset number can be X, and the second preset number can be X + Y. The broadcast address detector 101 can receive the broadcast fuse address count to generate the number of fuses that have been broadcast, and compare the number of fuses that have been broadcast with the first preset number and the second preset number. The broadcast address detector 101 can generate an enable signal 1 and an enable signal 2 based on the comparison result of the number of fuses that have been broadcast and the preset numbers. The first sub-broadcast circuit 200 can receive the enable signal 1, and the second sub-broadcast circuit 300 can receive the enable signal 2. Specifically, when the number of fuses that have been broadcast is less than X, the enable signal 1 is valid and the enable signal 2 is invalid, and the broadcast data can be broadcast through the first sub-broadcast circuit 200; when the number of fuses that have been broadcast is greater than or equal to X and less than X + Y, the enable signal 1 is invalid and the enable signal 2 is valid, and the broadcast data can be broadcast through the second sub-broadcast circuit 300; when the number of fuses that have been broadcast is equal to X + Y, both the enable signal 1 and the enable signal 2 are invalid, and the broadcast of the fuse array is completed.
[0076] It should be noted that, in the embodiments of the present disclosure, a signal being valid means that the signal is at the first logic level, and a signal being invalid means that the signal is at the second logic level. The first logic level may be a high level relative to the second logic level, and the second logic level may be a low level relative to the first logic level.
[0077] In some embodiments, the broadcast clock signal generated by the broadcast clock signal generation circuit 103 may also serve as the clock signal for the fuse array 100 to output broadcast data. Moreover, the broadcast clock signal and the broadcast data may be output synchronously and may be transmitted to the latch circuit via the gating circuit and the broadcast bus in the sub-broadcast circuit.
[0078] In the embodiments of the present disclosure, the gating circuits in the N sub-broadcast circuits may have the same circuit structure. Hereinafter, the composition and circuit structure of the gating circuit will be described by taking the gating circuit 201 in the first sub-broadcast circuit 200 as an example.
[0079] In some embodiments, Figure 2 is a schematic diagram of the composition of the gating circuit provided by the embodiments of the present disclosure. As Figure 2 shown, the gating circuit 201 includes: a clock gating circuit 2011, configured to perform a logical operation on the enable signal 1 and the broadcast clock signal to generate a gated broadcast clock signal; and a data gating circuit 2012, configured to perform a logical operation on the enable signal 1 and the broadcast data to generate a gated broadcast data.
[0080] In a specific example, Figure 3 is the circuit diagram of the gating circuit provided by the embodiments of the present disclosure. With reference to Figure 1 、 Figure 2 and Figure 3 , both the clock gating circuit 2011 and the data gating circuit 2012 include a NAND gate and a NOT gate, and the output terminal of the NAND gate is connected to the input terminal of the NOT gate. Among them, the NAND gate 2013 of the clock gating circuit 2011 is configured to receive the enable signal 1 and the broadcast clock signal and output an intermediate broadcast clock signal; the NOT gate 2014 of the clock gating circuit 2011 is configured to receive the intermediate broadcast clock signal and output a gated broadcast clock signal; the NAND gate 2015 of the data gating circuit 2012 is configured to receive the enable signal 1 and the broadcast data and output an intermediate broadcast data; the NOT gate 2016 of the data gating circuit 2012 is configured to receive the intermediate broadcast data and output a gated broadcast data.
[0081] In an embodiment of the present disclosure, a gating circuit in a sub-broadcast circuit receives an enable signal, and N enable signals generated by a broadcast address detector are correspondingly output to N sub-broadcast circuits. Only when the enable signal received by the gating circuit is valid, the gating circuit will output a gated broadcast clock signal and gated broadcast data. At most one of the N enable signals is valid, so that the data stored in the fuse array can be broadcast through different sub-broadcast circuits respectively.
[0082] In some embodiments, the broadcast bus may include a data bus and a clock bus. The data bus may be configured to transmit the gated broadcast data to a latch circuit, and the clock bus may be configured to transmit the gated broadcast clock signal to the latch circuit.
[0083] In some embodiments, Figure 4 is a circuit diagram of the latch circuit provided by the embodiment of the present disclosure. With reference to Figure 1 and Figure 4 , taking the latch circuit 203 in the first sub-broadcast circuit 200 as an example, the latch circuit in the broadcast circuit provided by the present disclosure will be described.
[0084] In some embodiments, as Figure 4 shown, the latch circuit 203 includes M flip-flops and M latches, and the control terminal of each latch is connected to the output terminal of a flip-flop; M is a positive integer greater than 1. Here, taking M equal to 3 as an example, the latch circuit 203 includes three flip-flops and three latches. Among them, the output terminal Q of the first flip-flop 2031 is connected to the control terminal Lat of the first latch 2034 and is connected to the inverted control terminal LatN of the first latch 2034 through an inverter; the output terminal Q of the second flip-flop 2032 is connected to the control terminal Lat of the second latch 2035 and is connected to the inverted control terminal LatN of the second latch 2035 through an inverter; the output terminal Q of the third flip-flop 2033 is connected to the control terminal Lat of the third latch 2036 and is connected to the inverted control terminal LatN of the third latch 2036 through an inverter.
[0085] In an embodiment of the present disclosure, the M flip-flops in the latch circuit are configured to: receive the gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid. At most one of the M selection control signals is valid; the latch is configured to: receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.
[0086] In some specific examples, continue to refer to Figure 4, the three flip - flops in the latch circuit 203 are configured to: receive the gated broadcast clock signal and the enable signal 1, and output three selection control signals when the enable signal 1 is valid. The three flip - flops are connected in series. The first flip - flop 2031 includes: a first data input terminal D, configured to receive the ground voltage VSS; a first clock input terminal CK, configured to receive the gated broadcast clock signal; a set terminal SN, configured to receive the enable signal 1. The flip - flops other than the first flip - flop 2031 among the three flip - flops include: a second data input terminal D, connected to the output terminal Q of the previous flip - flop. For example, the data input terminal D of the second flip - flop 2032 is connected to the output terminal Q of the first flip - flop 2031, and the data input terminal D of the third flip - flop 2033 is connected to the output terminal Q of the second flip - flop 2032; a second clock input terminal CK, configured to receive the gated broadcast clock signal; a reset terminal RN, configured to receive the enable signal 1.
[0087] In the embodiment of the present disclosure, when the enable signal 1 is valid, the first flip - flop 2031 can generate the selection control signal 1, the second flip - flop 2032 can generate the selection control signal 2, and the third flip - flop 2033 can generate the selection control signal 3. At the same moment, at most one selection control signal is valid, that is, at most one latch is enabled at the same moment. The data input terminal D of the enabled latch receives the gated broadcast data, latches it and outputs one bit of the gated broadcast data from the output terminal Q.
[0088] In some specific examples, the latch circuit 303 in the second sub - broadcast circuit 300 may have a circuit structure similar to that of the latch circuit 203 in the first sub - broadcast circuit 200.
[0089] It should be noted that the above - mentioned embodiment takes M equal to 3 as an example, but the present disclosure is not limited thereto. In other embodiments, M can be any positive integer greater than 1, such as 4, 7, 16, 32, etc.
[0090] In the embodiments of the present disclosure, a broadcast address detector can generate N enable signals. Each of the N sub-broadcast circuits can receive one enable signal. The gating circuit in the sub-broadcast circuit can output gated broadcast data and a gated broadcast clock signal when the enable signal is valid. The broadcast bus in the sub-broadcast circuit can transmit the gated broadcast data and the gated broadcast clock signal to a latch circuit. The latch circuit can latch and output the gated broadcast data when the enable signal is valid. At most one of the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively. The length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, through the broadcast circuit of the fuse array provided by the present disclosure, the routing length of the broadcast bus can be reduced, and the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast of the fuse array can be reduced, thereby improving the reliability of the broadcast of the fuse array.
[0091] In some embodiments, multiple latches and multiple flip-flops in the latch circuit can constitute local registers, such as the local register of the row decoder, the local register of the column decoder, and the test mode register. Among them, the local register of the row decoder can store the row repair information in the fuse array, the local register of the column decoder can store the column repair information in the fuse array, and the test mode register can store the relevant parameter information for the memory device test in the fuse array.
[0092] In some specific examples, Figure 5 is a layout schematic diagram of the broadcast circuit of the fuse array provided by the embodiments of the present disclosure. For easy observation, the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit are shown in a perspective view. As Figure 5As shown, the fuse array 400 is located in the peripheral circuit on one side of the memory bank 407 in the Y direction. The broadcast circuit of the fuse array includes two sub-broadcast circuits connected to the fuse array 400. Among them, the broadcast bus 401 in the first sub-broadcast circuit extends along the X direction and is connected to a plurality of test mode registers 403 arranged along the X direction on one side of the fuse array 400. The broadcast bus 402 in the second sub-broadcast circuit includes a part extending along the X direction and a part extending along the Y direction, and is connected to a plurality of registers between the two memory banks 407. The plurality of registers may include local registers 404 of a plurality of column decoders, local registers 405 of a plurality of row decoders, and a plurality of test mode registers 406. In this example, compared with a single broadcast bus that needs to be connected to a plurality of test mode registers 403 on one side of the fuse array 400 and a plurality of registers between the two memory banks 407, the lengths of the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit are smaller. At the same time, one of the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit is enabled, so that the routing length of the broadcast bus for transmitting broadcast data and broadcast clock signals can be reduced, the risk of mismatch between broadcast data and broadcast clock signals during the broadcast process can be reduced, and the reliability of the fuse array broadcast can be improved.
[0093] In some specific examples, Figure 6 This is a schematic diagram of the layout of the broadcast circuit of the fuse array provided by the embodiment of the present disclosure. For the convenience of observation, the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit are shown in a perspective view. As Figure 6As shown, the fuse array 500 is located in the peripheral circuit between two memory banks 510. The broadcast circuit of the fuse array includes two sub-broadcast circuits connected to the fuse array 500. Among them, the broadcast bus 501 in the first sub-broadcast circuit includes a portion extending in the X direction and a portion extending in the Y direction, and is connected to the test mode register 503 and multiple registers located on one side of the fuse array 500. The multiple registers may include local registers 504 of multiple column decoders, local registers 505 of multiple row decoders, and test mode register 506. The broadcast bus 502 in the second sub-broadcast circuit also includes a portion extending in the X direction and a portion extending in the Y direction, and is connected to the test mode register 503 and multiple registers located on the other side of the fuse array 500. The multiple registers may include test mode register 507. In this example, compared with a single broadcast bus that needs to be connected to all the registers on both sides of the fuse array 500, the lengths of the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit are smaller. At the same time, one of the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit is enabled, so that the routing length of the broadcast bus for transmitting broadcast data and broadcast clock signals can be reduced, the risk of mismatch between broadcast data and broadcast clock signals during the broadcast process can be reduced, and the reliability of the fuse array broadcast can be improved.
[0094] It should be noted that Figure 5 and Figure 6 some of the registers are not directly connected to the broadcast bus, and the branches for connecting these registers to the broadcast bus are omitted in the figure. In addition, Figure 5 and Figure 6 structures such as the broadcast address detector in the broadcast circuit and the gating circuit in the sub-broadcast circuit are omitted in the figure, and their functions and circuit structures can be referred to the descriptions of Figure 1 , Figure 2 and Figure 3 in the foregoing embodiments.
[0095] It should be noted that, in the above embodiments, N is taken as 2 as an example, but the present disclosure is not limited thereto. In other embodiments, N may be any positive integer greater than 1, such as 3, 4, 5, etc. For example, when N is equal to 4, the broadcast circuit of the fuse array may include four sub-broadcast circuits, and each sub-broadcast circuit includes a gating circuit, a broadcast bus, and a latch circuit; the broadcast address detector may compare the number of fuses that have been broadcast with four preset numbers in a preset list and generate four enable signals; the four sub-broadcast circuits respectively receive the four enable signals, and at most one of the four enable signals is valid, that is, at most one of the four gating circuits can output the gated broadcast data and the gated broadcast clock signal, so that the data in the fuse array can be broadcast through the four sub-broadcast circuits respectively. Without changing the number of local registers, the length of each broadcast bus can be further reduced, thereby further reducing the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast process and improving the reliability of the fuse array broadcast.
[0096] Based on a concept similar to the broadcast circuit of the above fuse array, the present disclosure also provides a broadcast method for a fuse array. Figure 7 It is a schematic flowchart of the broadcast method for the fuse array provided by the embodiment of the present disclosure. As Figure 7 shown, the broadcast method for the fuse array includes the following steps.
[0097] Step S10: The broadcast address detector receives the broadcast fuse address count to generate N enable signals; N is a positive integer greater than 1.
[0098] Step S20: The gating circuit of one sub-broadcast circuit among the N sub-broadcast circuits receives an enable signal, a broadcast clock signal, and broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid.
[0099] Step S30: The broadcast bus of one sub-broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to a latch circuit.
[0100] In some embodiments, with reference to Figure 1 and Figure 7 specifically, the process of step S10 includes: the broadcast address detector 101 receives the broadcast fuse address count to generate the number of fuses that have been broadcast; compares the number of fuses that have been broadcast with the preset numbers in a preset list to generate N enable signals; the preset list includes N preset numbers; at most one of the N enable signals is valid. Here, taking N equal to 2 as an example, the broadcast address detector 101 may generate enable signal 1 and enable signal 2.
[0101] In some embodiments, with reference to Figure 2and Figure 7 Taking the broadcast of the fuse array by the first sub-broadcast circuit 200 as an example, the specific process of step S20 includes: The clock gating circuit 2011 performs a logical operation on the enable signal 1 and the broadcast clock signal to generate a gated broadcast clock signal; the data gating circuit 2012 performs a logical operation on the enable signal 1 and the broadcast data to generate a gated broadcast data.
[0102] In some embodiments, with reference to Figure 3 and Figure 7 Taking the broadcast of the fuse array by the first sub-broadcast circuit 200 as an example, the specific process of step S20 may include: The NAND gate 2013 of the clock gating circuit receives the enable signal 1 and the broadcast clock signal, and outputs an intermediate broadcast clock signal; the NOT gate 2014 of the clock gating circuit receives the intermediate broadcast clock signal and outputs a gated broadcast clock signal; the NAND gate 2015 of the data gating circuit receives the enable signal 1 and the broadcast data, and outputs an intermediate broadcast data; the NOT gate 2016 of the data gating circuit receives the intermediate broadcast data and outputs a gated broadcast data.
[0103] In some embodiments, with reference to Figure 4 and Figure 7 Taking the broadcast of the fuse array by the first sub-broadcast circuit 200 as an example, the broadcast method of the fuse array further includes: M flip-flops in the latch circuit 203 receive the gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; M is a positive integer greater than 1; the latch in the latch circuit 203 receives the selection control signal and the gated broadcast data, and latches and outputs the gated broadcast data when the selection control signal is valid.
[0104] In some specific examples, with reference to Figure 1 and Figure 7 Before step S10, the broadcast circuit of the fuse array can be enabled in response to a fuse broadcast command. The broadcast method of the fuse array further includes: The broadcast clock signal generation circuit 103 generates a broadcast clock signal, and the broadcast address counting circuit 102 receives the broadcast clock signal and generates a broadcast fuse address count based on the broadcast clock signal.
[0105] In some specific examples, with reference to Figure 1 and Figure 7, The specific process of step S10 may include that the broadcast address detector 101 receives the number of fuses whose broadcast fuse addresses have been counted; compares the number of fuses whose broadcast addresses have been counted with the preset numbers in the preset list to generate enable signal 1 and enable signal 2. Here, the preset list may include two preset numbers. The first preset number may be the number of fuses X that the first sub-broadcast circuit 200 can broadcast, and the second preset number may be the sum X + Y of the number of fuses that the first sub-broadcast circuit 200 can broadcast and the number of fuses that the second sub-broadcast circuit 300 can broadcast.
[0106] In some specific examples, with reference to Figure 1 and Figure 7 , the broadcast method of the fuse array may include: when the number of fuses whose broadcast addresses have been counted is less than X, enable signal 1 is valid and enable signal 2 is invalid, and the broadcast data can be broadcast through the first sub-broadcast circuit 200, including: step S20, the gating circuit 201 in the first sub-broadcast circuit 200 receives enable signal 1, the broadcast clock signal and the broadcast data, and outputs the first gated broadcast clock signal and the first gated broadcast data; step S30, the broadcast bus 202 in the first sub-broadcast circuit 200 transmits the first gated broadcast clock signal and the first gated broadcast data to the latch circuit 203; the latch circuit 203 receives enable signal 1, the first gated broadcast clock signal and the first gated broadcast data, latches and outputs the first gated broadcast data.
[0107] In some specific examples, with reference to Figure 1 and Figure 7 , the broadcast method of the fuse array may include: when the number of fuses whose broadcast addresses have been counted is greater than or equal to X and less than X + Y, enable signal 1 is invalid and enable signal 2 is valid, and the broadcast data can be broadcast through the second sub-broadcast circuit 300, including: step S20, the gating circuit 301 in the second sub-broadcast circuit 300 receives enable signal 2, the broadcast clock signal and the broadcast data, and outputs the second gated broadcast clock signal and the second gated broadcast data; step S30, the broadcast bus 302 in the second sub-broadcast circuit 300 transmits the second gated broadcast clock signal and the second gated broadcast data to the latch circuit 303; the latch circuit 303 receives enable signal 2, the second gated broadcast clock signal and the second gated broadcast data, latches and outputs the second gated broadcast data.
[0108] In some specific examples, the broadcast method of the fuse array may include: when the number of fuses whose broadcast addresses have been counted is equal to X + Y, both enable signal 1 and enable signal 2 are invalid, and the broadcast of the fuse array is completed.
[0109] In an embodiment of the present disclosure, a broadcast address detector may generate N enable signals according to the broadcast progress. Each of the N sub-broadcast circuits may receive one enable signal. A gating circuit in the sub-broadcast circuit may output gated broadcast data and a gated broadcast clock signal when the enable signal is valid. A broadcast bus in the sub-broadcast circuit may transmit the gated broadcast data and the gated broadcast clock signal to a latch circuit. The latch circuit may latch and output the gated broadcast data when the enable signal is valid. At most one of the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively. The length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, by the broadcast method of the fuse array provided by the present disclosure, the risk of mismatch between the broadcast data and the broadcast clock signal generated during the broadcast of the fuse array can be reduced, and the probability of error in the broadcast data received by the local register can be reduced, thereby improving the reliability of the fuse array broadcast.
[0110] The features disclosed in several device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain a new device embodiment.
[0111] The methods disclosed in several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain a new method embodiment.
[0112] The above is only a specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure.
Claims
1. A broadcast circuit of a fuse array, characterized in that Comprising: A broadcast address detector, configured to: receive a broadcast fuse address count and generate N enable signals; wherein N is a positive integer greater than 1; N sub-broadcast circuits; Each of the sub-broadcast circuits includes: A gating circuit, connected to the fuse array and the broadcast address detector, and configured to: receive one of the enable signals, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid; A broadcast bus and a latch circuit, the broadcast bus being connected to the gating circuit and the latch circuit; the broadcast bus is configured to: transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.
2. The broadcast circuit of the fuse array according to claim 1, characterized in that, The broadcast circuit of the fuse array further includes: A broadcast clock signal generation circuit, configured to: generate the broadcast clock signal in response to a fuse broadcast command; A broadcast address count circuit, configured to: receive the broadcast clock signal and generate the broadcast fuse address count; the fuse array is configured to: receive the broadcast fuse address count and output the broadcast data.
3. The broadcast circuit of the fuse array according to claim 1, characterized in that, The broadcast address detector is specifically configured to: Receive the broadcast fuse address count to generate the number of fuses that have been broadcast; Compare the number of fuses that have been broadcast with a preset number in a preset list to generate the N enable signals; the preset list includes N preset numbers; at most one of the N enable signals is valid.
4. The broadcast circuit of the fuse array according to claim 1, characterized in that, The gating circuit includes: A clock gating circuit, configured to perform a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal; A data gating circuit, configured to perform a logical operation on the enable signal and the broadcast data to generate the gated broadcast data.
5. The broadcast circuit of the fuse array according to claim 4, characterized in that, Both the clock gating circuit and the data gating circuit include a NAND gate and a NOT gate; the output terminal of the NAND gate is connected to the input terminal of the NOT gate; wherein, The NAND gate of the clock gating circuit is configured to: receive the enable signal and the broadcast clock signal and output an intermediate broadcast clock signal; The NOT gate of the clock gating circuit is configured to: receive the intermediate broadcast clock signal and output the gated broadcast clock signal; The NAND gate of the data gating circuit is configured to: receive the enable signal and the broadcast data and output an intermediate broadcast data; The NOT gate of the data gating circuit is configured to: receive the intermediate broadcast data and output the gated broadcast data.
6. The broadcast circuit of the fuse array according to claim 1, characterized in that, The latch circuit includes M flip-flops and M latches; the control terminal of each latch is connected to the output terminal of one of the flip-flops; M is a positive integer greater than 1; wherein, The M flip-flops are configured to: receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; The latch is configured to: receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.
7. The broadcast circuit of the fuse array according to claim 6, wherein The M flip-flops are connected in series; The first one of the M flip-flops includes: A first data input terminal, configured to: receive a ground voltage; A first clock input terminal, configured to: receive the gated broadcast clock signal; A set terminal, configured to: receive the enable signal; The flip-flops among the M flip-flops other than the first one include: A second data input terminal, connected to the output terminal of the previous flip-flop; A second clock input terminal, configured to: receive the gated broadcast clock signal; A reset terminal, configured to: receive the enable signal.
8. A broadcast method for a fuse array, characterized in that, Comprising: The broadcast address detector receives the broadcast fuse address count to generate N enable signals; The N is a positive integer greater than 1; The gating circuit of one of the N sub-broadcast circuits receives one of the enable signals, the broadcast clock signal, and the broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid; The broadcast bus of the one sub-broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to a latch circuit.
9. The broadcast method of the fuse array according to claim 8, characterized in that, The broadcast address detector receives the broadcast fuse address count to generate N enable signals, including: The broadcast address detector receives the broadcast fuse address count to generate the number of fuses that have been broadcast; Compare the number of fuses that have been broadcast with the preset numbers in the preset list to generate the N enable signals; the preset list includes N preset numbers; at most one of the N enable signals is valid.
10. The broadcast method of the fuse array according to claim 8, characterized in that, The gating circuit of one of the N sub-broadcast circuits receives one of the enable signals, the broadcast clock signal, and the broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid, including: The clock gating circuit performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal; The data gating circuit performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data.
11. The broadcast method of the fuse array according to claim 10, characterized in that, The clock gating circuit performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal, including: The NAND gate of the clock gating circuit receives the enable signal and the broadcast clock signal, and outputs an intermediate broadcast clock signal; The NOT gate of the clock gating circuit receives the intermediate broadcast clock signal and outputs the gated broadcast clock signal; The data gating circuit performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data, including: The NAND gate of the data gating circuit receives the enable signal and the broadcast data, and outputs an intermediate broadcast data; The NOT gate of the data gating circuit receives the intermediate broadcast data and outputs the gated broadcast data.
12. The broadcast method of the fuse array according to claim 8, characterized in that, The broadcast method of the fuse array further includes: M flip - flops in the latch circuit receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; M is a positive integer greater than 1; Latches in the latch circuit receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.