Multi-die transformer power supply module

Abstract

Embodiments of the application relate to a multi-die transformer power module. In an example, an isolation device (100) includes a multi-layer substrate (112) having opposing first (113) and second (115) surfaces. The multilayer substrate includes: a first coil (114) in a first layer of the substrate, the first coil having first and second terminals; a second coil (116) in a second layer of the substrate vertically spaced apart from the first layer, the second coil having third and fourth terminals; and a dielectric material (117) covering the first and second coils. The apparatus includes: a first semiconductor die (108) coupled to the first surface and the first and second terminals; a second semiconductor die (110) coupled to the second surface and the third and fourth terminals, the second semiconductor die being galvanically isolated from the first semiconductor die; a conductive terminal (104) coupled to the multilayer substrate; and a molding compound (102) covering the multilayer substrate, the first and second semiconductor dies, and the conductive terminals.

Description

Technical Field

[0001] This application relates to the technical field of semiconductors, and more particularly, to a multi-die transformer power module. Background Art

[0002] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to fabricate semiconductor chips. Typically, a number of integrated circuits are formed on a single wafer using complex manufacturing processes. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is diced into multiple pieces, called semiconductor dies, where each die contains one of the circuits. Dicing or sawing the wafer into individual dies is called singulation. The die is then coupled to a lead frame and the die is covered with a molding compound, and subsequently the molding compound is sawed to produce a package. Summary of the Invention

[0003] In an example, an isolation device includes a multi-layer substrate having opposite first and second surfaces. The multi-layer substrate includes: a first coil in a first layer of the substrate, the first coil having first and second terminals; a second coil in a second layer of the substrate vertically spaced from the first layer, the second coil having third and fourth terminals; and a dielectric material covering the first and second coils. The device includes: a first semiconductor die coupled to the first surface and the first and second terminals; a second semiconductor die coupled to the second surface and the third and fourth terminals, the second semiconductor die being electrically isolated from the first semiconductor die; conductive terminals coupled to the multi-layer substrate; and a molding compound covering the multi-layer substrate, the first and second semiconductor dies, and the conductive terminals.

[0004] In an example, a method of manufacturing an isolation device includes: coupling a first semiconductor die to a first coil of a multi-layer substrate using a first solder bump, the substrate including a second coil and a dielectric material covering the first and second coils; coupling the substrate to conductive terminals of a lead frame; coupling a second semiconductor die to the second coil using a second solder bump, the first and second semiconductor dies being coupled to opposite surfaces of the substrate; covering the substrate and the first and second semiconductor dies with a molding compound; and trimming the conductive terminals to separate the conductive terminals from the lead frame. Brief Description of the Drawings

[0005] Figure 1A is a profile cross-sectional view of an isolation device according to various examples.

[0006] Figure 1B is a top view of an isolation device according to various examples.

[0007] Figure 1CIs a perspective view of an isolation device according to various examples.

[0008] Figure 2A Is a profile cross-sectional view of an isolation device according to various examples.

[0009] Figure 2B Is a top view of an isolation device according to various examples.

[0010] Figure 2C Is a perspective view of an isolation device according to various examples.

[0011] Figure 3 Is a flowchart of a method for manufacturing an isolation device according to various examples.

[0012] Figure 4A1-4F3 Is a process flow for manufacturing an isolation device according to various examples.

[0013] Figure 5A And 5B Is a top view of an isolation device substrate coil indicating temperature according to various examples.

[0014] Figure 6A Is a graph depicting the operating behavior of an isolation device according to various examples.

[0015] Figure 6B And 6C Depicts a representative isolation device that can be represented as depicted by the curves in the graph in Figure 6A Specific embodiments

[0016] ​Some isolation devices include a laminated transformer and optionally include semiconductor dies coupled to the transformer. Some isolation devices include a plurality of coplanar die pads, where a first die pad is coupled to the transformer, a second die pad is coupled to the semiconductor die, and a third die pad is coupled to a different semiconductor die. Some isolation devices include a plurality of coplanar semiconductor dies coupled to the top surface of the transformer. Some isolation devices include a transformer coil that is directly wire bonded to a bond pad or lead of the isolation device. These isolation devices have a number of technical drawbacks. For example, the dies and the transformer in these configurations are not able to adequately dissipate the heat that is typically generated in power applications. Additionally, in some of the isolation devices described above, wire bonds are used to couple the dies to the transformer. These wire bonds inherently introduce parasitic effects into the isolation device, and because the wire bonds are serially coupled with the coils of the transformer, the wire bonds introduce inductance asymmetry and leakage in series with the magnetic component into the isolation device, which can adversely affect the operation of the isolation device. Therefore, engineers must consider such wire bond parasitic effects during the design phase, which presents significant technical challenges due to limited modeling capabilities during the design phase and additional design margins that must be considered. In some of the isolation devices described above, in order to comply with spatial design constraints, the semiconductor dies must be closely spaced. When there is a voltage potential between the dies, especially in current isolation applications, this proximity between the dies forms a high electric field region between the dies, which can adversely affect the operation of the isolation device and the current isolation capability. Additionally, in isolation devices where the semiconductor dies are coupled to the same side of the transformer, the transformer must be specifically designed to provide coil terminals to the respective semiconductor dies, which can prove to be spatially challenging when fewer transformer coil layers are required. Isolation devices designed to address these issues face their own challenges. For example, isolation devices designed to minimize the number of transformer layers are severely limited in terms of the possible number of transformer coil turns.

[0017] The present disclosure describes various examples of isolation devices that mitigate the various technical challenges described above. In an example, an isolation device includes a multilayer substrate having opposing first and second surfaces. The multilayer substrate includes a first coil in a first layer of the substrate. The first coil has first and second terminals. A second coil in a second layer of the substrate is vertically spaced apart from the first layer. The second coil has third and fourth terminals. The substrate also includes an insulating material covering the first and second coils. The isolation device includes a first semiconductor die coupled to the first surface and the first and second terminals, a second semiconductor die coupled to the second surface and the third and fourth terminals, a conductive terminal coupled to the multilayer substrate, and a molding compound. The molding compound covers the multilayer substrate, the first and second semiconductor dies, and the conductive terminal. Such isolation devices are technically advantageous for several reasons. First, because the first and second semiconductor dies are positioned on opposing first and second surfaces of the substrate, they respectively facilitate heat dissipation from the first and second coils. Second, by positioning the first and second dies on opposing surfaces of the substrate, the electric fields generated between semiconductor dies on the same surface of the substrate and the adverse effects of the electric fields on the operation of the isolation device are significantly reduced. Third, by positioning the first and second dies on opposing surfaces of the substrate, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated. Fourth, because the first and second semiconductor dies are coupled to their respective terminals by metal (e.g., solder) bumps rather than bond wires, the drawbacks introduced by bond wire parasitic effects as described above are mitigated. Fifth, the isolation device achieves operational symmetry, thus mitigating the detrimental operational effects of external interference acting on the isolation device. Sixth, because positioning the semiconductor dies on opposing surfaces of the multilayer substrate makes the wiring of the coils in the substrate less complex (e.g., by eliminating the need for complex coil terminal configurations), fewer layers can be used in the substrate, resulting in a thinner substrate and a thinner isolation device (e.g., up to 50% thinner). Various examples of the isolation device are now described with reference to the drawings.

[0018] Figure 1AFIG. 0 is a contour cross-sectional view of an isolation device 100 (e.g., a package) according to various examples. The isolation device 100 can be included in any suitable electronic device or system. For example, the isolation device 100 can be included in a personal computer, laptop computer, desktop computer, notebook computer, tablet computer, smart phone, appliance (e.g., refrigerator, television, audio player, video player, video recorder, lighting device, etc.), automobile, airplane, spacecraft, etc. The isolation device 100 can include a molding compound 102 that covers various structures including portions of conductive terminals (e.g., leads) 104, a semiconductor die 108 having a device side 109 in which a circuit system is formed, and a semiconductor die 110 having a device side 111 in which a circuit system is formed. In an example, the semiconductor dies 108, 110 can be electrically isolated from each other and can operate in different voltage domains. In an example, the semiconductor dies 108, 110 are "flip chip" coupled to a substrate 112, meaning that the device sides 109, 111 face the substrate 112 and the isolation device 100 does not have bond wires. The isolation device 100 includes and the molding compound 102 covers a multilayer substrate 112 having opposing surfaces 113, 115. Surface 113 is coupled to the semiconductor die 108, and surface 115 is coupled to the semiconductor die 110. In some examples, the semiconductor dies 108, 110 are vertically overlapping, meaning that a vertical line orthogonal to the surfaces 113, 115 of the substrate 112 extends through both of the semiconductor dies 108, 110. In other examples, the semiconductor dies 108, 110 are not vertically overlapping, meaning that a vertical line orthogonal to the surfaces 113, 115 of the substrate 112 does not extend through both of the semiconductor dies 108, 110. The semiconductor dies 108, 110 are vertically separated by a distance in the range of 100 to 500 microns, where a distance below this range is disadvantageous because the material composition of the substrate 112 will limit the dielectric strength of the isolation barrier, the mechanical stability of the substrate 112, and the parasitic barrier capacitance, and where a distance above this range is disadvantageous because the coupling between the coils of the transformer is reduced for the coil sizes that can be integrated into the isolation device 100. However, this distance depends on the breakdown voltage capability of the material that makes up the substrate 112. For example, a silica substrate 112 can have a thickness of 15 - 20 microns, depending on the operating voltage intended to be used. For an organic substrate having a lower dielectric strength and thus a lower breakdown voltage, this distance is increased.

[0019] In an example, the multi-layer substrate 112 includes a plurality of transformer coils 114, 116 positioned in different layers of the substrate 112. In an example, coil 114 is in a layer of substrate 112 that is between surface 113 and surface 115 and between surface 113 and the layer in which coil 116 is located. Similarly, in an example, coil 116 is in a layer of substrate 112 that is between surface 113 and surface 115 and between surface 115 and the layer in which coil 114 is located. Coils 114, 116 are formed of any suitable type of metal or metal alloy (e.g., copper). Any number of coils (i.e., two or more) may be used. Each coil 114, 116 may have any suitable number of turns. In examples where more than two coils are used, each such coil may have any suitable number of turns. In an example, coil 114 is exposed to surface 113, and in other examples, coil 114 is embedded within substrate 112 such that coil 114 is not exposed to surface 113. In an example, coil 116 is exposed to surface 115, and in other examples, coil 116 is embedded within substrate 112 such that coil 116 is not exposed to surface 115. In some examples, coils 114, 116 are vertically overlapped, as defined vertically overlap above.

[0020] Substrate 112 includes traces 118 that can be horizontally coplanar with coil 114. Substrate 112 includes traces 120 that can be horizontally coplanar with coil 116. Trace 120 is coupled to conductive terminal 104, for example, by soldering or any other suitable coupling technique. Trace 118 can be coupled to conductive terminal 104 by means of one or more of traces 120. Trace 118 can be coupled to trace 120 by means of vias 122. Solder bumps 124 couple the device side 109 of semiconductor die 108 to the terminals of coil 114 and to trace 118. Similarly, solder bumps 126 couple the device side 111 of semiconductor die 110 to the terminals of coil 116 and to at least some of traces 120. Substrate 112 includes a dielectric material 117 (e.g., a solid non-air dielectric material, such as a build-up film, a BT laminate, or another suitable build-up film), which contacts the metal structures of substrate 112, such as coils 114, 116, traces 118, 120, and vias 122. In some examples, conductive terminal 104 is coupled to surface 115, and in other examples, conductive terminal 104 is coupled to surface 113 (by means of metal trace 118 and Figure 1A additional metal traces 118 not explicitly shown in).

[0021] A multi-layer substrate is defined as a component of a semiconductor package, where the component includes a plurality of metal layers formed by plating (e.g., electroplating), and also includes a dielectric, such as a molding compound or a film (e.g., Stacked film (ABF)). The multi-layer substrate is different from a printed circuit board (PCB) in that the multi-layer packaging substrate is within the isolation device 100, while the PCB is outside the isolation device 100. The multi-layer substrate includes a plurality of metal layers separated by a solid, tangible dielectric, while the PCB may include a multi-layer printed circuit board that may not be separated by a dielectric material other than air.

[0022] In operation, the semiconductor die 108 supplies power and / or data to the coil 114 and receives power and / or data from the coil. The semiconductor die 110 supplies power to the coil 116 and receives power from the coil. When energized by the semiconductor die 108, the coil 114 generates a fluctuating magnetic field that induces a voltage in the coil 116 through mutual inductance. Similarly, when energized by the semiconductor die 110, the coil 116 generates a fluctuating magnetic field that induces a voltage in the coil 114 through mutual inductance. The semiconductor dies 108, 110 communicate with devices external to the isolation device 100 by means of conductive terminals 104. For example, the isolation device 100 may be coupled to a printed circuit board (PCB) on which one or more other devices are mounted, and the isolation device 100 may communicate with these other devices by means of the conductive terminals 104 and metal traces on the PCB.

[0023] Since the semiconductor dies 108, 110 are respectively positioned on the opposite surfaces 113, 115 of the multi-layer substrate 112, many technical advantages are achieved. First, the positioning of the semiconductor dies 108, 110 respectively facilitates heat dissipation from the coils 114, 116. Second, a minimum or no electric field is generated between the semiconductor dies 108, 110, and thus any adverse effects on the operation of the isolation device 100 caused by such an electric field are alleviated or eliminated. Third, the design challenges associated with connecting coil terminals to dies positioned on the same surface of the substrate are eliminated by positioning the semiconductor dies 108, 110 on the opposite surfaces 113, 115 of the substrate 112. Fourth, since the semiconductor dies 108, 110 are coupled to their respective terminals by metal (e.g., solder) bumps 124, 126 rather than bond wires, the disadvantages introduced by bond wire parasitic effects as described above are alleviated.

[0024] Figure 1B is in accordance with various examples Figure 1A of a top view of the isolation device 100. Figure 1C is in accordance with various examples Figure 1A of a perspective view of the isolation device 100.

[0025] The semiconductor dies 108, 110 can vary in size, position, or both. The positioning of the semiconductor dies 108, 110 on the opposing surfaces 113, 115 of the substrate 112 eliminates any adverse effects that would otherwise result from positioning the semiconductor dies 108, 110 in close proximity to each other, such as the formation of an electric field that would detrimentally affect the operation of the isolation device 100. For example, the semiconductor dies 108, 110 can be centered directly above and below the substrate 112, respectively, as opposed to Figure 1A the configuration where the semiconductor dies 108, 110 are horizontally offset from each other (i.e., not centered directly above and below the substrate 112, respectively). The substrate 112 should be thick enough to form an isolation barrier between the semiconductor dies 108, 110 that can withstand the applied voltage. The thickness of the substrate 112 will vary depending on the material used to implement the isolation barrier and its dielectric strength. The thickness of the substrate 112 will also vary depending on the number of wiring layers implemented in the substrate 112, which can be any suitable number (e.g., 3 - 6 layers). Conversely, the substrate 112 should not be too thick to avoid an unacceptably large increase in the size of the isolation device 100 in terms of both the vertical thickness and the area of the substrate 112, thus enabling suitable coupling between the coils 114, 116. Figure 2A Depicts such semiconductor dies 108, 110 centered directly above and below the substrate 112, respectively. Specifically, aside from the semiconductor dies 108, 110 being larger and centered directly above and below the substrate 112 as shown, Figure 2A the isolation device 100 of Figure 1A is the same as the isolation device 100 of Figure 2B is a top view of the isolation device 100 according to various examples. Additionally, Figure 2A is a perspective view of the isolation device 100 according to various examples. Figure 2C is a perspective view of the isolation device 100 according to various examples. Figure 2A is a perspective view of the isolation device 100 according to various examples.

[0026] Figure 3 is a flowchart of a method 300 for manufacturing an isolation device (e.g., the isolation device 100) according to various examples. Figure 4A1-4F3 is a process flow for manufacturing an isolation device according to various examples. Thus, Figure 3 and 4A1 - 4F3 are now described in parallel.

[0027] The method 300 includes forming a substrate, such as the substrate 112, by an iterative plating (e.g., electroplating) and dielectric film deposition process (302). Figure 4A1Is a contour cross-sectional view of a substrate 112 that has been formed by an iterative process of electroplating and dielectric film deposition. For example, in a first step, a seed layer can be deposited on a metal carrier, and a photolithography process can be used to plate some or all of a first coil (e.g., coil 116) and a first trace (e.g., trace 120) coplanar with the first coil. In a second step, a dielectric film can be deposited (e.g., by lamination) on and around the first coil and the first trace. In a third step, the dielectric film can be ground and electroplated with metal. These steps can be repeated until the first coil and the first trace are fully formed. Subsequently, one or more dielectric films can be deposited, followed by another iterative process in which electroplating, photolithography, and grinding are used to form a second coil (e.g., coil 114) and a second trace (e.g., trace 118) coplanar with the second coil. This iterative process is continued until the second coil and the second trace are fully formed, and enough dielectric film has been deposited to surround and contact the second coil and the second trace (e.g., until a multi-layer substrate 112 of 2A is fully formed). Figure 1A Or a multi-layer substrate 112 of 2A). Figure 4A2 Is according to various examples Figure 4A1 Top view of the structure of Figure 4A3 Is according to various examples Figure 4A1 Perspective view of the structure of

[0028] Method 300 includes coupling a bottom die to the bottom surface of the substrate by solder reflow (304). In addition to adding a semiconductor die 110 coupled to the surface 115 of the substrate 112 by solder bumps 126, Figure 4B1 Is Figure 4A1 Contour cross-sectional view of the structure of. Specifically, the device side 111 of the semiconductor die 110 is coupled to the coil 116 and the metal trace 120 by solder bumps 126, as shown. Figure 4B2 Is according to various examples Figure 4B1 Top view of the structure of Figure 4B3 Is according to various examples Figure 4B1 Perspective view of the structure of

[0029] Method 300 includes coupling the substrate to a lead frame strip by solder reflow, where the bottom semiconductor die faces downward toward the lead frame conductive terminals (306). In addition to Figure 4B1 The structure of has been coupled to the conductive terminals 104 of the lead frame strip, Figure 4C1 Is Figure 4B1 Contour cross-sectional view of the structure of. As shown, the conductive terminal 104 is flat and not curved as in Figure 1A Because the conductive terminal 104 is still coupled to the lead frame strip. Figure 4C2 Is according to various examples Figure 4C1 Top view of the structure of Figure 4C3 Is according to various examplesFigure 4C1 Perspective view of the structure of

[0030] Method 300 includes coupling a top die to the top surface (308) of a substrate by solder reflow. In addition to the semiconductor die 108 already being coupled to the surface 113 of the substrate 112 by solder bumps 124, Figure 4D1 is Figure 4C1 Contour cross-sectional view of the structure of Figure 4D2 is according to various examples of Figure 4D1 Top view of the structure of Figure 4D3 is according to various examples of Figure 4D1 Perspective view of the structure of

[0031] Method 300 includes applying a molding compound to Figure 4D1 the structure (310). In addition to the molding compound 102 already being applied as shown to cover Figure 4D1 the various structures of Figure 4E1 is Figure 4D1 Contour cross-sectional view of the structure of. Any suitable technique can be used to apply the molding compound 102, such as injection molding. Figure 4E2 is according to various examples of Figure 4E1 Top view of the structure of Figure 4E3 is according to various examples of Figure 4E1 Perspective view of the structure of

[0032] Method 300 includes trimming leads from a lead frame and bending the leads (312). In addition to the conductive terminals 104 already being trimmed to separate from the lead frame strip and the conductive terminals 104 subsequently being bent to have a gull-wing (or other suitable) shape, Figure 4F1 is Figure 4E1 Contour cross-sectional view of the structure of Figure 4F2 is according to various examples of Figure 4F1 Top view of the structure of Figure 4F3 is according to various examples of Figure 4F1 Perspective view of the structure of

[0033] The scope of the present disclosure is not limited to the exact manufacturing process flows shown in Figure 4A1-4F3 . For example, a solder paste stencil can be printed onto the substrate 112, and the substrate 112 can be coupled to the top surface of the leads of a lead frame (e.g., by reflowing the solder paste stenciled onto the substrate 112). A semiconductor die (e.g., semiconductor die 110) can be coupled to the bottom surface of the substrate 112 (i.e., the lead-facing surface of the substrate 112). Another semiconductor die (e.g., semiconductor die 108) can be coupled to the top surface of the substrate 112 (i.e., the lead-back surface of the substrate 112). Then, a molding compound can be applied to cover the dies 108, 110, the substrate 112, the leads, and other components of the package.

[0034] As described above, the advantage of coupling semiconductor dies 108, 110 to opposite surfaces 113, 115 of substrate 112 is to increase heat dissipation from coils 114, 116. Effective heat dissipation is particularly valuable in power applications where a large amount of heat is generated (e.g., in isolation device 100). As Figure 1A-1C shown in FIGS. 2A - 2C, positioning semiconductor die 108 directly above coil 114 facilitates heat dissipation from coil 114 and through semiconductor die 108. Similarly, as Figure 1A-1C shown in FIGS. 2A - 2C, positioning semiconductor die 110 directly below coil 116 facilitates heat dissipation from coil 116 and through semiconductor die 110. Figure 5A and 5B are top views of isolation device substrate coils 116 and 114 indicating temperature across the coils according to various examples. As Figure 5A shown, the portion of coil 116 vertically aligned with semiconductor die 110 is cooler than the rest of coil 116 due to heat dissipation from coil 116 and through semiconductor die 110. Similarly, as Figure 5B shown, the portion of coil 114 vertically aligned with semiconductor die 108 is cooler than the rest of coil 114 due to heat dissipation from coil 114 and through semiconductor die 108.

[0035] Figure 6A is a graph 600 depicting the operating behavior of an isolation device according to various examples. Graph 600 includes three sub - graphs. The three sub - graphs share a common x - axis that indicates frequency in gigahertz (GHz). The y - axes of the top two sub - graphs indicate voltage gain in V / V, and the y - axis of the bottom sub - graph indicates impedance in ohms. The number 602 indicates the example channel operating frequency of an example isolation device (e.g., isolation device 100). The third (i.e., bottom - most) sub - graph illustrates the cross - impedance that describes the behavior of the communication channel of an example isolation device acting as a dual - tuned transformer. A differential current is provided to the example isolation device resonating at a given frequency (e.g., as indicated on the x - axis), and the magnitude of the voltage response is determined at the output of the isolation device (e.g., as indicated on the y - axis). Curve 604 indicates the typical performance of a conventional isolation device where the semiconductor die is located on the same surface of the substrate. Figure 6BDepict such a traditional isolation device having a substrate 620, dies 622 and 624 on the same surface of the substrate 620, coils 626 vertically aligned with each other, and a connector 628 connecting the die 624 to one of the coils 626. The connector 628 distorts the capacitive and inductive differential symmetry of the isolation device, resulting in the poor performance shown in graph 600, as described below. Curve 606 indicates the performance of an isolation device according to an example herein (i.e., where semiconductor dies are on opposite surfaces of a multi-layer substrate). Figure 6C Depict such an example isolation device including a substrate 630, dies 632 and 634 on opposite surfaces of the substrate 630, and coils 636 vertically aligned with each other positioned inside the substrate 630. Figure 6C The example isolation device of omits the connector 628 that would otherwise cause the capacitive and inductive differential asymmetry described above, thereby improving performance, as described below. As shown by curves 604 and 606, Figure 6B and 6C the isolation devices of do not have a significant change in behavior in terms of transimpedance.

[0036] The second (i.e., middle) sub-graph illustrates the common-mode voltage transfer function seen across half of the receiving transformer coil (i.e., from one end of the coil to the center tap, and from the opposite end of the coil to the center tap) for the frequency sweep depicted on the x-axis. Curves 608, 610 depict the voltage response of the common-mode voltage of a traditional isolation device (e.g., an isolation device such as Figure 6B ), while curves 612, 613 depict the voltage response of the common-mode voltage of an example isolation device (e.g., isolation device 100 or an isolation device such as Figure 6C ). As shown, curves 608, 610 depict the operational asymmetry present in a traditional isolation device (e.g., an isolation device such as Figure 6B ), as depicted by the inconsistencies near the channel operating frequency 602 and the consistencies present at the remaining frequencies on the x-axis. This asymmetry results in the operational drawbacks described above. In contrast, curves 608, 610 depict the operational symmetry of an example isolation device (e.g., isolation device 100 or an isolation device such as Figure 6C ) over the entire frequency range depicted on the x-axis, including the channel operating frequency 602. This operational symmetry enables mitigation of the technical drawbacks associated with inductive asymmetry as described above.

[0037] The first (i.e., topmost) sub-graph represents the difference between the common-mode voltages (i.e., the voltage across the receiving coil). At the channel operating frequency 602, curve 616 (which depicts the behavior in an example isolation device (e.g., isolation device 100 or an isolation device such as Figure 6C )) has a lower value than curve 614 (which depicts, for example, Figure 6BThe typical behavior of traditional isolation devices in) much lower voltages (e.g., 60 times lower on the logarithmic scale graph 600), thus confirming the symmetry depicted by curves 612, 613 compared to the asymmetry depicted by curves 608, 610. The almost eliminated operational asymmetry in an example isolation device (e.g., isolation device 100) alleviates the above-described challenges associated with inductive asymmetry and further improves the performance of the example isolation device (e.g., isolation device 100) to resist external interference by reducing the common-mode to differential-mode conversion provided by the asymmetry. For example, in a symmetric system, external interference is not reflected in the difference between the common-mode voltages and thus does not affect the operational integrity of the example isolation device (e.g., isolation device 100 or Figure 6C the isolation device).

[0038] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A. Other types of coupling, such as inductive coupling, capacitive coupling, and optical coupling, are also contemplated and included within the scope of the present disclosure.

[0039] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be carried out by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnections of the device, or by a combination thereof.

[0040] The use of the term "ground" and its variants in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "approximately", or "substantially" before a parameter means within + / - 10% of the parameter. Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. An isolation device, comprising: A multi-layer substrate having opposing first and second surfaces, the multi-layer substrate comprising: a first coil in a first layer of the substrate, the first coil having first and second terminals; a second coil in a second layer of the substrate vertically spaced apart from the first layer, the second coil having third and fourth terminals; as well as a dielectric material covering the first and second coils; a first semiconductor die coupled to the first surface and the first and second terminals; a second semiconductor die coupled to the second surface and to the third and fourth terminals, the second semiconductor die being galvanically isolated from the first semiconductor die; a conductive terminal coupled to the multilayer substrate; as well as A molding compound covers the multi-layer substrate, the first and second semiconductor dies, and the conductive terminals.

2. The isolation device of claim 1, wherein the dielectric material comprises a deposited film. The isolation device of claim 1 , wherein the conductive terminal is coupled to the second surface. The isolation device of claim 1 , wherein the conductive terminal is coupled to the first surface. 5 . The isolation device of claim 1 , wherein a vertical line normal to the first and second surfaces extends through both the first and second semiconductor dies. 6 . The isolation device of claim 1 , wherein a vertical line normal to the first and second surfaces does not extend through both the first and second semiconductor dies.

7. The isolation device of claim 1, wherein the first layer is between the first surface and the second layer.

8. The isolation device of claim 1, wherein the second layer is between the second surface and the first layer.

9. The isolation device of claim 1, wherein the dielectric material is a solid dielectric material other than air.

10. The isolation device of claim 1, wherein the first and second coils form a transformer.

11. The isolation device of claim 1, wherein the first and second semiconductor dies are coupled to the first, second, third, and fourth terminals by solder bumps. 12 . The isolation device of claim 1 , wherein device sides of the first and second semiconductor dies, in which circuitry is formed, face the substrate.

13. An isolation device comprising: A multi-layer substrate having opposing first and second surfaces, the multi-layer substrate comprising: a first coil in a first layer of the substrate closer to the first surface than to the second surface, the first coil having first and second terminals; a second coil in a second layer of the substrate closer to the second surface than to the first surface, the second coil having third and fourth terminals; as well as a dielectric material covering the first and second coils; a first semiconductor die coupled to the first and second terminals via a first set of solder bumps; a second semiconductor die coupled to the third and fourth terminals via a second set of solder bumps, the first and second semiconductor dies being separated from each other in a vertical direction by a first distance and in a horizontal direction by a second distance; a conductive terminal coupled to the multilayer substrate; as well as A molding compound covers the multi-layer substrate, the first and second semiconductor dies, and the conductive terminals, wherein the conductive terminals are exposed to the outside of the molding compound. The isolation device of claim 13 , wherein the dielectric material comprises a deposited film.

15. The isolation device of claim 13, wherein the substrate is not a printed circuit board (PCB) and the dielectric material is not air.

16. The isolation device of claim 13, wherein device sides of the first and second semiconductor dies, in which circuitry is formed, face the substrate.

17. A method for manufacturing an isolation device, comprising: coupling a first semiconductor die to a first coil of a multilayer substrate using a first solder bump, the substrate comprising a second coil and a dielectric material covering the first and second coils; coupling the substrate to conductive terminals of a lead frame; coupling a second semiconductor die to the second coil using second solder bumps, the first and second semiconductor dies being coupled to opposing surfaces of the substrate; covering the substrate and the first and second semiconductor dies with a molding compound; as well as The conductive terminals are trimmed to separate the conductive terminals from the lead frame.

18. The method of claim 17, wherein device sides of the first and second semiconductor dies, in which circuitry is formed, face the substrate.

19. The method of claim 17, wherein the power module package has no bond wires.

20. The method of claim 17, wherein the first and second coils form a transformer.

21. The method of claim 17, wherein the dielectric material is a deposited film.

22. The method of claim 21, wherein the dielectric material is not air, and wherein the substrate is not a printed circuit board (PCB).

23. An isolation package comprising: a substrate having first and second coupling members and first and second surfaces, the first and second surfaces being opposite to each other; a first semiconductor die coupled to the first surface and the first coupling member; a second semiconductor die coupled to the second surface and to the second coupling member, the second semiconductor die being galvanically isolated from the first semiconductor die; a conductive terminal coupled to the substrate; as well as A molding compound covers the substrate, the first and second semiconductor dies, and the conductive terminals.

24. The isolation package of claim 23, wherein the first and second coupling members are inductive coupling members.

25. The isolation package of claim 23, wherein the first and second coupling members are capacitive coupling members.

26. The isolation package of claim 23, wherein the first and second coupling members are optical coupling members.

27. The isolation package of claim 23, wherein the conductive terminals are package leads.

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