Power-on protection circuit of low-side power tube, electronic circuit and electronic equipment

Abstract

The invention provides a power-on protection circuit of a low-side power tube, an electronic circuit and electronic equipment, which are used for performing power-on protection on the low-side power tube integrated in a chip, a drain electrode of the low-side power tube is coupled to an external power supply voltage through a load, and a source electrode of the low-side power tube is coupled to a ground end. The electric leakage unit can output electric leakage current according to the electric leakage characteristic of the electric leakage unit and the drain voltage of the low-side power tube. The voltage bias unit generates a first bias voltage according to the leakage current and the feedback current, the first bias voltage acts on the control end of the pull-down transistor to conduct the pull-down transistor to pull down the grid electrode of the low-side power tube, and the current positive feedback unit outputs the feedback current to the output end of the leakage unit according to the first bias voltage. Therefore, the first bias voltage output by the voltage bias unit is more stable than the first bias voltage output by only the leakage current, so that the low-side power tube is stably turned off in the power-on process of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular, to a power-on protection circuit for a low-side power transistor, an electronic circuit, and an electronic device. Background Art

[0002] Chips integrated with a switching power supply and chips integrated with a low-dropout regulator (LDO regulator) are widely used in modern household appliances, automobiles, mobile phones and other electronic products. In many application scenarios, a switching power supply and a low-dropout regulator are also integrated in the same chip. With the development of microelectronic manufacturing technology, in order to improve the integration of the chip, those skilled in the art integrate the power transistors that were originally placed outside the chip in the switching power supply and the low-dropout regulator into the chip. In the chip, the power transistor is used to withstand high voltages and large currents, and is the core of the chip. Once the power transistor conducts wrongly, it will cause the internal part of the chip and the external circuit driven by the chip to withstand large currents, resulting in confusion of the circuit function at the least, and damage to the chip and the external circuit at the most.

[0003] However, during the power-on process of the chip, the low-side power transistor inside the chip is prone to conduct wrongly, resulting in damage to the circuit connected thereto.

[0004] Therefore, providing a solution for protecting the low-side power transistor inside the chip during the power-on process of the chip has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a power-on protection circuit for a low-side power transistor, an electronic circuit, and an electronic device, so as to protect the low-side power transistor inside the chip during the power-on process of the chip.

[0006] The technical solution of the present invention provides a power-on protection circuit for a low-side power transistor, which is used to protect the low-side power transistor integrated inside the chip. The drain of the low-side power transistor is coupled to an external power supply voltage through a load, and the source of the low-side power transistor is coupled to the ground terminal. The power-on protection circuit includes:

[0007] A leakage unit, configured to output a leakage current according to its own leakage characteristics and the drain voltage of the low-side power transistor;

[0008] A voltage biasing unit, configured to generate and output a first bias voltage according to the leakage current and a feedback current;

[0009] A current positive feedback unit, configured to output the feedback current to the output end of the leakage unit according to the first bias voltage;

[0010] A pull-down transistor, whose control terminal is connected to the output terminal of the voltage biasing unit, whose first terminal is connected to the gate of the low-side power transistor, and whose second terminal is coupled to the ground terminal. The pull-down transistor is used to be turned on by the first biasing voltage to turn off the low-side power transistor;

[0011] A turn-off unit, configured to control the pull-down transistor to turn off after the chip is powered on.

[0012] Optionally, the current positive feedback unit includes a first resistor, a first current transistor, a second current transistor, and a third current transistor. The first end of the first resistor is coupled to the ground terminal, the second end of the first resistor is coupled to the second end of the first current transistor, the control terminal of the first current transistor is coupled to the first end of the voltage biasing unit, the first end of the first current transistor is coupled to the first end of the second current transistor, the control terminal of the second current transistor is connected to its own first end, the control terminal of the third current transistor is connected to the control terminal of the second current transistor, the first end of the third current transistor is coupled to the input terminal of the voltage biasing unit, and the second ends of the third current transistor and the second current transistor are both coupled to the drain of the low-side power transistor.

[0013] Optionally, the voltage biasing unit includes a first biasing transistor and a second biasing transistor. The first end of the first biasing transistor serves as the input terminal of the voltage biasing unit and is connected to its own control terminal. The control terminal of the first biasing transistor serves as the output terminal of the voltage biasing unit and is connected to the control terminal of the pull-down transistor. The second end of the first biasing transistor is connected to the first end of the second biasing transistor. The control terminal of the second biasing transistor serves as the first end of the voltage biasing unit and is respectively connected to its own first end and the control terminal of the first current transistor. The second end of the second biasing transistor is coupled to the ground terminal.

[0014] Optionally, the first bias transistor, the second bias transistor, and the first current transistor are all NMOS transistors, the second current transistor and the third current transistor are both PMOS transistors. The first ends of the first bias transistor, the second bias transistor, and the first current transistor are all the drains of the NMOS transistors. The second ends of the first bias transistor, the second bias transistor, and the first current transistor are all the sources of the NMOS transistors. The control ends of the first bias transistor, the second bias transistor, and the first current transistor are all the gates of the NMOS transistors. The first ends of the second current transistor and the third current transistor are both the drains of the PMOS transistors. The second ends of the second current transistor and the third current transistor are both the sources of the PMOS transistors. The control ends of the second current transistor and the third current transistor are both the gates of the PMOS transistors. The aspect ratio of the first current transistor is greater than that of the second bias transistor.

[0015] Optionally, the first bias transistor, the second bias transistor, and the first current transistor are all NPN bipolar junction transistors, the second current transistor and the third current transistor are both PNP bipolar junction transistors. The first ends of the first bias transistor, the second bias transistor, and the first current transistor are all the collectors of the NPN bipolar junction transistors. The second ends of the first bias transistor, the second bias transistor, and the first current transistor are all the emitters of the NPN bipolar junction transistors. The control ends of the first bias transistor, the second bias transistor, and the first current transistor are all the bases of the NPN bipolar junction transistors. The first ends of the second current transistor and the third current transistor are both the collectors of the PNP bipolar junction transistors. The second ends of the second current transistor and the third current transistor are both the emitters of the PNP bipolar junction transistors. The control ends of the second current transistor and the third current transistor are both the bases of the PNP bipolar junction transistors.

[0016] Optionally, the leakage unit includes a leakage diode. The negative electrode of the leakage diode is coupled to the drain of the low-side power transistor, and the positive electrode of the leakage diode is coupled to the input end of the voltage bias unit.

[0017] Optionally, a pull-down resistor is further included. The first end of the pull-down resistor is coupled to the second end of the pull-down transistor, and the second end of the pull-down resistor is connected to the ground terminal.

[0018] Optionally, the turn-off unit includes a turn-off NMOS transistor. The gate of the turn-off NMOS transistor is connected to the chip power-on signal. The source of the turn-off NMOS transistor is coupled to the ground terminal. The drain of the turn-off NMOS transistor is coupled to the input terminal of the voltage biasing unit. The chip power-on signal is at a low level before the chip is powered on, and jumps to a high level after the chip is powered on.

[0019] The technical solution of the present invention further provides an integrated chip, including the power-on protection circuit of the low-side power transistor.

[0020] The technical solution of the present invention further provides an electronic device, including the integrated chip.

[0021] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0022] In the power-on protection circuit of the low-side power transistor provided by the technical solution of the present invention, during the power-on process of the chip, as long as the chip is connected to an external power supply, the drain of the low-side power transistor will be pulled high by the load. And the leakage unit will output a leakage current according to its own leakage characteristics and the drain voltage of the low-side power transistor. The voltage biasing unit generates a first bias voltage according to the leakage current and the feedback current. The first bias voltage acts on the control terminal of the pull-down transistor to turn on the pull-down transistor. Since the first end of the pull-down transistor is connected to the gate of the low-side power transistor and its second end is coupled to the ground terminal, after the pull-down transistor is turned on, the low-side power transistor is turned off because its gate is pulled down to the ground terminal. On this basis, the current positive feedback unit will output the feedback current to the output terminal of the leakage unit according to the first bias voltage, so that the first bias voltage output by the voltage biasing unit is more stable than only the leakage current, thereby stably turning off the low-side power transistor during the power-on process of the chip. Description of the Drawings

[0023] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0024] Figure 1 is a schematic circuit structure diagram of the actual application of a low-side power transistor;

[0025] Figure 2 is a schematic circuit structure of the power-on protection circuit of the low-side power transistor provided by the embodiment of the present invention Figure 1 ;

[0026] Figure 3 is a schematic circuit structure of the power-on protection circuit of the low-side power transistor M0 provided by the embodiment of the present invention Figure 2 ;

[0027] Figure 4Schematic diagram of the power - on protection circuit for the low - side power transistor M0 provided by the embodiments of the present invention Figure 3 ;

[0028] Figure 5 Schematic diagram of the power - on protection circuit for the low - side power transistor M0 provided by the embodiments of the present invention Figure 4 。 Detailed implementation manners

[0029] As described in the background art, during the power - on process of the chip, the low - side power transistor inside the chip is prone to mis - conduction, resulting in damage to the circuit connected thereto. Taking the actual application of a low - side power transistor as an example, the specific reasons for the mis - conduction of the low - side power transistor during the chip power - on process are analyzed in detail below.

[0030] Figure 1 is a schematic diagram of the circuit structure of an actual application of a low - side power transistor.

[0031] Please refer to Figure 1 , this embodiment includes a low - side power transistor, a drive circuit, a load, and an external power supply voltage. The output end of the drive circuit is connected to the gate of the low - side power transistor. The drive circuit is used to output a drive signal to control the conduction and cut - off of the low - side power transistor. The first end of the load is connected to the drain of the low - side power transistor, the second end of the load is connected to the external power supply voltage, and the source of the low - side power transistor is connected to the ground terminal. The drive circuit needs to be powered by the internal power supply of the chip to drive the gate of the low - side power transistor. Since the establishment of the internal power supply of the chip is generated by converting the external power supply voltage, and there is a certain time difference between the establishment of the internal power supply and the establishment of the external power supply voltage, in the initial stage of chip power - on, a situation where the internal power supply has not been established but the external power supply voltage has been established will occur. At this time, the drain of the low - side power transistor will be pulled high by the load and the external power supply voltage, and the gate of the low - side power transistor will also be pulled high by its own drain due to the gate - drain capacitance, resulting in the mis - conduction of the low - side power transistor.

[0032] Therefore, the prior art will set a pull - down resistor between the gate and the source of the low - side power transistor. And to ensure that the low - side power transistor will not be mis - conducted during chip power - on, the resistance value of the pull - down resistor needs to be set very small. However, the problem with this solution is that when the chip is powered on and normally drives the low - side power transistor, the drive circuit needs to provide a very large current to generate enough voltage drop on the pull - down resistor to turn on the low - side power transistor, thus greatly increasing the output power consumption of the drive circuit.

[0033] In view of this, an embodiment of the present invention provides a power - on protection circuit for a low - side power transistor, which is used to perform power - on protection on the low - side power transistor integrated inside a chip. The drain of the low - side power transistor is coupled to an external power supply voltage through a load, and the source of the low - side power transistor is coupled to the ground terminal.

[0034] Figure 2 Schematic diagram of the circuit structure of the power - on protection circuit for the low - side power transistor provided by the embodiment of the present invention Figure 1 。

[0035] Please refer to Figure 2 , the power - on protection circuit for the low - side power transistor provided by the embodiment of the present invention includes:

[0036] Leakage unit 100, which is used to output a leakage current IA according to its own leakage characteristics and the drain D voltage of the low - side power transistor;

[0037] Voltage bias unit 200, which is used to generate and output a first bias voltage V1 according to the leakage current IA and a feedback current IB;

[0038] Current positive - feedback unit 300, which is used to output the feedback current IB to the output terminal of the leakage unit 100 according to the first bias voltage V1;

[0039] Pull - down transistor 400, whose control terminal is connected to the output terminal of the voltage bias unit 200, whose first end is connected to the gate of the low - side power transistor M0, and whose second end is coupled to the ground terminal. The pull - down transistor 400 is used to be turned on by the first bias voltage V1 to turn off the low - side power transistor M0;

[0040] Turn - off unit 500, which is used to control the pull - down transistor 400 to turn off after the chip completes power - on.

[0041] Before the chip completes the establishment of the internal power supply, that is, before power - on, the turn - off unit 500 does not work. Since the drain D of the low - side power transistor will be pulled up by the rapidly established external power supply voltage, the leakage unit 100 outputs a leakage current IA to the voltage bias unit 200 according to its own leakage characteristics. The voltage bias unit 200 generates a first bias voltage V1 according to the leakage current IA and the feedback current IB, and the first bias voltage V1 acts on the control terminal of the pull - down transistor 400 to turn on the pull - down transistor 400. Since the first end of the pull - down transistor 400 is connected to the gate of the low - side power transistor M0 and its second end is coupled to the ground terminal, after the pull - down transistor 400 is turned on, the low - side power transistor M0 is turned off because its gate is pulled down to the ground terminal.

[0042] Since the leakage current IA is easily interfered by environmental factors and is unstable, the first bias voltage V1 becomes unstable. As a result, the first bias voltage V1 cannot stably turn on the pull-down transistor 400, leading to the inability of the pull-down transistor 400 to stably pull down the gate voltage of the low-side power transistor M0, which further affects the power-on protection of the low-side power transistor M0. Therefore, a current positive feedback unit 300 is provided, and the current positive feedback unit 300 outputs a feedback current IB to the voltage bias unit 200 according to the first bias voltage V1. Since the magnitude of the feedback current IB is not affected by the external environment, the leakage current IA can keep the first bias voltage V1 stable after combining with the feedback current IB, thereby stably turning on the pull-down transistor 400.

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0044] As a specific implementation manner, the leakage unit 100 includes a leakage transistor M2. The control terminal and the first terminal of the leakage transistor M2 are both coupled to the drain D of the low-side power transistor, and the second terminal of the leakage transistor M2 is coupled to the input terminal of the voltage bias unit 200.

[0045] The voltage bias unit 200 includes a first bias transistor M3 and a second bias transistor M4. The first terminal of the first bias transistor M3 serves as the input terminal of the voltage bias unit 200 and is connected to its own control terminal. The second terminal of the first bias transistor M3 is connected to the first terminal of the second bias transistor M4. The control terminal of the second bias transistor M4 is connected to its own first terminal, and the second terminal of the second bias transistor M4 is coupled to the ground terminal.

[0046] The current positive feedback unit 300 includes a first resistor R1, a first current transistor M5, a second current transistor M6, and a third current transistor M7. A first end of the first resistor R1 is coupled to the ground terminal, a second end of the first resistor R1 is coupled to a second end of the first current transistor M5, a control terminal of the first current transistor M5 is coupled to a control terminal of the second bias transistor M4, a first end of the first current transistor M5 is coupled to a first end of the second current transistor M6, a control terminal of the second current transistor M6 is connected to its own first end, a control terminal of the third current transistor M7 is connected to the control terminal of the second current transistor M6, a first end of the third current transistor M7 is coupled to a first end of the first bias transistor M3, a second end of the third current transistor M7 and a second end of the second current transistor M6 are both coupled to a drain D of the low-side power transistor, and a width-to-length ratio of the first current transistor M5 is greater than a width-to-length ratio of the second bias transistor M4.

[0047] The turn-off unit 500 includes a turn-off NMOS transistor. A gate of the turn-off NMOS transistor receives a power-on signal of the chip, a source of the turn-off NMOS transistor is coupled to the ground terminal, a drain of the turn-off NMOS transistor is coupled to an input terminal of the voltage bias unit 200, the power-on signal of the chip is at a low level before the chip is powered on, and the power-on signal of the chip jumps to a high level after the chip is powered on.

[0048] The following Figure 3 describes the working principle of the power-on protection circuit for the low-side power transistor:

[0049] Figure 3 is a schematic circuit structure of the power-on protection circuit for the low-side power transistor M0 provided by the embodiment of the present invention Figure 2 .

[0050] Please refer to Figure 3 , as a specific embodiment, the leakage transistor M2 includes a PMOS transistor. A gate and a source of the PMOS transistor are both coupled to a drain D of the low-side power transistor, and a drain of the PMOS transistor is coupled to an input terminal of the voltage bias unit 200.

[0051] The pull - down transistor 400, the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 are all NMOS transistors. The first ends of the pull - down transistor 400, the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 all serve as the drains of the NMOS transistors. The second ends of the pull - down transistor 400, the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 all serve as the sources of the NMOS transistors. The control ends of the pull - down transistor 400, the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 all serve as the gates of the NMOS transistors.

[0052] The second current transistor M6 and the third current transistor M7 are both PMOS transistors. The first ends of the second current transistor M6 and the third current transistor M7 both serve as the drains of the PMOS transistors. The second ends of the second current transistor M6 and the third current transistor M7 both serve as the sources of the PMOS transistors. The control ends of the second current transistor M6 and the third current transistor M7 both serve as the gates of the PMOS transistors.

[0053] When the external power supply voltage is established and the internal power supply of the chip is not established, the drain D of the low - side power transistor is pulled high by the external power supply voltage. Due to the leakage characteristic of the leakage transistor M2 itself, a leakage current IA is output to the first bias transistor M3 and the second bias transistor M4. The first bias transistor M3 and the second bias transistor M4 are sequentially turned on by the leakage current IA. After the first bias transistor M3 and the second bias transistor M4 are sequentially turned on, the gate voltage of the first bias transistor M3, that is, the formula for the first bias voltage V1 is as follows:

[0054] V1 = VGS_MN1 + VGS_MN2 Formula (1)

[0055] Where, V1 is used to represent the first bias voltage V1, VGS_MN1 is used to represent the gate - source voltage of the first bias transistor M3, and VGS_MN2 is used to represent the gate - source voltage of the second bias transistor M4.

[0056] Since the gate of the first bias transistor M3 is connected to the gate of the pull - down transistor 400, the first bias voltage V1 acts on the gate of the pull - down transistor 400 to turn on the pull - down transistor 400.

[0057] When the second bias transistor M4 is turned on, the first current transistor M5 is turned on. At this time, the current formula flowing through the first resistor R1 is as follows:

[0058] I1 = (VGS_MN2 - VGS_MN3) / R0 Formula (2)

[0059] Where, I1 is used to represent the current flowing through the first resistor R1, VGS_MN3 is used to represent the gate-source voltage of the first current transistor M5, and R0 is used to represent the resistance value of the first resistor R1.

[0060] It should be noted that in order for the current flowing through the first resistor R1 to be generated, the aspect ratio of the first current transistor M5 needs to be set to be greater than the aspect ratio of the second bias transistor M4.

[0061] The current flowing through the first resistor R1 flows through the second current transistor M6, and the current mirror formed by the second current transistor M6 and the third current transistor M7 transforms it into the feedback current IB. The feedback current IB is output from the drain of the third current transistor M7 to the drain of the first bias transistor M3.

[0062] Since the feedback current IB is proportional to the current flowing through the first resistor R1, and according to Formula (2), by setting the resistance value of the first resistor R1, the aspect ratio of the second bias transistor M4, and the aspect ratio of the first current transistor M5, the magnitude of the current flowing through the first resistor R1 can be adjusted, thereby adjusting the magnitude of the feedback current IB.

[0063] It should be added that in addition to being set as PMOS transistors, the leakage transistor M2, the second current transistor M6, and the third current transistor M7 can also be set as PNP triodes. The first ends of the leakage transistor M2, the second current transistor M6, and the third current transistor M7 are all the collectors of the PNP triodes. The second ends of the leakage transistor M2, the second current transistor M6, and the third current transistor M7 are all the emitters of the PNP triodes. The control ends of the leakage transistor M2, the second current transistor M6, and the third current transistor M7 are all the bases of the PNP triodes. Of course, the specific devices of the leakage transistor M2, the second current transistor M6, and the third current transistor M7 can be selected according to requirements and are not limited here.

[0064] In addition to being configured as NMOS transistors, the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 can also be configured as NPN bipolar transistors. The first ends of the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 are all the collectors of the NPN bipolar transistors. The second ends of the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 are all the emitters of the NPN bipolar transistors. The control ends of the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 are all the bases of the NPN bipolar transistors. Of course, the specific devices of the first bias transistor M3, the second bias transistor M4, and the first current transistor M5 can be selected according to requirements and are not limited herein.

[0065] After the external power supply voltage is established and the internal power supply of the chip is also established, the power-on signal at the gate of the turn-off NMOS transistor jumps from low level to high level, and the turn-off NMOS transistor is turned on to pull down the gate voltage of the first bias transistor M3 to the ground terminal. The pull-down transistor 400 is turned off, thereby stopping the pull-down of the gate of the low-side power transistor M0. The first bias transistor M3 and the second bias transistor M4 are both turned off. Therefore, no current flows through the first resistor R1, so the feedback current IB is zero.

[0066] Figure 4 Schematic diagram of the circuit structure of the power-on protection circuit for the low-side power transistor M0 provided by the embodiment of the present invention Figure 3 。

[0067] Please refer to Figure 4 , in another embodiment, the power-on protection circuit further includes a pull-down resistor R2. The first end of the pull-down resistor R2 is coupled to the second end of the pull-down transistor 400, and the second end of the pull-down resistor R2 is connected to the ground terminal. After the pull-down transistor 400 is turned on, the current formula for the current flowing through the pull-down resistor R2 is as follows:

[0068] I2 = (VGS_MN2 + VGS_MN1 - VGS_MN4) / R1 Formula (3)

[0069] wherein, I2 is used to represent the current flowing through the pull-down resistor R2, and VGS_MN4 is used to represent the gate-source voltage of the pull-down transistor 400.

[0070] If the width-to-length ratios of the pull-down transistor 400 and the first bias transistor M3 are set to be the same, the magnitude of the current flowing through the pull-down resistor R2 can be adjusted by adjusting the width-to-length ratio of the second bias transistor M4 and the magnitude of the pull-down resistor R2.

[0071] The purpose of setting the pull-down resistor R2 is to limit the gate pull-down current of the low-side power transistor M0, which is beneficial to the layout connection of the actual circuit.

[0072] Since the other circuit structures and operating principles are the same as those of the Figure 3 illustrated embodiment, they will not be elaborated here.

[0073] Figure 5 FIG. is a schematic circuit structure diagram of the power-on protection circuit for the low-side power transistor M0 provided by the embodiment of the present invention Figure 4 .

[0074] Please refer to Figure 5 , in another embodiment, the leakage transistor M2 is replaced by a leakage diode. The negative electrode of the leakage diode is coupled to the drain D of the low-side power transistor, and the positive electrode of the leakage diode is coupled to the input terminal of the voltage bias unit 200. In this embodiment, the leakage current IA is output by using the reverse leakage characteristic after the leakage diode is broken down. The first bias transistor M3 and the second bias transistor M4 are respectively replaced by a first bias diode and a second bias diode. The positive electrode of the first bias diode serves as the input terminal of the voltage bias unit 200. The negative electrode of the first bias diode is connected to the positive electrode of the second bias diode, so the negative electrode of the second bias diode is connected to the ground terminal. The first bias voltage V1 is equal to the sum of the conduction voltages of the first bias transistor M3 and the second bias transistor M4. Since the other circuit structures and operating principles are the same as those of the Figure 4 illustrated embodiment, they will not be elaborated here.

[0075] In summary, in the power-on protection circuit of the low-side power transistor provided by the embodiment of the present invention, during the power-on process of the chip, as long as the chip is connected to an external power supply, the drain of the low-side power transistor will be pulled up by the load. And the leakage unit will output a leakage current according to its own leakage characteristics and the drain voltage of the low-side power transistor. The voltage biasing unit generates a first bias voltage according to the leakage current and the feedback current, and the first bias voltage acts on the control terminal of the pull-down transistor to turn on the pull-down transistor. Since the first end of the pull-down transistor is connected to the gate of the low-side power transistor and its second end is coupled to the ground terminal, after the pull-down transistor is turned on, the low-side power transistor is turned off because its gate is pulled down to the ground terminal. On this basis, the current positive feedback unit outputs the feedback current to the output terminal of the leakage unit according to the first bias voltage, so that the first bias voltage output by the voltage biasing unit is more stable than when there is only the leakage current, thereby stably turning off the low-side power transistor during the power-on process of the chip.

[0076] An embodiment of the present invention further provides an integrated chip, including the power-on protection circuit of the low-side power transistor.

[0077] An embodiment of the present invention further provides an electronic device, including the integrated chip.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power-on protection circuit for a low-side power tube, characterized in that: The power-on protection circuit is used to protect the low-side power tube integrated in the chip, wherein the drain of the low-side power tube is coupled to the external power supply voltage through the load, and the source of the low-side power tube is coupled to the ground terminal. The power-on protection circuit includes: A leakage unit, used for outputting leakage current according to its own leakage characteristics and the drain voltage of the low-side power tube; A voltage bias unit, used to generate and output a first bias voltage according to the leakage current and the feedback current; a current positive feedback unit, configured to output the feedback current to an output terminal of the leakage unit according to the first bias voltage; A pull-down transistor, whose control end is connected to the output end of the voltage bias unit, whose first end is connected to the gate of the low-side power tube, and whose second end is coupled to the ground end, wherein the pull-down transistor is used to be turned on by the first bias voltage to turn off the low-side power tube; A shut-down unit is used to control the pull-down transistor to shut down after the chip is powered on.

2. The power-on protection circuit of the low-side power tube according to claim 1, characterized in that: The current positive feedback unit includes a first resistor, a first current transistor, a second current transistor, and a third current transistor. The first end of the first resistor is coupled to the ground end, the second end of the first resistor is coupled to the second end of the first current transistor, the control end of the first current transistor is coupled to the first end of the voltage bias unit, the first end of the first current transistor is coupled to the first end of the second current transistor, the control end of the second current transistor is connected to its own first end, the control end of the third current transistor is connected to the control end of the second current transistor, the first end of the third current transistor is coupled to the input end of the voltage bias unit, and the second end of the third current transistor and the second end of the second current transistor are both coupled to the drain of the low-side power tube.

3. The power-on protection circuit of the low-side power tube according to claim 2, characterized in that: The voltage bias unit includes a first bias transistor and a second bias transistor, wherein the first end of the first bias transistor is connected to its own control end as the input end of the voltage bias unit, the control end of the first bias transistor is connected to the control end of the pull-down transistor as the output end of the voltage bias unit, the second end of the first bias transistor is connected to the first end of the second bias transistor, the control end of the second bias transistor is connected to its own first end and the control end of the first current transistor as the first end of the voltage bias unit, and the second end of the second bias transistor is coupled to the ground end.

4. The power-on protection circuit of the low-side power tube according to claim 3, characterized in that: The first bias transistor, the second bias transistor and the first current transistor are all NMOS transistors, the second current transistor and the third current transistor are all PMOS transistors, the first end of the first bias transistor, the first end of the second bias transistor and the first current transistor are all drains of the NMOS transistor, the second end of the first bias transistor, the second end of the second bias transistor and the second end of the first current transistor are all sources of the NMOS transistor, the control end of the first bias transistor, the control end of the second bias transistor and the control end of the first current transistor are all gates of the NMOS transistor, the first end of the second current transistor and the first end of the third current transistor are all drains of the PMOS transistor, the second end of the second current transistor and the second end of the third current transistor are all sources of the PMOS transistor, the control end of the second current transistor and the control end of the third current transistor are all gates of the PMOS transistor, and the width-to-length ratio of the first current transistor is greater than the width-to-length ratio of the second bias transistor.

5. The power-on protection circuit of the low-side power tube according to claim 3, characterized in that: The first bias transistor, the second bias transistor and the first current transistor are all NPN transistors, the second current transistor and the third current transistor are all PNP transistors, the first end of the first bias transistor, the first end of the second bias transistor and the first end of the first current transistor are all collectors of the NPN transistor, the second end of the first bias transistor, the second end of the second bias transistor and the second end of the first current transistor are all emitters of the NPN transistor, the control end of the first bias transistor, the control end of the second bias transistor and the control end of the first current transistor are all bases of the NPN transistor, the first end of the second current transistor and the first end of the third current transistor are all collectors of the PNP transistor, the second end of the second current transistor and the second end of the third current transistor are all emitters of the PNP transistor, and the control end of the second current transistor and the control end of the third current transistor are all bases of the PNP transistor.

6. The power-on protection circuit of the low-side power tube according to claim 1, characterized in that: The leakage unit includes a leakage diode, a cathode of the leakage diode is coupled to the drain of the low-side power tube, and an anode of the leakage diode is coupled to the input end of the voltage bias unit.

7. The power-on protection circuit of the low-side power tube according to claim 1, characterized in that: A pull-down resistor is also included, wherein a first end of the pull-down resistor is coupled to the second end of the pull-down transistor, and a second end of the pull-down resistor is connected to a ground end.

8. The power-on protection circuit of the low-side power tube according to claim 1, characterized in that: The shutdown unit includes a shutdown NMOS tube, the gate of the shutdown NMOS tube is connected to the on-chip power signal, the source of the shutdown NMOS tube is coupled to the ground terminal, the drain of the shutdown NMOS tube is coupled to the input terminal of the voltage bias unit, the on-chip power signal is at a low level before the chip is powered on, and the on-chip power signal jumps to a high level after the chip is powered on.

9. An integrated chip, characterized in that: A power-on protection circuit for a low-side power tube comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the integrated chip as claimed in claim 9.

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