Through silicon via filling method based on atomic layer deposition process and through silicon via

Abstract

The invention provides a through-silicon-via filling method based on an atomic layer deposition process and a through-silicon-via, belongs to the technical field of semiconductors, and aims to improve the metal filling rate of the through-silicon-via, and the method comprises the steps: S1, carrying out the etching of a first surface of a substrate, and obtaining a to-be-filled blind hole; s2, directly depositing a seed layer on the blind hole by adopting an atomic layer deposition process; s3, depositing a metal layer on the seed layer; s4, depositing a seed layer on the metal layer; and S5, repeatedly executing the steps S3 and S4 until the blind hole is completely filled to obtain the through silicon via.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a method for filling through-silicon vias and through-silicon vias based on an atomic layer deposition process. Background Art

[0002] As the integrated circuit manufacturing process continues to approach the physical limit, traditional planar interconnection technologies are increasingly unable to meet the requirements of high-density, high-bandwidth, and low-power chip designs. Nanoscale through-silicon vias (TSVs), through the innovation of vertical interconnection architectures, have laid the foundation for the large-scale application of three-dimensional integrated chips. Obtaining a nanoscale TSV structure with perfect metal filling is a key link to ensure that its technical advantages are transformed into actual performance. The quality of metal filling directly determines the electrical characteristics, mechanical stability, and long-term reliability of TSV interconnections. A perfect filling process needs to ensure that the metal material is uniformly deposited without defects and voids in the nanoscale holes, thereby avoiding sharp increases in resistivity, thermal stress concentration, or interface delamination failure caused by discontinuous microstructures.

[0003] However, traditional metal filling methods are difficult to achieve uniform and complete metal filling during the metal filling process of nanoscale TSVs. Summary of the Invention

[0004] This application provides a method for filling through-silicon vias and through-silicon vias based on an atomic layer deposition process to improve the metal filling rate of through-silicon vias.

[0005] In the first aspect of the embodiments of this application, a method for filling through-silicon vias based on an atomic layer deposition process is provided. The method includes: S1. Etch the first surface of the substrate to obtain a blind hole to be filled; S2. Use the atomic layer deposition process to deposit a seed layer into the blind hole; S3. Deposit a metal layer on the seed layer; S4. Deposit a seed layer on the metal layer; S5. Repeat steps S3 and S4 until the blind hole is completely filled to obtain a through-silicon via.

[0006] In a possible implementation manner, etching the first surface of the substrate to obtain a blind hole to be filled includes: Based on a first parameter and a second parameter, etch the first surface of the substrate to obtain the blind hole. The first parameter represents the width of the blind hole, the second parameter represents the depth of the blind hole, and the ratio of the second parameter to the first parameter is greater than 10.

[0007] In a possible implementation manner, the first parameter is greater than or equal to 50 nm and less than or equal to 1000 nm.

[0008] In a possible implementation, depositing a seed layer into the blind via includes: Using a first material to deposit a seed layer into the blind via, where the first material is titanium nitride or ruthenium.

[0009] In a possible implementation, depositing a seed layer into the blind via includes: Based on a third parameter, depositing a seed layer into the blind via, where the third parameter represents the thickness of the seed layer, and the third parameter is greater than or equal to 5 nm and less than or equal to 10 nm.

[0010] In a possible implementation, depositing a metal layer on the seed layer includes: Using a second metal material to deposit a metal layer on the seed layer, where the second metal material is copper.

[0011] In a possible implementation, depositing a metal layer on the seed layer includes: Based on a fourth parameter, depositing a metal layer on the seed layer, where the fourth parameter represents the thickness of the metal layer, and the fourth parameter is greater than or equal to 20 nm and less than or equal to 50 nm.

[0012] In a possible implementation, after the blind via is completely filled, the method further includes: Removing the excess metal material on the first surface of the substrate.

[0013] A second aspect of the embodiments of the present application further provides a through-silicon via structure, which is prepared by the through-silicon via filling method described in the first aspect of the embodiments of the present application; The through-silicon via structure includes a plurality of stacked metal-filled layers, and each metal-filled layer includes: a seed layer and a metal layer stacked in sequence.

[0014] In a possible implementation, the ratio of the depth to the width of the through-silicon via is greater than 10.

[0015] The present application provides a through-silicon via filling method based on an atomic layer deposition process. The method includes: etching on the first surface of a substrate to obtain a blind via to be filled; using the atomic layer deposition process to deposit a seed layer into the blind via and deposit a metal layer on the seed layer; repeating the above step until the blind via is completely filled to obtain a through-silicon via.

[0016] The beneficial effects of the present application are as follows: In the embodiment of the present application, by adopting the atomic layer deposition process, a seed layer is first deposited on the side wall and bottom of the blind hole, and then a metal layer with a certain thickness is deposited on the seed layer (so as to avoid grain agglomeration and reduce the porosity in the metal layer). By repeating this step, the seed layer-metal layer-seed layer-metal layer (such as Ru-Cu-Ru-Cu) is alternately deposited to completely fill the blind hole and obtain a through-silicon via, thereby improving the metal filling rate.

[0017] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the following specifically gives the specific implementation manners of the present application. Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings. It should be noted that the ratios in the drawings are only for illustration and do not represent the actual ratios.

[0019] Figure 1 It is a flowchart of the steps of a method for filling a through-silicon via based on the atomic layer deposition process in the embodiment of the present application; Figure 2 It is a schematic structural diagram of a blind hole in the embodiment of the present application; Figure 3 It is a scanning electron microscope image of the deposition state of a through-silicon via in the embodiment of the present application; Figure 4 It is a schematic structural diagram of a seed layer in the embodiment of the present application; Figure 5 It is a schematic structural diagram of a metal layer in the embodiment of the present application; Figure 6 It is a schematic structural diagram of a through-silicon via in the embodiment of the present application; Brief Description of the Drawings: Substrate 100, Blind Hole 101, Seed Layer 102, Metal Layer 103. Detailed Description of the Embodiments

[0020] To make the above objects, features, and advantages of the present application more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0021] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same category, and the number of objects is not limited. For example, the first object can be one or at least two. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0022] Nano TSV technology provides a revolutionary path for the semiconductor industry to break through physical bottlenecks, achieve multi-dimensional integration, and upgrade functions. As the integrated circuit manufacturing process continues to approach the physical limit, traditional planar interconnect technologies are increasingly unable to meet the requirements of high-density, high-bandwidth, and low-power chip designs. Nano-scale through-silicon vias (TSVs), through the innovation of vertical interconnect architectures, lay the foundation for the large-scale application of three-dimensional integrated chips. By directly constructing via structures with micron- to nano-scale sizes in silicon-based materials, nano TSVs can tightly stack different functional chips or devices vertically, significantly shortening the signal transmission distance, thus remarkably reducing interconnect delay and power consumption while increasing the data transmission rate. This technology not only solves the signal integrity problems caused by long-distance wiring in traditional wire bonding or flip-chip technologies but also provides a physical carrier for heterogeneous integration, enabling modules with different process nodes, such as logic chips, memory cells, sensors, and optoelectronic devices, to cooperate efficiently, providing hardware support for frontier fields such as artificial intelligence, high-performance computing, and the Internet of Things. In addition, nano TSV technology improves the heat dissipation efficiency under high-density integration by optimizing the thermal management path. Its combination with advanced packaging technologies (such as fan-out packaging and wafer-level packaging) further promotes the miniaturization and multi-functionality of chip systems. Against the backdrop of continuous iteration of semiconductor materials, the compatibility advantages of nano TSVs are particularly prominent. They can be adapted to various substrate materials such as silicon, silicon carbide, and gallium nitride and can be combined with new interconnect metals such as copper, cobalt, and graphene, leaving room for the diverse development of future chip architectures. From the perspective of the industrial chain, the maturity of nano TSVs will accelerate the commercialization process of three-dimensional integrated chips, reconstruct the collaboration models of chip design, manufacturing, and packaging and testing, and is of profound significance for breaking through systematic bottlenecks such as the "memory wall" and "power wall" and building an independent and controllable high-end chip ecosystem.

[0023] Obtaining a metal-filled perfect nano-TSV structure is a key link to ensure the transformation of its technical advantages into actual performance. The quality of metal filling directly determines the electrical characteristics, mechanical stability, and long-term reliability of TSV interconnections. A perfect filling process needs to ensure that the metal material is uniformly deposited without defects and voids in the nano-scale holes, thus avoiding sharp increases in resistivity, thermal stress concentration, or interface delamination failure caused by discontinuous microstructures. By precisely controlling the deposition kinetics and interface reactions, highly complete metal filling can significantly improve the current-carrying capacity of TSV conductors, reduce Ohmic losses and skin effects during signal transmission, which is particularly important for high-frequency and high-current application scenarios. In terms of mechanical properties, dense metal filling can effectively buffer the difference in thermal expansion coefficients between the silicon substrate and the interconnect material, inhibit the propagation of microcracks generated under temperature cycling or mechanical shock, thereby improving the anti-fatigue characteristics and packaging reliability of the three-dimensional integrated structure. In addition, the elimination of interface defects can also reduce carrier scattering and improve the phase consistency of high-frequency signal transmission, which is crucial for fields such as 5G communication and millimeter-wave radar that have strict requirements for signal integrity. From the perspective of manufacturing processes, the perfection of metal filling directly affects the yield of key processes such as subsequent chemical mechanical polishing and redistribution layer preparation. A filling surface with high flatness can reduce metal residues or hole exposure caused by over-polishing, providing process tolerance for the precise alignment of multi-layer stacked structures. In extreme working environments, such as high temperature, high humidity, or high radiation conditions, a defect-free metal-filled structure can extend the service life of the device by suppressing electromigration phenomena and corrosion reactions, meeting the high-standard application requirements of aerospace, automotive electronics, etc. Generally speaking, the breakthrough of the metal filling process not only enables the nano-TSV technology to truly have the ability to be engineered and implemented, but also provides underlying support for the comprehensive improvement of three-dimensional integrated chips in terms of computing power density, energy efficiency ratio, environmental adaptability, etc. by optimizing the electro-thermal-mechanical multi-physical field coupling performance, becoming the core driving force to promote the evolution of advanced packaging technology to higher dimensions.

[0024] Currently, the metal filling methods for sub-micron TSV structures can be divided into several categories, such as electroplating, magnetron sputtering, evaporation, and ALD. However, these metal filling methods are all difficult to achieve uniform and complete metal filling during the metal filling process of nano-scale TSVs.

[0025] As the mainstream technology for traditional TSV metal filling, the electroplating process faces the risk of failure under the combined action of multiple physics and chemistry when dealing with submicron high aspect ratio structures. The core contradiction stems from the dynamic imbalance of ion transport, electric field distribution, and interfacial reactions during the electrochemical deposition process. At submicron pore diameters, a nearly closed microenvironment is formed inside the deep holes, significantly weakening the concentration gradient of metal ions (such as copper ions) inside and outside the pores in the electrolyte, resulting in insufficient diffusion driving force. At the same time, there are significant differences in the electric field distribution at the pore mouth and the bottom during electroplating: due to the concentration of electric field lines in the pore mouth area, a higher current density is generated, and metal ions are preferentially reduced and deposited here, forming a rapidly thickening metal layer at the top. This "top-accelerated deposition" phenomenon rapidly reduces the pore mouth size, further hindering the penetration of the electrolyte to the bottom of the deep hole, and finally forming unfilled voids or slit structures at the bottom of the hole due to the interruption of ion supply. In addition, the diffusion kinetics and adsorption behavior of electroplating additives (such as inhibitors, accelerators, and leveling agents) are distorted in deep holes: due to the size effect, additive molecules are difficult to enter the deep holes synchronously, resulting in a mismatch in the chemical environment of the deposition surfaces at the pore mouth and the bottom. For example, excessive adsorption of inhibitors at the pore mouth will overly inhibit the deposition rate in this area, while dendrite growth or rough surfaces may occur at the bottom of the hole due to insufficient inhibitor concentration, exacerbating interfacial defects. The out-of-control of metal crystal orientation during the deposition process further magnifies the problem - fine grains or amorphous structures are formed at the bottom of the deep hole due to mass transfer limitations, while columnar grains tend to form in the pore mouth area. This gradient difference in the microstructure is prone to grain boundary slip or crack propagation under subsequent thermal cycling or mechanical loading, resulting in electromigration failure or mechanical fracture. Even more complex is that the residual stress (such as tensile stress or compressive stress) accompanying metal deposition in the electroplating process continues to accumulate in high aspect ratio structures due to limited stress release paths, which may directly lead to the interfacial peeling between the TSV sidewall and the metal or the overall warping deformation of the through hole.

[0026] Physical vapor deposition (PVD) technology has been attempted for TSV metal filling due to its ability to prepare high-purity thin films. However, there is a fundamental conflict between its line-of-sight deposition characteristics and the geometric constraints of submicron high aspect ratio structures. During the PVD process, metal atoms or ions are sputtered from the target surface to the substrate along an approximately straight-line trajectory. This deposition method highly depends on the directionality and aspect ratio of the pore for the coverage ability inside deep holes. When the pore diameter is reduced to submicron and the aspect ratio exceeds 10:1, the collision probability of sputtered particles with the pore wall increases sharply after entering the pore. Most metal atoms lose kinetic energy due to multiple scattering near the pore opening, and only a few particles can reach the bottom region of the pore. This deposition non-uniformity forms a metal accumulation with a thickness much greater than that at the bottom at the pore edge, namely the "overhang" structure. It not only blocks the path for subsequent metal to enter the deep hole but also causes interfacial shear stress due to the difference in thermal expansion coefficients between the overhang and the substrate material during subsequent high-temperature processes, resulting in film delamination or pore wall cracking. In addition, the insufficient step coverage ability of the PVD thin film leads to an exponential decay of the metal deposition thickness on the sidewall of the deep hole from the pore opening to the bottom, significantly reducing the continuity and compactness of the sidewall metal layer and forming a longitudinally penetrating microcrack or pore network. Such structural defects will become electron scattering centers during high current density operation, greatly increasing the resistivity and local Joule heat, and at the same time providing a diffusion channel for moisture or corrosive media, accelerating device failure. From the perspective of process control, the contradiction between the PVD deposition rate and the deep hole filling requirement is difficult to reconcile: increasing the sputtering power can increase the metal flux, but it will exacerbate the bombardment damage of high-energy particles on the pore wall, inducing interface amorphization or an increase in the density of defect states; reducing the power results in too low a deposition rate to meet the mass production requirement. More severely, the PVD process is difficult to achieve conformal coverage of the bottom and sidewalls of deep holes, and the interfacial bonding strength between the metal thin film and the silicon substrate continuously weakens with increasing depth, and is prone to local peeling during subsequent chemical mechanical polishing or thermal annealing processes, forming interface voids or metal residues. These limitations make the PVD technology only an auxiliary process in high aspect ratio TSV metal filling and unable to independently complete the high-quality filling task.

[0027] Although the atomic layer deposition (ALD) technology is known for its nanoscale conformality, the problems of out-of-control grain size and increasing porosity that are difficult to avoid during the metal filling process seriously restrict the electrical and mechanical properties of high-aspect-ratio TSV structures. The low-temperature layer-by-layer deposition characteristics of ALD lead to inherent defects in the crystallization process of metal thin films: in the initial stage of deposition, the surface self-limiting reaction of metal precursors and reaction gases tends to form an initial layer with an amorphous or nanocrystalline structure, and as the number of deposition cycles increases, the thermodynamically driven grain coalescence phenomenon gradually appears. Since the ALD process usually uses a relatively low deposition temperature to maintain the reactivity of precursors and the compatibility with the substrate, the migration ability of metal atoms at the deposition interface is limited, and the grain boundaries cannot be optimized by in-situ annealing, ultimately forming large grains with a discrete size distribution. This non-uniform grain structure will induce microcracks due to grain boundary slip or stress concentration at twin interfaces under subsequent thermal cycles or current loads. Especially at the interface between the TSV sidewall and the metal, the mismatch in the thermal expansion coefficients of large grains and the silicon substrate will exacerbate the risk of interface delamination. Even more seriously, the randomness of the grain orientation of ALD metal thin films is relatively high, and there is a lack of means to control the oriented texture, resulting in a significant increase in the probability of grain boundary scattering in the electron transport path, significantly increasing the resistivity and weakening the high-frequency signal integrity.

[0028] In view of the above problems, the present application provides a method for filling through-silicon vias and a through-silicon via based on the atomic layer deposition process. By using the atomic layer deposition process, a seed layer is first deposited on the sidewalls and bottom of the blind via, and then a metal layer with a certain thickness is deposited on the seed layer (thereby avoiding grain agglomeration and reducing the porosity in the metal layer). By repeating this step, the seed layer-metal layer-seed layer-metal layer (such as Ru-Cu-Ru-Cu) is alternately deposited to completely fill the blind via, obtaining a through-silicon via to improve the metal filling rate.

[0029] In the first aspect of the present application, a method for filling through-silicon vias based on the atomic layer deposition process ALD is proposed. Referring to Figure 1 , Figure 1 shows a flowchart of the steps of a method for filling through-silicon vias based on the atomic layer deposition process. As shown in Figure 1 ,the method includes: Step S1, etching is performed on the first surface of the substrate to obtain a blind via to be filled.

[0030] Specifically, the substrate used in step S1 can be a bare silicon wafer or a transfer board, or a silicon wafer or a transfer board prefabricated with other structures (such as metal interconnection structures, chips, insulating layers, etc.). The position where the through-silicon vias need to be prepared is determined on the first surface of the substrate. The upper and lower surfaces of the substrate are determined as the first surface and the second surface, and the surface to be processed is determined as the first surface.

[0031] Referring to Figure 2 ,Figure 2 A schematic structural diagram of a blind via is shown. As Figure 2 shown, on the first surface of the substrate 100 (such as Figure 2 the first surface shown is the upper surface of the substrate), a blind via 101 to be filled is prepared by etching. Further, in step S1, etching is performed in a direction perpendicular to the first surface to obtain a blind via with a certain depth. As Figure 2 shown, the extending direction of the sidewall of the blind via is perpendicular to the first surface, so that the intersection position of the sidewall of the blind via and the first surface is a sharp angle (the angle is 90 degrees).

[0032] In a possible implementation manner, etching is performed on the first surface of the substrate to obtain a blind via to be filled, including: Based on a first parameter and a second parameter, etching is performed on the first surface of the substrate to obtain the blind via. The first parameter represents the width of the blind via, the second parameter represents the depth of the blind via, and the ratio of the second parameter to the first parameter is greater than 10.

[0033] In order to fabricate a through-silicon via with a high aspect ratio, the aspect ratio of the fabricated blind via can be controlled by setting the first parameter and the second parameter. The ratio of the second parameter to the first parameter being greater than 10 means that the ratio of the depth to the width of the fabricated blind via (depth: width) is greater than 10. Specifically, for a through-silicon via with a high aspect ratio, problems such as out-of-control grain size and increasing porosity are more likely to occur during the metal filling process. If PVD is used to fill the blind via, when the aperture shrinks to sub-microns and the aspect ratio exceeds 10:1, the collision probability of sputtered particles with the pore wall increases sharply after entering the pore channel. Most metal atoms lose kinetic energy due to multiple scattering near the pore mouth, and only a few particles can reach the bottom region of the pore, resulting in poor filling effect. Using the electroplating process will cause the residual stress (such as tensile stress or compressive stress) associated with metal deposition to continuously accumulate in the high-aspect-ratio structure due to limited stress release paths, which may directly cause the interface peeling between the sidewall of the TSV and the metal or the overall warping deformation of the via. This application proposes to use the atomic layer deposition process to fabricate a through-silicon via with a high aspect ratio, and by first depositing a seed layer on the sidewall and bottom of the blind via, and then depositing a metal layer with a certain thickness on the seed layer (thereby avoiding grain agglomeration and reducing the porosity in the metal layer), and by repeating this step, alternately depositing to form a seed layer-metal layer-seed layer-metal layer (such as Ru-Cu-Ru-Cu) to completely fill the blind via and obtain a through-silicon via to improve the metal filling rate.

[0034] In a possible implementation manner, the first parameter is greater than or equal to 50 nm and less than or equal to 1000 nm.

[0035] Among them, in order to fabricate through-silicon vias (TSVs) at the sub-micron level, the diameter of the blind holes needs to be controlled to be less than or equal to 1 micron. Specifically, the width of the blind holes is within 50 nm to 1000 nm. Exemplarily, the width of the blind holes can be 50 nm, 200 nm, 500 nm, or 1000 nm. By controlling the width of the blind holes (setting the first parameter), through-silicon vias at the sub-micron level are fabricated.

[0036] Step S2: Using atomic layer deposition technology, deposit a seed layer into the blind holes; Step S3: Deposit a metal layer on the seed layer.

[0037] Specifically, referring to Figure 3 , Figure 3 shows a scanning electron microscope image of the deposition state of a through-silicon via. As shown in Figure 3 , if a metal material is directly used to fill the blind holes, at the initial stage of deposition, the surface self-limiting reaction between the metal precursor and the reaction gas tends to form an initial layer with an amorphous or nanocrystalline structure (such as the relatively dense initial layer formed on the sidewalls of the blind holes in Figure 3 ). As the number of deposition cycles increases, the phenomenon of grain coalescence driven by thermodynamics gradually appears. Since the ALD process usually uses a relatively low deposition temperature to maintain the reaction activity of the precursor and the compatibility with the substrate, the migration ability of metal atoms at the deposition interface is limited, and the grain boundaries cannot be optimized by in-situ annealing, ultimately forming large grains with a discrete size distribution (such as the grain agglomeration phenomenon with a large porosity in the middle position of the blind holes shown in Figure 3 ).

[0038] To solve the above problems, the present application proposes to deposit a seed layer in advance, so as to pre-form a regular, dense, and smooth crystal valley structure layer on the surface (the sidewalls and bottom of the blind holes) by using the seed layer, enhancing the adhesion force between the electrolyte and the metal and promoting the surface uniformity of the deposit. Depositing a metal layer on the seed layer makes the metal layer more evenly distributed, inhibits the occurrence of grain agglomeration in the metal layer, and thus improves the metal filling rate.

[0039] In a possible implementation manner, depositing a seed layer into the blind holes includes: Using a first material, deposit a seed layer into the blind holes, and the first material is titanium nitride or ruthenium.

[0040] In this embodiment, the first material used for the seed layer can be titanium nitride or ruthenium (Ru).

[0041] In a possible implementation manner, depositing a seed layer into the blind holes includes: Based on a third parameter, deposit a seed layer into the blind holes, and the third parameter represents the thickness of the seed layer, and the third parameter is greater than or equal to 5 nm and less than or equal to 10 nm.

[0042] Refer to Figure 4 , Figure 4 which shows a schematic structural diagram of a seed layer. As Figure 4 shown, a layer of seed layer 102 is first deposited in the blind hole. In this embodiment, the thickness of the seed layer is greater than or equal to 5 nm and less than or equal to 10 nm. Exemplarily, the thickness of the seed layer can be 5 nm, 7 nm, or 10 nm. The material used for the seed layer (such as ruthenium Ru) has a high cost, so the thickness of the seed layer should not be too thick (less than or equal to 10 nm) to avoid excessive cost; and the thickness of the seed layer should not be too thin (greater than or equal to 5 nm), as being too thin will affect the deposition effect of the metal layer and cannot achieve the purpose of reducing the porosity.

[0043] In a possible implementation manner, depositing a metal layer on the seed layer includes: Using a second metal material to deposit a metal layer on the seed layer, and the second metal material is copper.

[0044] In this embodiment, the material used for the metal layer (the second metal material) can be copper. When using ruthenium as the seed layer and copper as the metal layer, the cooperation of the two materials can achieve a good deposition effect.

[0045] In a possible implementation manner, depositing a metal layer on the seed layer includes: Based on a fourth parameter, depositing a metal layer on the seed layer, where the fourth parameter represents the thickness of the metal layer, and the fourth parameter is greater than or equal to 20 nm and less than or equal to 50 nm.

[0046] Refer to Figure 5 , Figure 5 which shows a schematic structural diagram of a metal layer. As Figure 5 shown, a layer of metal layer 103 is deposited on the seed layer 102. In this embodiment, the thickness of the metal layer is greater than or equal to 20 nm and less than or equal to 50 nm. Exemplarily, the thickness of the metal layer can be 20 nm, 37 nm, or 50 nm. The thickness of the metal layer should not be too thick (less than or equal to 50 nm) to avoid affecting the deposition effect of the metal layer. After the thickness of the metal layer exceeds a certain threshold, grain agglomeration will gradually occur, resulting in an increase in porosity; and the thickness of the metal layer should not be too thin (greater than or equal to 20 nm), as being too thin will cause the need to deposit the seed layer frequently and use too much seed layer material, increasing the process cost.

[0047] Step S4, depositing a seed layer on the metal layer; Step S5, repeating the above Step S3 and S4 until the blind hole is completely filled to obtain a through-silicon via.

[0048] Specifically, referring to Figure 6 , Figure 6 which shows a schematic structural diagram of a through-silicon via. As Figure 6 shown, after depositing a metal layer with a certain thickness, a seed layer is continuously deposited on the surface of the metal layer, and then a metal layer is deposited in the seed layer. This deposition step is repeatedly executed until the blind via is completely filled, obtaining a filling structure with alternating layers of the seed layer and the metal layer, that is, obtaining a through-silicon via. Among them, the thickness of each deposited seed layer is greater than or equal to 5 nm and less than or equal to 10 nm, and the thickness of each deposited metal layer is greater than or equal to 20 nm and less than or equal to 50 nm. In addition, the substrate can also be thinned from the second surface until the metal material at the bottom of the through-silicon via is exposed.

[0049] In a possible implementation manner, after the blind via is completely filled, the method further includes: removing the excess metal material on the first surface of the substrate.

[0050] Specifically, during the process of filling the blind via by using the atomic layer deposition process, there will be some excess materials (the first material and the second metal material) remaining on the first surface. Therefore, after filling the blind via, it is necessary to remove the excess materials on the first surface of the substrate.

[0051] To improve the metal filling rate, the embodiments of the present application propose to repeatedly execute steps S3 and S4 to achieve the alternating deposition of the seed layer - metal layer - seed layer - metal layer (such as Ru - Cu - Ru - Cu), thereby avoiding grain agglomeration in the metal layer, reducing the porosity in the metal layer, completely filling the blind via, obtaining a through-silicon via, and improving the metal filling rate.

[0052] The second aspect of the embodiments of the present application further provides a through-silicon via structure, which is prepared by the through-silicon via filling method described in the first aspect of the embodiments of the present application. The through-silicon via structure is as Figure 6 shown, the through-silicon via structure includes a plurality of stacked metal filling layers, and each metal filling layer includes: a seed layer and a metal layer stacked in sequence.

[0053] In a possible implementation manner, the ratio between the depth and the width of the through-silicon via is greater than 10.

[0054] In a possible implementation manner, the width of the through-silicon via is within 50 nm to 1000 nm.

[0055] In a possible implementation manner, the thickness of each seed layer is greater than or equal to 5 nm and less than or equal to 10 nm.

[0056] In a possible implementation, the thickness of each of the metal layers is greater than or equal to 20 nm and less than or equal to 50 nm.

[0057] In a possible implementation, the first material used for the seed layer is titanium nitride or ruthenium.

[0058] In a possible implementation, the second metal material used for the metal layer is copper.

[0059] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0060] Finally, it should also be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, commodity or device comprising the element.

[0061] The above provides a detailed introduction to a method for filling through-silicon vias and through-silicon vias based on atomic layer deposition technology. Specific examples are used in this text to elaborate on the principle and implementation of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

[0062] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application aims to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0063] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

[0064] As used herein, the terms "one embodiment", "an embodiment", or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. In addition, it should be noted that the examples of the phrase "in one embodiment" herein do not necessarily all refer to the same embodiment.

[0065] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0066] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for filling through - silicon vias based on atomic layer deposition process, characterized in that, The method includes: S1. Etch on the first surface of the substrate to obtain blind vias to be filled; S2. Use atomic layer deposition process to directly deposit a seed layer into the blind vias; S3. Deposit a metal layer on the seed layer; S4. Deposit a seed layer on the metal layer; S5. Repeat steps S3 and S4 until the blind vias are completely filled to obtain through-silicon vias.

2. The method for filling a through-silicon via according to claim 1, wherein Etching on the first surface of the substrate to obtain blind vias to be filled includes: Based on a first parameter and a second parameter, etch on the first surface of the substrate to obtain the blind vias, where the first parameter represents the width of the blind vias, the second parameter represents the depth of the blind vias, and the ratio of the second parameter to the first parameter is greater than 10.

3. The method for filling a through-silicon via according to claim 2, wherein, The first parameter is greater than or equal to 50 nm and less than or equal to 1000 nm.

4. The method for filling a through-silicon via according to claim 1, wherein Directly depositing a seed layer into the blind vias includes: Use a first material to deposit a seed layer into the blind vias, and the first material is titanium nitride or ruthenium.

5. The method for filling a through-silicon via according to claim 1, wherein Directly depositing a seed layer into the blind vias includes: Based on a third parameter, deposit a seed layer into the blind vias, where the third parameter represents the thickness of the seed layer, and the third parameter is greater than or equal to 5 nm and less than or equal to 10 nm.

6. The method for filling a through-silicon via according to claim 1, wherein Depositing a metal layer on the seed layer includes: Use a second metal material to deposit a metal layer on the seed layer, and the second metal material is copper.

7. The method for filling a through-silicon via according to claim 1, wherein Depositing a metal layer on the seed layer includes: Based on a fourth parameter, deposit a metal layer on the seed layer, where the fourth parameter represents the thickness of the metal layer, and the fourth parameter is greater than or equal to 20 nm and less than or equal to 50 nm.

8. The method for filling a through-silicon via according to claim 1, wherein After the blind vias are completely filled, the method further includes: Remove the excess metal material on the first surface of the substrate.

9. A through-silicon via structure, characterized in that, The through-silicon via structure is prepared by the through-silicon via filling method according to any one of claims 1-8; The through-silicon via structure includes a plurality of stacked metal-filled layers, and each metal-filled layer includes: a seed layer and a metal layer stacked in sequence.

10. The through-silicon via structure according to claim 9, wherein The ratio of the depth to the width of the through-silicon via is greater than 10.

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