Liquid cooling packaging structure of power chip
Through the design of the central coolant distribution layer and micro-nanoflow channel, the thermal resistance problem introduced by multi-layer materials in the power chip packaging structure is solved, and high-efficiency heat dissipation and high-integration power chip packaging is achieved.
Patent Information
- Application Number
- CN202510408547.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-07-01
AI Technical Summary
The existing power chip package structures have additional thermal resistance introduced by multiple layers of materials between the chip and the radiator, resulting in the inability to achieve efficient near-junction heat dissipation.
The design of a central coolant distribution layer and micro-nanoflow channel is adopted. The coolant directly contacts the heating area of the power chip through the substrate and circulates through the micro-nanoflow channel to reduce the introduction of excess material.
It significantly reduces thermal resistance, improves heat dissipation efficiency, enhances the reliability and stability of the packaging structure, and improves the power density per unit volume.
Smart Images
Figure CN120237105A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of high-efficiency heat dissipation packaging of power chips, and relates to a liquid-cooled packaging structure for power chips. Background Art
[0002] With the growth of power demand, power transformation and distribution equipment is gradually developing towards miniaturization, high capacity, and high efficiency. The increase in integration and power makes the equipment face severe thermal challenges. Although the development of technologies such as heat pipes and vapor chambers has significantly reduced the thermal resistance of system-level heat dissipation, the chip-level thermal resistance is still the key factor restricting the temperature of the equipment.
[0003] The existing power chip packaging structures mainly reduce the thermal resistance by using solder layers or thermal interface materials with high thermal conductivity and liquid-cooled plates, etc. However, these methods can only optimize the heat conduction path in a small range and do not fundamentally solve the problem of additional thermal resistance introduced by multiple layers of materials between the chip and the radiator. In addition, although the traditional liquid-cooled plate improves the heat transfer efficiency, there are still multiple layers of heat conduction paths between the liquid-cooled plate and the chip heating area, resulting in the inability to achieve efficient near-junction heat dissipation. Summary of the Invention
[0004] Aiming at the deficiencies of the prior art, the present application provides a liquid-cooled packaging structure for power chips, which realizes efficient heat dissipation while achieving high-integration packaging of the chips.
[0005] To achieve the above object, in a first aspect, the present invention provides a liquid-cooled packaging structure for power chips, including a coolant distribution layer, at least two power chips, and a circuit board;
[0006] The two power chips are in a stacked structure, and the coolant distribution layer is arranged between the two power chips; each power chip is respectively connected to the coolant distribution layer through its own chip substrate, and the other side of each power chip relative to the chip substrate is connected to the circuit board;
[0007] Each chip substrate is etched with micro-nano channels, and the flow channel inlet of the micro-nano channels is connected to the inlet of the coolant distribution layer, and the flow channel outlet of the micro-nano channels is connected to the outlet of the coolant distribution layer;
[0008] The coolant in the coolant distribution layer sequentially passes through the inlet, the flow channel inlet into the micro-nano channels, and sequentially passes through the flow channel outlet and the outlet to return to the coolant distribution layer.
[0009] Compared with the prior art, the embodiments of the present application have the following beneficial effects: By introducing a central coolant distribution layer and micro-nano channels, the complexity in the traditional multi-layer substrate design is reduced; the coolant contacts the heat-generating area of the power chip through the substrate, without introducing extra materials, significantly reducing the thermal resistance and improving the heat dissipation efficiency; the power chips are encapsulated together in a stacked structure, and compared with the planar arrangement, more chips can be integrated within the same volume, significantly increasing the power density per unit volume.
[0010] In some embodiments of the first aspect of the present application, the chip substrate is provided with a plurality of through holes at positions corresponding to the heat-generating areas of the power chips, and the through holes are connected to the micro-nano channels, so that the coolant can directly contact the back of the power chips.
[0011] Compared with the prior art, the above embodiments have the following beneficial effects: Through the through-hole design, the coolant can directly contact the back of the power chip, minimizing the thermal resistance to provide efficient local cooling.
[0012] In some embodiments of the first aspect of the present application, a sealing ring or sealing material is provided around the through holes.
[0013] Compared with the prior art, the above embodiments have the following beneficial effects: The sealing ring or sealing material ensures that the coolant only flows through the designated path, prevents leakage, and improves the reliability and stability of the packaging structure.
[0014] In some embodiments of the first aspect of the present application, the coolant distribution layer includes a plurality of independent inflow ports and outflow ports, and the cross-sectional shapes of the inflow ports and outflow ports are circular.
[0015] Compared with the prior art, the above embodiments have the following beneficial effects: The design of the circular cross-sectional inflow ports and outflow ports can minimize the fluid resistance, ensure the smooth circulation of the coolant, and improve the heat dissipation efficiency.
[0016] In some embodiments of the first aspect of the present application, each of the power chips forms a symmetric stacked structure or an asymmetric stacked structure along the coolant distribution layer.
[0017] Compared with the prior art, the above embodiments have the following beneficial effects: Supporting symmetric and asymmetric stacked mounting structures provides greater design flexibility to meet different application requirements and technical requirements.
[0018] In some embodiments of the first aspect of the present application, the circuit board is provided with a bump array for flip-chip bonding process, and the power chip is electrically connected to the circuit board through the bump array.
[0019] Compared with the prior art, the above embodiments have the following beneficial effects: The flip-chip bonding process combined with the bump array realizes high-density electrical interconnection, shortens the signal transmission path, and reduces the influence of parasitic inductance and capacitance.
[0020] In some embodiments of the first aspect of the present application, the power chip is electrically connected to the circuit board through the bump array, and power chips can be extendedly installed on the circuit board along the length direction of the coolant distribution layer.
[0021] Compared with the prior art, the above embodiments have the following beneficial effects: Electrical connection is achieved through the bump array, allowing other power chips to be extendedly installed on the circuit board, enhancing the flexibility and scalability of the package structure.
[0022] In some embodiments of the first aspect of the present application, the micro-nano channels are parallel micro-nano channels, serpentine micro-nano channels or cylindrical micro-nano channels.
[0023] Compared with the prior art, the above embodiments have the following beneficial effects: Different types of micro-nano channels such as parallel, serpentine or cylindrical are provided, and the channel layout can be adjusted according to specific application requirements to achieve the best cooling effect.
[0024] In some embodiments of the first aspect of the present application, the coolant distribution layer is prepared by using a ceramic plate.
[0025] Compared with the prior art, the above embodiments have the following beneficial effects: The ceramic plate has high thermal conductivity and excellent insulation performance, is suitable for high-temperature and high-power application scenarios, and further improves the heat dissipation capacity and electrical safety of the system.
[0026] In some embodiments of the first aspect of the present application, the coolant distribution layer can also be prepared by using a PCB board.
[0027] Compared with the prior art, the above embodiments have the following beneficial effects: The PCB board has good electrical performance and mechanical strength, and can enhance the stability of the structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 : Schematic diagram of a liquid-cooled package structure of a power chip provided in some embodiments of the present invention.
[0029] Figure 2 : Liquid-cooled package structure diagram of a power chip provided in some embodiments of the present invention.
[0030] In the figure: 1. Coolant distribution layer; 12. Outflow port; 13. Inflow port; 2. Power chip; 21. Chip substrate; 213. Micro-nano channel; 211. Channel inlet; 212. Channel outlet; 214. Through hole; 22. Bump array; 3. Circuit board. Detailed implementation mode
[0031] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0032] Embodiment 1:
[0033] Please refer to Figure 1 , a liquid-cooled packaging structure of a power chip provided by an embodiment of the present invention, including: a coolant distribution layer 1, at least two power chips 2 and a circuit board 3;
[0034] The two power chips 2 are in a stacked structure, and the coolant distribution layer 1 is arranged between the two power chips 2; each power chip 2 is respectively connected to the coolant distribution layer 1 through its own chip substrate 21, and the other side of each power chip 2 relative to the chip substrate 21 is connected to the circuit board 3;
[0035] Each chip substrate 21 is etched with a micro-nano channel 213, and the channel inlet 211 of the micro-nano channel 213 is connected to the inflow port 13 of the coolant distribution layer 1, and the channel outlet 212 of the micro-nano channel 213 is connected to the outflow port 12 of the coolant distribution layer 1;
[0036] The coolant in the coolant distribution layer 1 sequentially passes through the inflow port 13, the channel inlet 211 and enters the micro-nano channel 213, and sequentially passes through the channel outlet 212 and the outflow port 12 and returns to the coolant distribution layer 1.
[0037] In specific implementation, the coolant enters the chip substrate through the inflow port of the coolant distribution layer and the channel inlet of the micro-nano channel, absorbs the heat generated by the power chip at a short distance in the micro-nano channel, and returns to the coolant distribution layer through the channel outlet of the micro-nano channel and the outflow port of the coolant distribution layer, realizing the close-range liquid-cooling heat dissipation of the power chip without introducing more heat dissipation materials (such as heat dissipation plates).
[0038] In addition, as an extension, in specific implementation, such as Figure 2The liquid-cooling packaging structure diagram of a power chip shown, multiple through-holes 214 can also be provided at the position of the chip substrate 21 corresponding to the heat-generating area of the power chip 2, and the through-holes 214 are connected to the micro-nano channels 213, so that the coolant can directly contact the back of the power chip 2, and a sealing ring or sealing material is provided around the through-holes 214.
[0039] In this embodiment, through the through-hole design, the coolant can directly contact the back of the power chip, minimizing the thermal resistance and providing efficient local cooling; the sealing ring or sealing material ensures that the coolant only flows through the specified path, preventing leakage and improving the reliability and stability of the packaging structure.
[0040] Preferably, the coolant distribution layer 1 includes a plurality of independent inflow ports 13 and outflow ports 12, and the cross-sectional shapes of the inflow ports 13 and the outflow ports 12 are circular.
[0041] In this preferred embodiment, the design of the circular cross-sectional inflow and outflow ports can minimize the fluid resistance, ensure the smooth circulation of the coolant, and improve the heat dissipation efficiency. In addition, the circular cross-section can better disperse the stress, reduce the risk of potential crack propagation, and improve the safety of the overall structure.
[0042] Furthermore, each of the power chips 2 forms a symmetric stacked structure or an asymmetric stacked structure along the coolant distribution layer 1.
[0043] In specific implementation, the stacked structure can effectively improve the packaging integration degree per unit volume compared with the planar arrangement; in this application, the support for symmetric and asymmetric stacked installation structures provides greater design flexibility to meet different application requirements and technical requirements.
[0044] Furthermore, a bump array 22 for flip-chip bonding process is provided on the circuit board 3, and the power chip 2 is electrically connected to the circuit board 3 through the bump array 22.
[0045] In specific implementation, the flip-chip bonding process combined with the bump array realizes high-density electrical interconnection, which can shorten the signal transmission path and reduce the influence of parasitic inductance and capacitance.
[0046] Preferably, the power chip 2 is electrically connected to the circuit board 3 through the bump array 22, and power chips can be extendedly installed on the circuit board 3 along the length direction of the coolant distribution layer 1.
[0047] In this preferred embodiment, the chips can not only be installed on both sides in the length direction of the coolant distribution layer, but also other chips are allowed to be further extendedly installed on the circuit board along the length direction of the coolant distribution layer, enhancing the flexibility and scalability of the packaging structure.
[0048] Further, the micro-nano channel 213 is a parallel micro-nano channel, a serpentine micro-nano channel or a cylindrical micro-nano channel.
[0049] In this preferred embodiment, the channel layout can be adjusted according to the actual requirements of specific applications, and parallel, serpentine, cylindrical or other different types of micro-nano channels can be selected to achieve the best cooling effect.
[0050] Further, the coolant distribution layer 1 is prepared by using a ceramic plate or a PCB board.
[0051] In specific implementation, the above two materials can also be combined to prepare the coolant distribution layer.
[0052] In this preferred embodiment, the ceramic plate has high thermal conductivity and excellent insulation performance, which is suitable for high-temperature and high-power application scenarios, further improving the heat dissipation capacity and electrical safety of the system; the PCB board has good electrical performance and mechanical strength, which can enhance the structural stability.
[0053] In summary, compared with the prior art, the embodiments of the present application have the following beneficial effects: by introducing the central coolant distribution layer and the micro-nano channel, the complexity in the traditional multi-layer substrate design is reduced; the coolant contacts the heat generation area of the power chip through the substrate, without introducing redundant materials, significantly reducing the thermal resistance and improving the heat dissipation efficiency; the power chips are packaged together in a stacked structure, which can integrate more chips in the same volume compared with the planar arrangement, significantly increasing the power density per unit volume.
[0054] The specific implementation manners described above further elaborate on the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above are only the specific implementation manners of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A liquid cooling packaging structure for a power chip, characterized in that: include: a coolant distribution layer, at least two power chips, and a circuit board; The two power chips are in a stacked structure, and the coolant distribution layer is arranged between the two power chips; each power chip is connected to the coolant distribution layer through its own chip substrate, and the other side of each power chip relative to the chip substrate is connected to the circuit board; Each chip substrate is etched with a micro-nano flow channel, and the flow channel inlet of the micro-nano flow channel is connected to the flow inlet of the coolant distribution layer, and the flow channel outlet of the micro-nano flow channel is connected to the flow outlet of the coolant distribution layer; The coolant in the coolant distribution layer sequentially passes through the inlet and the flow channel inlet into the micro-nano flow channel, and sequentially passes through the flow channel outlet and the outlet to return to the coolant distribution layer.
2. A liquid cooling packaging structure for a power chip as claimed in claim 1, characterized in that: The chip substrate is provided with a plurality of through holes at positions corresponding to the heating area of the power chip, and the through holes are connected to the micro-nano flow channels, so that the coolant can directly contact the back side of the power chip.
3. A liquid cooling packaging structure for a power chip as claimed in claim 2, characterized in that: A sealing ring or sealing material is arranged around the through hole.
4. A liquid cooling packaging structure for a power chip as claimed in claim 3, characterized in that: The coolant distribution layer comprises a plurality of independent inlets and outlets, and the cross-sectional shapes of the inlets and outlets are circular.
5. The liquid cooling packaging structure of a power chip as claimed in claim 4, characterized in that: The power chips form a symmetrical stacking structure or an asymmetrical stacking structure along the cooling liquid distribution layer.
6. The liquid cooling packaging structure of a power chip as claimed in claim 5, characterized in that: The circuit board is provided with a bump array for flip-chip soldering process, and the power chip is electrically connected to the circuit board through the bump array.
7. A liquid cooling packaging structure for a power chip as claimed in claim 6, characterized in that: The power chip is electrically connected to the circuit board through the bump array, and the power chip can be extendedly mounted on the circuit board along the length direction of the coolant distribution layer.
8. The liquid cooling packaging structure of a power chip as claimed in claim 7, characterized in that: The micro-nano flow channel is a parallel micro-nano flow channel, a serpentine micro-nano flow channel or a cylindrical micro-nano flow channel.
9. A liquid cooling packaging structure for a power chip according to any one of claims 1 to 8, characterized in that: The coolant distribution layer is prepared by using a ceramic plate.
10. A liquid cooling packaging structure for a power chip according to any one of claims 1 to 8, characterized in that: The cooling liquid distribution layer can also be prepared by using a PCB board.