Semiconductor memory device, method for controlling semiconductor memory device, and method for manufacturing semiconductor memory device

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body and a columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device, a control method of a semiconductor memory device, and a manufacturing method of a semiconductor memory device. Background Art

[0002] A semiconductor memory device is known that includes a laminate formed by alternately laminating a conductive layer and an insulating layer, and a columnar body penetrating the laminate. Summary of the Invention

[0003] One embodiment provides a semiconductor memory device, a control method of a semiconductor memory device, and a manufacturing method of a semiconductor memory device that can achieve an improvement in electrical characteristics. The semiconductor memory device according to one embodiment includes a laminate and a columnar body. The laminate includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are alternately laminated layer by layer in a first direction. The columnar body extends in the laminate in the first direction and includes a memory film and a channel layer. The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer. The second gate electrode layer is disposed on a first side in the first direction with respect to the first gate electrode layer and is adjacent to the first gate electrode layer among the plurality of gate electrode layers. The plurality of insulating layers include a first insulating layer adjacent to the first gate electrode layer from a second side in the first direction, and a second insulating layer located between the first gate electrode layer and the second gate electrode layer. The second side is opposite to the first side. When observing in a cross-section along the first direction and a second direction orthogonal to the first direction, a first distance is defined as the distance between a first edge of the first gate electrode layer adjacent to the columnar body at a first boundary along the second direction between the first gate electrode layer and the first insulating layer and a second edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the first edge. A second distance is defined as the distance between a third edge of the first gate electrode layer adjacent to the columnar body at a second boundary along the second direction between the first gate electrode layer and the second insulating layer and a fourth edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the third edge. A third distance is defined as the distance between a fifth edge of the second gate electrode layer adjacent to the columnar body at a third boundary along the second direction between the second gate electrode layer and the second insulating layer and a sixth edge of the second gate electrode layer adjacent to the columnar body from a side opposite to the fifth edge. In this case, the second distance is greater than the first distance and greater than the third distance. Brief Description of the Drawings

[0004] Figure 1It is a block diagram showing a part of the configuration of the semiconductor memory device according to the first embodiment. Figure 2 It is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. Figure 3 It is a cross-sectional view showing a part of the semiconductor memory device according to the first embodiment. Figure 4 It is Figure 3 A cross-sectional view showing an enlarged view of the region surrounded by the F4 line of the semiconductor memory device shown. Figure 5 It is Figure 4 A cross-sectional view of the semiconductor memory device shown along the F5-F5 line. Figure 6 It is Figure 4 A cross-sectional view showing an enlarged view of the region surrounded by the F6 line of the semiconductor memory device shown. Figure 7 It is Figure 6 A cross-sectional view of the semiconductor memory device shown along the F7-F7 line. Figure 8 It is Figure 6 A cross-sectional view of the semiconductor memory device shown along the F8-F8 line. Figure 9 It is Figure 3 A cross-sectional view of the semiconductor memory device shown along the F9-F9 line. Figure 10 It is Figure 9 A cross-sectional view showing an enlarged view of the region surrounded by the F10 line of the semiconductor memory device shown. Figure 11 It is a diagram showing the sequence of the write operation of the semiconductor memory device according to the first embodiment. Figure 12 It is a diagram schematically showing the memory column according to the first embodiment. Figure 13 It is a timing diagram for explaining the write operation according to the first embodiment. Figure 14A It is a cross-sectional view for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 14B It is a cross-sectional view for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 15 It is a cross-sectional view for explaining the operation of the semiconductor memory device according to the first embodiment. Figure 16 It is a cross-sectional view showing the semiconductor memory device according to the second embodiment. Figure 17 This is a cross-sectional view showing the semiconductor memory device according to the third embodiment. Figure 18 This is a cross-sectional view showing the semiconductor memory device according to the fourth embodiment. Figure 19 This is a cross-sectional view showing the semiconductor memory device according to the fifth embodiment. Detailed Embodiments

[0005] Hereinafter, with reference to the drawings, a semiconductor memory device, a control method of the semiconductor memory device, and a manufacturing method of the semiconductor memory device according to the embodiments will be described. In the following description, components having the same or similar functions are given the same reference numerals. Also, redundant descriptions of these components may be omitted. In the following description, reference numerals with a distinguishing number or letter at the end may omit the number or letter at the end when they can be distinguished from each other.

[0006] In the present application, the terms are defined as follows. "Parallel", "orthogonal", or "identical" may respectively include cases of "substantially parallel", "substantially orthogonal", or "substantially identical". "Connection" is not limited to mechanical connection and may include electrical connection. That is, the so-called "connection" is not limited to the case where multiple elements are directly connected and may include the case where multiple elements are connected with other elements intervening therebetween. The so-called "next to" and "adjacent" are not limited to the case of being in contact and may include the case of being arranged with other elements intervening therebetween.

[0007] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the word line WL described later extends (refer to Figure 3 ). The -X direction is the opposite direction of the +X direction. When the +X direction and -X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction intersecting (e.g., orthogonal) with the X direction. The +Y direction is the direction in which the bit line BL extends (refer to Figure 3 ). The -Y direction is the opposite direction of the +Y direction. When the +Y direction and -Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction orthogonal to the X direction and the Y direction. The +Z direction is the direction from the laminate 30 described later toward the bit line BL (refer to Figure 3 ). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and -Z direction are not distinguished, they are simply referred to as the Z direction. In the following description, the position in the Z direction is sometimes referred to as "height". The Z direction is an example of the "first direction". The X direction is an example of the "second direction". In the drawings described below, the illustration of components irrelevant to the description may sometimes be omitted.

[0008] (First Embodiment) <1. Configuration of Semiconductor Memory Device> Figure 1 It is a block diagram showing a part of the configuration of the semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device and can be used as the storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 11 includes a plurality of blocks BLKO to BLK(k - 1) (k is an integer of 1 or more). A plurality of memory cell transistors are provided in the block BLK. The block BLK is used, for example, as an erasure unit of data. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 11. Each memory cell transistor is associated with one bit line and one word line.

[0010] The command register 12 holds the command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds the address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used for the selection of the block BLK, word line, and bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a write operation, a read operation, an erase operation, etc. of data based on the command CMD held in the command register 12.

[0011] The driver module 15 includes a voltage generation circuit. The voltage generation circuit generates the voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line. In the write operation, the sense amplifier module 17 applies a desired voltage to each bit line. In the read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage or current of each bit line, and transmits the determination result as the read data DAT to the host device.

[0012] <2. Electrical Configuration of Memory Cell Array> Figure 2 It is a diagram showing an equivalent circuit of a part of the memory cell array 11. Figure 2 One block BLK included in the memory cell array 11 is shown. The block BLK includes a plurality of (for example, 4) strings STR0 to STR3.

[0013] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MT7, one or more dummy memory cell transistors MTD, one or more drain side select transistors STD, and one or more source side select transistors STS. Additionally, in Figure 2 for the sake of convenience in explanation, only eight memory cell transistors MT0 to MT7 are shown for each NAND string NS. However, each NAND string NS may also include more memory cell transistors MT.

[0014] In each NAND string NS, the memory cell transistors MT0 to MT7 are electrically connected in series. Each memory cell transistor MT includes a control gate and a charge storage portion. The control gate of the memory cell transistor MT is electrically connected to one of the word lines WL0 to WL7. Each memory cell transistor MT stores charge in the charge storage portion according to the voltage applied to the control gate via the word line WL, and non-volatilely holds data.

[0015] In the present embodiment, each block BLK includes a first sub-block BLKSA and a second sub-block BLKSB. Each sub-block BLKS is a unit capable of erasing data independently of other sub-blocks BLKS included in the same block BLK.

[0016] In Figure 2 the example shown, the first sub-block BLKSA includes sub-strings STRA0 to STRA3. The sub-string STRA0 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR0. The sub-string STRA1 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR1. The sub-string STRA2 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR2. The sub-string STRA3 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR3. Additionally, in Figure 2 for the sake of convenience in explanation, only four memory cell transistors MT0 to MT3 are shown for each sub-string STRA. However, each sub-string STRA may also include more memory cell transistors MT.

[0017] Similarly, the second sub-block BLKSB contains sub-strings STRB0 to STRB3. Sub-string STRB0 contains the memory cell transistors MT4 to MT7 of each NAND string NS in string STR0. Sub-string STRB1 contains the memory cell transistors MT4 to MT7 of each NAND string NS in string STR1. Sub-string STRB2 contains the memory cell transistors MT4 to MT7 of each NAND string NS in string STR2. Sub-string STRB3 contains the memory cell transistors MT4 to MT7 of each NAND string NS in string STR3. Additionally, in Figure 2 for ease of explanation, only 4 memory cell transistors MT4 to MT7 are shown for each sub-string STRB. However, each sub-string STRB may also contain more memory cell transistors MT.

[0018] The dummy memory cell transistor MTD has the same structure as the memory cell transistor MT, but it is a transistor that is not used for holding valid data. In each NAND string NS, the dummy memory cell transistor MTD is arranged between the memory cell transistors MT0 to MT3 included in the first sub-block BLKSA and the memory cell transistors MT4 to MT7 included in the second sub-block BLKSB. The dummy memory cell transistor MTD is arranged, for example, to suppress the influence of the erasing operation of erasing the data of a certain sub-block BLKS from spreading to other sub-blocks BLKS (e.g., sub-blocks BLKS that do not erase data). Additionally, the number of dummy memory cell transistors MTD arranged between 2 sub-blocks BLKS in each NAND string NS is not limited to 1, and may also be 2 or more.

[0019] The drain of the drain side selection transistor STD is electrically connected to the bit line BL corresponding to the NAND string NS. The source of the drain side selection transistor STD is electrically connected to one end of the memory cell transistors MT0 to MT7 connected in electrical series. The control gate of the drain side selection transistor STD is electrically connected to one of the drain side selection gate lines SGD0 to SGD3. The drain side selection transistor STD is electrically connected to the row decoder module 16 via the drain side selection gate line SGD. The drain side selection transistor STD electrically connects the NAND string NS to the bit line BL when a prescribed voltage is applied to the corresponding drain side selection gate line SGD.

[0020] The drain of the source side selection transistor STS is electrically connected to the other end of the memory cell transistors MT0 to MT7 connected in electrical series. The source of the source side selection transistor STS is electrically connected to the source line SL. The control gate of the source side selection transistor STS is electrically connected to the source side selection gate line SGS. The source side selection transistor STS electrically connects the NAND string NS to the source line SL when a prescribed voltage is applied to the source side selection gate line SGS.

[0021] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are electrically commonly connected to the corresponding word lines WL0 to WL7 one by one. Further, in the same block BLK, the control gate of the dummy memory cell transistor MTD is electrically commonly connected to the dummy word line WLD. In the same string STR, the control gates of the drain side selection transistors STD are electrically commonly connected to the corresponding drain side selection gate lines SGD0 to SGD3. The control gates of the source side selection transistors STS are electrically commonly connected to the source side selection gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS assigned the same column address in a plurality of strings STR.

[0022] <3. Physical configuration of the semiconductor memory device> Next, the physical configuration of the semiconductor memory device 1 will be described. Figure 3 It is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3.

[0023] <3.1 First chip> The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0024] The semiconductor substrate 21 is a substrate that forms the base of the first chip 2. At least a part of the semiconductor substrate 21 is plate-shaped along the X direction and the Y direction. The peripheral circuit 22 is a circuit for causing the above-described memory cell array 11 to function. The peripheral circuit 22 includes one or more of the above-described command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. The insulating portion 23 covers the peripheral circuit 22. A plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0025] <3.2 Second chip> The second chip 3 is an array chip including the memory cell array 11. The second chip 3 has, for example, a memory cell array 11, an insulating portion 25, and a plurality of pads 26. Here, the insulating portion 25 and the plurality of pads 26 will be described, and the memory cell array 11 will be described later.

[0026] The insulating portion 25 covers the memory cell array 11. A plurality of pads 26 are provided on the surface of the insulating portion 25. Each pad 26 is electrically connected to the wiring included in the memory cell array 11. In the present embodiment, the first chip 2 and the second chip 3 are integrated by bringing the plurality of pads 24 of the first chip 2 into contact with the plurality of pads 26 of the second chip 3 facing each other.

[0027] <4. Physical Structure of Memory Cell Array> Next, the physical structure of the memory cell array 11 will be described. As Figure 3 shown, the memory cell array 11 includes: a stacked body 30, a source line SL, a plurality of memory posts MH, a plurality of bit lines BL, a plurality of contacts CH for the memory posts, a plurality of contacts VY for the memory posts, a plurality of contacts CC for the conductive layer, and a wiring portion 80.

[0028] <4.1 Stacked Body> First, the stacked body 30 will be described. Figure 4 is a cross-sectional view showing an enlarged view of the region surrounded by the F4 line of the semiconductor memory device 1 shown in Figure 3 . In addition, after Figure 4 , the configuration of the semiconductor memory device 1 is shown with the +Z direction as the upper side and the -Z direction as the lower side. In the following description, the +Z direction side may sometimes be referred to as "upper", and the -Z direction side may be referred to as "lower". However, these expressions are used for convenience of explanation and do not define the direction of gravity.

[0029] The stacked body 30 includes a first stacked body 31, a second stacked body 32, and an intermediate insulating layer 33. The first stacked body 31 is disposed on the +Z direction side with respect to the source line SL. The second stacked body 32 is disposed on the +Z direction side with respect to the first stacked body 31. The intermediate insulating layer 33 is disposed between the first stacked body 31 and the second stacked body 32 in the Z direction. The thickness of the intermediate insulating layer 33 in the Z direction is equal to or greater than the thickness of the insulating layer 42 in the Z direction described later. The intermediate insulating layer 33 is formed of a film containing silicon and oxygen, for example.

[0030] Each of the first stacked body 31 and the second stacked body 32 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. In each of the first stacked body 31 and the second stacked body 32, the plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked layer by layer in the Z direction.

[0031] The conductive layer 41 is a layer along the X direction and the Y direction and has conductivity. Each conductive layer 41 includes a conductive material such as tungsten, molybdenum, or silicon doped with impurities, for example. The conductive layer 41 is an example of a "gate electrode layer".

[0032] One or more of the conductive layers 41 located above in the plurality of conductive layers 41 in the laminate 30 can function as a drain-side select gate line SGD. The drain-side select gate line SGD is commonly provided with respect to a plurality of memory pillars MH arranged in the X direction and the Y direction. The intersection portion of the drain-side select gate line SGD and the channel layer 52 (described later) of each memory pillar MH functions as the above-described drain-side select transistor STD.

[0033] One or more of the conductive layers 41 located below in the plurality of conductive layers 41 in the laminate 30 can function as a source-side select gate line SGS. The source-side select gate line SGS is commonly provided with respect to a plurality of memory pillars MH arranged in the X direction and the Y direction. The intersection portion of the source-side select gate line SGS and the channel layer 52 of each memory pillar MH functions as the above-described source-side select transistor STS.

[0034] In the laminate 30, the plurality of conductive layers 41 include a conductive layer 41 that functions as a drain-side select gate line SGD. This conductive layer 41 may be referred to as a first conductive layer. The plurality of conductive layers 41 include a conductive layer 41 that functions as a source-side select gate line SGS. This conductive layer 41 may be referred to as a second conductive layer. In the laminate 30, at least a part of the remaining conductive layers 41 provided between the first conductive layer and the second conductive layer can function as a word line WL. The word line WL is commonly provided with respect to a plurality of memory pillars MH arranged in the X direction and the Y direction. In the present embodiment, the intersection portion of the word line WL and the channel layer 52 of each memory pillar MH functions as a memory cell transistor MT. The memory cell transistor MT will be described in detail later.

[0035] In the present embodiment, the plurality of word lines WL include a plurality of word lines WLA corresponding to the first sub-block BLKSA and a plurality of word lines WLB corresponding to the second sub-block BLKSB. The plurality of word lines WLA are included in the first laminate 31. The plurality of word lines WLB are included in the second laminate 32.

[0036] In the laminate 30, at least another part of the remaining conductive layers 41 provided between the first conductive layer and the second conductive layer can function as a dummy word line WLD. The dummy word line WLD is commonly provided with respect to a plurality of memory pillars MH arranged in the X direction and the Y direction. In the present embodiment, the intersection portion of the dummy word line WLD and the channel layer 52 of each memory pillar MH functions as a dummy memory cell transistor MTD.

[0037] In the present embodiment, one or more of the conductive layers 41 included in the first stack 31 that are located at the uppermost position may be referred to as upper conductive layers. One or more of the conductive layers 41 included in the second stack 32 that are located at the lowermost position may be referred to as lower conductive layers. One or more upper conductive layers and one or more lower conductive layers function as dummy word lines WLD. In other words, the dummy word lines WLD are arranged in the Z direction between the plurality of word lines WLA and the plurality of word lines WLB.

[0038] An insulating layer 42 is provided between two adjacent conductive layers 41 in the Z direction. The insulating layer 42 is an insulating film that insulates the two conductive layers 41. The insulating layer 42 is a layer along the X direction and the Y direction. The insulating layer 42 contains, for example, silicon and oxygen.

[0039] <4.2 Source line> The source line SL is arranged on the -Z direction side with respect to the stack 30. The source line SL is a conductive layer that extends in the X direction and the Y direction. The source line SL contains a conductive material such as tungsten, molybdenum, or silicon doped with impurities.

[0040] <4.3 Memory pillar> A plurality of memory pillars MH are arranged in the X direction and the Y direction (refer to Figure 3 ). Each memory pillar MH extends in the Z direction within the stack 30. Each memory pillar MH penetrates the stack 30. The lower end of each memory pillar MH is connected to the source line SL. The upper end of each memory pillar MH is connected to a contact CH described later. The memory pillar MH is an example of a "columnar body".

[0041] Figure 5 is Figure 4 a cross-sectional view of the semiconductor memory device 1 along the F5-F5 line shown in Figure 4 ).

[0042] The memory film 51 is provided on the outer peripheral side of the channel layer 52. The memory film 51 is located between the plurality of conductive layers 41 and the channel layer 52. The memory film 51 contains, for example, a barrier insulating film 61, a charge trapping film 62, and a tunnel insulating film 63.

[0043] A blocking insulating film 61 is disposed between a plurality of conductive layers 41 and a charge trapping film 62. The blocking insulating film 61 is an insulating film that suppresses reverse tunneling. Reverse tunneling is a phenomenon in which charges return from the word line WL to the charge trapping film 62. The blocking insulating film 61 is formed in a ring shape and extends in the Z direction. The blocking insulating film 61 is formed, for example, over the entire length of the storage pillar MH in the Z direction. The blocking insulating film 61 is, for example, a laminated structure film formed by laminating a plurality of insulating films such as a film containing silicon and oxygen or a film containing metal and oxygen. An example of the film containing metal and oxygen is aluminum oxide. The blocking insulating film 61 may also contain a high dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0044] The charge trapping film 62 is located between the blocking insulating film 61 and the tunnel insulating film 63. The charge trapping film 62 is formed in a ring shape and extends in the Z direction. The charge trapping film 62 is formed, for example, over the entire length of the storage pillar MH in the Z direction. The charge trapping film 62 is a functional film having a plurality of crystal defects (trapping energy levels) and capable of trapping charges into the crystal defects. The charge trapping film 62 contains, for example, silicon and nitrogen. A portion of the charge trapping film 62 adjacent to each word line WL is an example of a "charge storage portion" capable of storing information by storing charges.

[0045] The tunnel insulating film 63 is disposed between the channel layer 52 and the charge trapping film 62. The tunnel insulating film 63 is, for example, in a ring shape along the outer peripheral surface of the channel layer 52. The tunnel insulating film 63 extends in the Z direction along the channel layer 52. The tunnel insulating film 63 is formed, for example, over the entire length of the storage pillar MH in the Z direction. The tunnel insulating film 63 is a barrier disposed between the channel layer 52 and the charge trapping film 62. The tunnel insulating film 63 contains silicon and oxygen, or silicon, oxygen, and nitrogen.

[0046] The channel layer 52 is disposed inside the memory film 51. The channel layer 52 is formed in a ring shape, for example. The channel layer 52 extends in the Z direction. The channel layer 52 is formed, for example, over the entire length of the storage pillar MH in the Z direction. The channel layer 52 contains a semiconductor material such as polysilicon. The channel layer 52 may also be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 can form a channel to electrically connect the bit line BL and the source line SL.

[0047] Thus, at the same height as each word line WL, a memory cell transistor MT of, for example, a MANOS (Metal - Al - Nitride - Oxide - Silicon) type is formed by the edge portion of the word line WL adjacent to the storage pillar MH, the blocking insulating film 61, the charge trapping film 62, the tunnel insulating film 63, and the channel layer 52. In addition, as the charge storage portion, the memory film 51 may have a charge storage portion (floating gate electrode) of a floating gate type instead of the charge trapping film 62. The floating gate electrode contains, for example, silicon doped with impurities.

[0048] The insulating core 53 is disposed inside the channel layer 52. The insulating core 53 fills at least a part of the inside of the channel layer 52. The insulating core 53 contains silicon and oxygen. A part of the insulating core 53 is formed in a columnar shape along the inner peripheral surface of the channel layer 52. The insulating core 53 may also have a space portion (air gap) inside the insulating core 53. The insulating core 53 extends in the Z direction. The insulating core 53, for example, except for the upper end portion of the storage column MH, extends over most of the Z direction of the storage column MH (refer to Figure 4 ).

[0049] Next, return Figure 4 , and explain the cover portion 54. The cover portion 54 is disposed above the insulating core 53. The cover portion 54 contains a semiconductor material such as amorphous silicon or polycrystalline silicon. The cover portion 54 may also be doped with impurities. The cover portion 54 is disposed on the inner peripheral side of the upper end portion of the memory film 51. The cover portion 54 is formed integrally with the channel layer 52. The cover portion 54 forms the upper end portion of the storage column MH together with the upper end portion of the channel layer 52. The contact CH is in contact with the cover portion 54 in the Z direction.

[0050] As Figure 4 shown, each storage column MH is, for example, a two-stage columnar body in the Z direction. Each storage column MH includes a first columnar portion 71 and a second columnar portion 72. The first columnar portion 71 is located between the source line SL and the second columnar portion 72 in the Z direction. The second columnar portion 72 is disposed on the +Z direction side with respect to the first columnar portion 71. The diameters of the first columnar portion 71 and the second columnar portion 72 gradually decrease as they advance in the -Z direction. In other words, the widths in the X direction of the first columnar portion 71 and the second columnar portion 72 gradually decrease as they advance in the -Z direction. In the present embodiment, the width in the X direction of the upper end of the first columnar portion 71 is greater than the width in the X direction of the lower end of the second columnar portion 72. Further, in the present embodiment, the width W1 in the X direction of the +Z direction side end MHe1 of the storage column MH is greater than the width W2 in the X direction of the -Z direction side end MHe2 of the storage column MH. The width W2 in the X direction of the -Z direction side end MHe2 refers to the width in the X direction at the contact position between the storage column MH and the surface of the source line SL.

[0051] <4.4 Bit lines> Next, explain the bit line BL. The bit line BL is a wiring for selecting at least one memory cell stack MH from a plurality of memory cell stacks MH. The plurality of bit lines BL are arranged on the +Z direction side with respect to the stacked body 30. The plurality of bit lines BL are arranged at intervals in the X direction in the X direction. Each bit line BL extends in the Y direction. Each bit line BL is connected to the channel layer 52 of the memory cell stack MH via the contact VY, the contact CH, and the cover portion 54. Thus, by the combination of the word line WL and the bit line BL, any memory cell transistor MT can be selected from the plurality of three-dimensionally arranged memory cell transistors MT.

[0052] <Contact for 4.5 conductive layers> As Figure 3 shown, the contact CC is an electrical connection portion that electrically connects the conductive layer 41 and the wiring included in the wiring portion 80. The plurality of contacts CC extend in the Z direction. For example, the lengths of the plurality of contacts CC in the Z direction are different from each other. One end of each contact CC is electrically connected to the corresponding conductive layer 41. The other end of each contact CC is electrically connected to the wiring included in the wiring portion 80.

[0053] <5. Shape of word line> Next, the shape of the conductive layer 41 according to the present embodiment will be described. Figure 6 is to Figure 4 A cross-sectional view showing an enlarged view of the region surrounded by the F6 line of the semiconductor memory device 1 shown. Each word line WL includes a conductive portion 45 and a barrier metal film 46.

[0054] The conductive portion 45 is a portion that forms the main part of the word line WL. The conductive portion 45 extends in a layered manner in the X direction and the Y direction. The conductive portion 45 includes the above-described conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0055] The barrier metal film 46 is a film for suppressing the diffusion of the conductive material contained in the conductive portion 45. The barrier metal film 46 is provided along the surface of the conductive portion 45. For example, the barrier metal film 46 is provided along both the +Z direction side surface and the -Z direction side surface of the conductive portion 45. The barrier metal film 46 includes, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen.

[0056] (Configuration of the second stacked body) First, the configuration of the second stacked body 32 will be described. As Figure 6As shown, the multiple word lines WLB of the second stacked body 32 include, for example, a word line WLB-1, a word line WLB-2, and a word line WLB-3. In the present embodiment, the +Z direction side is an example of the "first side". The word line WLB-1 is an example of the "first gate electrode layer". The word line WLB-2 is arranged on the +Z direction side with respect to the word line WLB-1. The word line WLB-2 is a word line WLB among the multiple word lines WLB that is adjacent to the word line WLB-1. The word line WLB-2 is an example of the "second gate electrode layer". The word line WLB-3 is arranged on the +Z direction side with respect to the word line WLB-2. The word line WLB-3 is a word line WLB among the multiple word lines WLB that is adjacent to the word line WLB-2.

[0057] In addition, the multiple insulating layers 42 of the second stacked body 32 include, for example, an insulating layer 42B-1, an insulating layer 42B-2, and an insulating layer 42B-3. In the present embodiment, the -Z direction side is an example of the "second side". The insulating layer 42B-1 is adjacent to the word line WLB-1 on the -Z direction side. The insulating layer 42B-1 is an example of the "first insulating layer". The insulating layer 42B-2 is located between the word line WLB-1 and the word line WLB-2. The insulating layer 42B-2 is an example of the "second insulating layer". The insulating layer 42B-3 is located between the word line WLB-2 and the word line WLB-3.

[0058] (Shape of the word line of the second stacked body) Next, the shape of the word line WLB will be described. In the present embodiment, each word line WLB includes a base portion 101 and a retreat portion 102.

[0059] The base portion 101, for example, in the word line WLB, is included between the center of the word line WLB in the Z direction and the surface on the -Z direction side of the word line WLB. The base portion 101 has a shape along the memory pillar MH in the Z direction. The base portion 101 has an edge 101a adjacent to the memory pillar MH in the X direction.

[0060] The retreat portion 102 is located on the +Z direction side with respect to the base portion 101. The retreat portion 102, for example, in the word line WLB, is included between the center of the word line WLB in the Z direction and the surface on the +Z direction side of the word line WLB. At least a part of the retreat portion 102 retreats from the base portion 101 in a manner away from the memory pillar MH in the X direction. The retreat portion 102 is inclined, for example, in such a way that the more it is located on the +Z direction side, the farther it is from the memory pillar MH. The retreat portion 102 has an edge 102a adjacent to the memory pillar MH in the X direction.

[0061] In the present embodiment, the memory film 51 of the storage column MH has a bulging portion 51a that bulges toward the recessed portion 102 of each word line WLB at a height corresponding to the recessed portion 102 of the word line WLB. Similarly, the channel layer 52 of the storage column MH has a bulging portion 52a that bulges toward the recessed portion 102 of each word line WLB at a height corresponding to the recessed portion 102 of the word line WLB. When viewed from the Z direction, the bulging portion 51a and the bulging portion 52a are each formed in a ring shape, for example.

[0062] In the present embodiment, the base portion 101 of the word line WLB-1 is an example of the "first part". The edge 101a of the base portion 101 of the word line WLB-1 is an example of the "first edge portion". The recessed portion 102 of the word line WLB-1 is an example of the "second part". The edge 102a of the recessed portion 102 of the word line WLB-1 is an example of the "second edge portion". The edge 102a of the word line WLB-1 is inclined relatively greatly with respect to the Z direction as compared with the edge 101a of the word line WLB-1.

[0063] Similarly, the base portion 101 of the word line WLB-2 is an example of the "third part". The edge 101a of the base portion 101 of the word line WLB-2 is an example of the "third edge portion". The recessed portion 102 of the word line WLB-2 is an example of the "fourth part". The edge 102a of the recessed portion 102 of the word line WLB-2 is an example of the "fourth edge portion". The edge 102a of the word line WLB-2 is inclined relatively greatly with respect to the Z direction as compared with the edge 101a of the word line WLB-2.

[0064] (Dimension relationship of word lines in the second stacked body) Next, the dimension relationship of the word line WLB of the second stacked body 32 will be described. When viewed from Figure 6 the cross section shown (the cross section along the X direction and the Z direction), the following dimension relationship is satisfied. The word line WLB-1 has a first edge E1 and a second edge E2 at a first boundary B1 along the X direction that is the boundary between the word line WLB-1 and the insulating layer 42B-1. The first edge E1 is adjacent to the storage column MH in the X direction. The second edge E2 is adjacent to the storage column MH from the side opposite to the first edge E1 in the X direction. The distance in the X direction between the first edge E1 and the second edge E2 is defined as a first distance L1.

[0065] In addition, the word line WLB-1 has a third edge E3 and a fourth edge E4 at a second boundary B2 along the X direction, which is the boundary between the word line WLB-1 and the insulating layer 42B-2. The third edge E3 is adjacent to the storage column MH in the X direction. The fourth edge E4 is adjacent to the storage column MH from the side opposite to the third edge E3 in the X direction. The distance in the X direction between the third edge E3 and the fourth edge E4 is defined as a second distance L2.

[0066] In addition, the word line WLB-2 has a fifth edge E5 and a sixth edge E6 at a third boundary B3 along the X direction, which is the boundary between the word line WLB-2 and the insulating layer 42B-2. The fifth edge E5 is adjacent to the storage column MH in the X direction. The sixth edge E6 is adjacent to the storage column MH from the side opposite to the fifth edge E5 in the X direction. The distance in the X direction between the fifth edge E5 and the sixth edge E6 is defined as a third distance L3.

[0067] In this case, the second distance L2 is greater than the first distance L1 and greater than the third distance L3. Additionally, from another perspective, the shortest distance between the channel layer 52 and the third edge E3 is greater than the shortest distance between the channel layer 52 and the first edge E1, and greater than the shortest distance between the channel layer 52 and the fifth edge E5.

[0068] This relationship is also satisfied between the other two word lines WLB included in the second stacked body 32. For example, the above relationship is also satisfied between the word line WLB-2 and the word line WLB-3. In this case, as long as in the above description regarding the word line WLB-1 and the word line WLB-2, "word line WLB-1" is replaced with "word line WLB-2", "word line WLB-2" is replaced with "word line WLB-3", "insulating layer 42B-1" is replaced with "insulating layer 42B-2", and "insulating layer 42B-2" is replaced with "insulating layer 42B-3".

[0069] Figure 7 is Figure 6 a cross-sectional view of the semiconductor memory device 1 along the line F7-F7 as shown. As Figure 6 shown, there is a second boundary B2 along the X direction at the boundary between the word line WLB-1 and the insulating layer 42B-2. As Figure 7 shown, when viewed from the Z direction, at the second boundary B2 (see Figure 6 ), a ring-shaped first boundary line BD1 is defined by the ring-shaped edge EC1 of the word line WLB-1. The first boundary line BD1 is defined between the word line WLB-1 and the storage column MH. Similarly, as Figure 6 shown, there is a third boundary B3 along the X direction at the boundary between the word line WLB-2 and the insulating layer 42B-2. AsFigure 7 As shown, when viewed from the Z direction, at the third boundary B3 (see Figure 6 ), a ring-shaped second boundary line BD2 is defined by the ring-shaped edge EC2 of the word line WLB-2. The second boundary line BD2 is defined between the word line WLB-2 and the memory pillar MH. When viewed from the Z direction, the second boundary line BD2 is located inside the first boundary line BD1.

[0070] This relationship is also satisfied between the other two word lines WLB included in the second stack 32. For example, the above relationship is also satisfied between the word line WLB-2 and the word line WLB-3. In this case, as long as in the above description regarding the word line WLB-1 and the word line WLB-2, "word line WLB-1" is replaced with "word line WLB-2", "word line WLB-2" is replaced with "word line WLB-3", and "insulating layer 42B-2" is replaced with "insulating layer 42B-3".

[0071] (Structure of the first stack) Next, the structure of the first stack 31 will be described. As Figure 6 shown, the multiple word lines WLA of the first stack 31 include, for example, the word line WLA-1, the word line WLA-2, and the word line WLA-3. The word line WLA-1 is arranged on the -Z direction side with respect to the word line WLB-1. The word line WLA-1 is an example of the "third gate electrode layer". The word line WLA-2 is arranged between the word line WLA-1 and the word line WLB-1. The word line WLA-2 is the word line WLA adjacent to the word line WLA-1 among the multiple word lines WLA. The word line WLA-2 is an example of the "fourth gate electrode layer". The word line WLA-3 is arranged on the +Z direction side with respect to the word line WLA-2. The word line WLA-3 is the word line WLB adjacent to the word line WLA-2 among the multiple word lines WLA.

[0072] In addition, the multiple insulating layers 42 of the first stack 31 include, for example, the insulating layer 42A-1, the insulating layer 42A-2, and the insulating layer 42A-3. The insulating layer 42A-1 is located between the word line WLA-1 and the word line WLA-2. The insulating layer 42A-1 is an example of the "third insulating layer". The insulating layer 42A-2 is located between the word line WLA-2 and the word line WLA-3. The insulating layer 42A-2 is adjacent to the word line WLA-2 on the +Z direction side. The insulating layer 42A-2 is an example of the "fourth insulating layer". The insulating layer 42A-3 is adjacent to the word line WLA-3 on the +Z direction side.

[0073] (Shape of the word line of the first stack) Next, the shape of the word line WLA will be described. In the present embodiment, each word line WLA includes a base portion 111 and a recessed portion 112.

[0074] The base portion 111 is, for example, included in the word line WLA between the center of the word line WLA in the Z direction and the surface on the +Z direction side of the word line WLA. The base portion 111 has a shape along the memory pillar MH in the Z direction. The base portion 111 has an edge 111a adjacent to the memory pillar MH in the X direction.

[0075] The recessed portion 112 is located on the -Z direction side with respect to the base portion 111. The recessed portion 112 is, for example, included in the word line WLA between the center of the word line WLA in the Z direction and the surface on the -Z direction side of the word line WLA. At least a part of the recessed portion 112 recedes from the base portion 111 in a manner of being away from the memory pillar MH in the X direction. The recessed portion 112 is inclined, for example, in such a manner that the more it is located on the -Z direction side, the farther it is from the memory pillar MH. The recessed portion 112 has an edge 112a adjacent to the memory pillar MH in the X direction.

[0076] In the present embodiment, the memory film 51 of the memory pillar MH has a bulged portion 51a bulging toward the recessed portion 112 of the word line WLA at a height corresponding to the recessed portion 112 of each word line WLA. Similarly, the channel layer 52 of the memory pillar MH has a bulged portion 52a bulging toward the recessed portion 112 of the word line WLA at a height corresponding to the recessed portion 112 of each word line WLA. When viewed from the Z direction, the bulged portion 51a and the bulged portion 52a are each formed, for example, in an annular shape.

[0077] In the present embodiment, the edge 112a of the word line WLA-1 is inclined relatively largely with respect to the Z direction compared to the edge 111a of the word line WLA-1. Similarly, the edge 112a of the word line WLA-2 is inclined relatively largely with respect to the Z direction compared to the edge 111a of the word line WLA-2.

[0078] (Dimension relationship of the word line of the first stack) Next, the dimension relationship of the word line WLA of the first stack 31 will be described. In the case of observing from Figure 6 the cross section (cross section along the X direction and the Z direction) shown, the following dimension relationship is satisfied. The word line WLA-1 has a seventh edge E7 and an eighth edge E8 at a fourth boundary B4 along the X direction, which is the boundary between the word line WLA-1 and the insulating layer 42A-1. The seventh edge E7 is adjacent to the memory pillar MH in the X direction. The eighth edge E8 is adjacent to the memory pillar MH from the side opposite to the seventh edge E7 in the X direction. Let the distance in the X direction between the seventh edge E7 and the eighth edge E8 be the fourth distance L4.

[0079] In addition, the word line WLA-2 has a ninth edge E9 and a tenth edge E10 at a fifth boundary B5 along the X direction, which is the boundary between the word line WLA-2 and the insulating layer 42A-1. The ninth edge E9 is adjacent to the memory pillar MH in the X direction. The tenth edge E10 is adjacent to the memory pillar MH from the side opposite to the ninth edge E9 in the X direction. The distance in the X direction between the ninth edge E9 and the tenth edge E10 is defined as a fifth distance L5.

[0080] In addition, the word line WLA-2 has an eleventh edge E11 and a twelfth edge E12 at a sixth boundary B6 along the X direction, which is the boundary between the word line WLA-2 and the insulating layer 42A-2. The eleventh edge E11 is adjacent to the memory pillar MH in the X direction. The twelfth edge E12 is adjacent to the memory pillar MH from the side opposite to the eleventh edge E11 in the X direction. The distance in the X direction between the eleventh edge E11 and the twelfth edge E12 is defined as a sixth distance L6.

[0081] In this case, the fifth distance L5 is greater than the fourth distance L4 and greater than the sixth distance L6. Additionally, from another perspective, the shortest distance between the channel layer 52 and the ninth edge E9 is greater than the shortest distance between the channel layer 52 and the seventh edge E7, and greater than the shortest distance between the channel layer 52 and the eleventh edge E11.

[0082] This relationship is also satisfied between the other two word lines WLA included in the first stack 31. For example, the above relationship is also satisfied between the word line WLA-2 and the word line WLA-3. In this case, in the above description regarding the word line WLA-1 and the word line WLA-2, just replace "word line WLA-1" with "word line WLA-2", "word line WLA-2" with "word line WLA-3", "insulating layer 42A-1" with "insulating layer 42A-2", and "insulating layer 42A-2" with "insulating layer 42A-3".

[0083] Figure 8 is Figure 6 a cross-sectional view of the semiconductor memory device 1 along the line F8-F8 as shown. As Figure 6 shown, there is a fifth boundary B5 along the X direction at the boundary between the word line WLA-2 and the insulating layer 42A-1. As Figure 8 shown, when viewed from the Z direction, at the fifth boundary B5 (see Figure 6 ), a ring-shaped fourth boundary line BD4 is defined by the ring-shaped edge EC4 of the word line WLA-2. The fourth boundary line BD4 is defined between the word line WLA-2 and the memory pillar MH. Similarly, as Figure 6As shown, there is a fourth boundary B4 in the X direction at the boundary between the word line WLA-1 and the insulating layer 42A-1. As Figure 8 shown, when viewed from the Z direction, at the fourth boundary B4 (see Figure 6 ), a ring-shaped third boundary line BD3 is defined by the ring-shaped edge EC3 of the word line WLA-1. The third boundary line BD3 is defined between the word line WLA-1 and the memory pillar MH. When viewed from the Z direction, the third boundary line BD3 is located inside the fourth boundary line BD4.

[0084] This relationship is also satisfied between the other two word lines WLA included in the first stack 31. For example, the above relationship is also satisfied between the word line WLA-2 and the word line WLA-3. In this case, as long as in the above description regarding the word line WLA-1 and the word line WLA-2, "word line WLA-1" is replaced with "word line WLA-2", "word line WLA-2" is replaced with "word line WLA-3", and "insulating layer 42A-1" is replaced with "insulating layer 42A-2".

[0085] <6. Configuration of the end region> Next, the end region ER of the memory cell array 11 will be described. Figure 9 is Figure 3 a cross-sectional view of the semiconductor memory device 1 along the line F9-F9. The stack 30 has a memory region CR and an end region ER.

[0086] The memory region CR includes the above-described plurality of conductive layers 41 and the plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked layer by layer in the Z direction. The plurality of conductive layers 41 are formed by a replacement process, which is a process of replacing a sacrificial layer (the insulating layer 130 described later) provided during manufacturing with the conductive layer 41.

[0087] On the other hand, the end region ER includes a plurality of insulating layers 130 instead of the plurality of conductive layers 41. That is, the end region ER includes a plurality of insulating layers 130 and the plurality of insulating layers 42. The plurality of insulating layers 130 and the plurality of insulating layers 42 are alternately stacked layer by layer in the Z direction. The insulating layer 130 is an insulating layer that remains in the stack 30 without being replaced by the conductive layer 41 due to its presence in the end region ER. In addition, a plurality of dummy memory pillars MHD are provided in the end region ER. The dummy memory pillar MHD is a columnar body having the same configuration as the memory pillar MH but not used for data storage.

[0088] Figure 10 is to Figure 9Cross-sectional view showing an enlarged view of the region of the semiconductor memory device 1 surrounded by the F10 line.

[0089] (Structure of the second stack) First, the structure of the second stack 32 will be described. As the plurality of insulating layers 130, the second stack 32 includes a plurality of insulating layers 130B. Each insulating layer 130B includes an insulating layer 131B and an insulating layer 132B.

[0090] The insulating layer 131B is included, for example, between the center in the Z direction of the insulating layer 130B and the surface on the -Z direction side of the insulating layer 130B in the insulating layer 130B. The insulating layer 131B may have the same thickness and the same shape as the base portion 101 of the word line WLB. The insulating layer 131B includes a first material. An example of the first material includes nitrogen and silicon (for example, silicon nitride (SiN)).

[0091] The insulating layer 132B is located on the +Z direction side with respect to the insulating layer 131B. The insulating layer 132B is included, for example, between the center in the Z direction of the insulating layer 130B and the surface on the +Z direction side of the insulating layer 130B in the insulating layer 130B. At least a part of the insulating layer 132B recedes from the dummy memory pillar MHD in the X direction with respect to the insulating layer 131B. The insulating layer 132B is inclined, for example, so as to be farther away from the dummy memory pillar MHD as it is located more on the +Z direction side. The insulating layer 132B may have the same thickness and the same shape as the recessed portion 102 of the word line WLB. The insulating layer 132B includes a second material. The second material has a different composition from the first material. The second material is a material that is more easily removed by the first etchant than the first material (for example, a material having a different wet etching rate with respect to the first etchant). An example of the second material includes nitrogen and silicon and has a higher oxygen content than the above-mentioned first material (for example, silicon nitride doped with oxygen (SiN)).

[0092] The presence of these two insulating layers, the insulating layer 131B and the insulating layer 132B, can be confirmed, for example, by the following method. (1) Observe the interface between the insulating layer 131B and the insulating layer 132B using a transmission electron microscope (TEM: Transmission Electron microscope). (2) Detect the case where the components (for example, oxygen concentration) in the insulating layer 131B and the insulating layer 132B are different through component analysis. Such a method is also applicable to the method for confirming the presence of the insulating layer 131A and the insulating layer 132A described later.

[0093] (Structure of the first stack) Next, the structure of the first stack 31 will be described. As the plurality of insulating layers 130, the first stack 31 includes a plurality of insulating layers 130A. Each insulating layer 130A includes an insulating layer 131A and an insulating layer 132A.

[0094] The insulating layer 131A is included, for example, between the center in the Z direction of the insulating layer 130A and the surface on the +Z direction side of the insulating layer 130A in the insulating layer 130A. The insulating layer 131A may have the same thickness and the same shape as the base portion 111 of the word line WLA. The insulating layer 131A contains the above-described first material.

[0095] The insulating layer 132A is located on the -Z direction side with respect to the insulating layer 131A. The insulating layer 132A is included, for example, between the center in the Z direction of the insulating layer 130A and the surface on the -Z direction side of the insulating layer 130A in the insulating layer 130A. At least a part of the insulating layer 132A recedes from the insulating layer 131A in the X direction so as to be away from the dummy memory pillar MHD. The insulating layer 132A is inclined, for example, so as to be more away from the dummy memory pillar MHD as it is more located on the -Z direction side. The insulating layer 132A may have the same thickness and the same shape as the recessed portion 112 of the word line WLA. The insulating layer 132A contains the above-described second material.

[0096] <7. Control Method> Next, the control method of the semiconductor memory device 1 will be described. In addition, the control method described below is executed, for example, by the control circuit 14.

[0097] <7.1 Write Sequence> Figure 11 is a diagram showing the write sequence according to the first embodiment. As Figure 11 shown, the data writing for the first sub-block BLKSA is performed by the following process: Regarding the plurality of word lines WLA of the first stack 31, starting from the word line WLA located at the uppermost side, the programming voltage Vpgm for data writing is sequentially applied to the word lines WLA located below one by one (refer to arrow A1 in the figure). On the other hand, the data writing for the second sub-block BLKSB is performed by the following process: Regarding the plurality of word lines WLB of the second stack 32, starting from the word line WLB located at the lowermost side, and then the programming voltage Vpgm for data writing is sequentially applied to the word lines WLB located above one by one (refer to arrow A2 in the figure).

[0098] In addition, in the present application, the so-called "applying a programming voltage" means, for example, repeatedly performing the following programming cycle until a specified condition is satisfied. The programming cycle includes: an operation of applying a programming voltage Vpgm; a programming verification for determining whether the threshold voltage of the memory cell transistor MT to be written has reached a threshold voltage corresponding to the desired data due to the application of the programming voltage Vpgm; and a voltage change operation for increasing the set value of the programming voltage Vpgm when the above programming verification fails.

[0099] In the present embodiment, a memory cell transistor MTA-1 is formed at the intersection of the word line WLA-1 and the memory pillar MH. A memory cell transistor MTA-2 is formed at the intersection of the word line WLA-2 and the memory pillar MH. A memory cell transistor MTA-3 is formed at the intersection of the word line WLA-3 and the memory pillar MH. The memory cell transistor MTA-1 is an example of the "third memory cell transistor". The memory cell transistor MTA-2 is an example of the "fourth memory cell transistor".

[0100] The memory cell transistors MTA-1 to MTA-3 are arranged in the -Z direction in the order of the memory cell transistor MTA-3, the memory cell transistor MTA-2, and the memory cell transistor MTA-1. In this case, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTA-3, and then performs a writing operation of injecting charge into the memory cell transistor MTA-2, and then performs a writing operation of injecting charge into the memory cell transistor MTA-1.

[0101] On the other hand, a memory cell transistor MTB-1 is formed at the intersection of the word line WLB-1 and the memory pillar MH. A memory cell transistor MTB-2 is formed at the intersection of the word line WLB-2 and the memory pillar MH. A memory cell transistor MTB-3 is formed at the intersection of the word line WLB-3 and the memory pillar MH. The memory cell transistor MTB-1 is an example of the "first memory cell transistor". The memory cell transistor MTB-2 is an example of the "second memory cell transistor".

[0102] The memory cell transistors MTB-1 to MTB-3 are arranged in the -Z direction in the order of the memory cell transistor MTB-3, the memory cell transistor MTB-2, and the memory cell transistor MTB-1. In this case, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTB-1, and then performs a writing operation of injecting charge into the memory cell transistor MTB-2, and then performs a writing operation of injecting charge into the memory cell transistor MTB-3.

[0103] <7.2 Voltage Management of the Channel Layer> Here, voltage management of the channel layer 52 will be described. When the potential of the channel layer 52 is reduced to a negative potential for some reason before a write operation, it is possible that the voltage of the channel layer 52 does not rise sufficiently during the write operation, resulting in a large potential difference when the programming voltage Vpgm is applied, and the threshold voltage of the memory cell transistor MT that is not the write target increases. Therefore, the control circuit 14 of the present embodiment performs channel pre-charging to reset the voltage of the channel layer 52 to 0V before the write operation.

[0104] Figure 12 is a diagram schematically showing the memory stack MH. Figure 13 is for explaining the Figure 12 shown timing chart of the write operation related to the memory stack MH. In Figure 13 Among them, in the voltage applied to the word line WL, the voltage annotated with "Vpgm" refers to the above-mentioned programming voltage Vpgm. On the other hand, in the voltage applied to the word line WL, the voltage between 0 and Vpgm without the annotation "Vpgm" refers to a voltage that is high enough to make the memory cell transistor MT conductive but low enough not to perform a write.

[0105] As Figure 13 shown, in the write to the first stack 31 (write to the first sub-block BLKSA), before performing the write operation on each memory cell transistor MT, channel pre-charging PA is performed by applying a voltage to the source-side select gate line SGS to electrically connect the channel layer 52 to the source line SL and make the voltage of the channel layer 52 0V. Therefore, in the write to the first stack 31 (write to the first sub-block BLKSA), after performing the channel pre-charging PA using the source-side select gate line SGS, the write operation is performed in the order of the memory cell transistor MT3, the memory cell transistor MT2, the memory cell transistor MT1, and the memory cell transistor MT0.

[0106] On the other hand, in the writing operation for the second stack 32 (writing operation for the second sub-block BLKSB), the first stack 31 (the first sub-block BLKSA) is already in the written state, making it difficult to perform channel pre-charging PA using the source-side selection gate line SGS. Therefore, in the writing operation for the second stack 32 (writing operation for the second sub-block BLKSB), before performing the writing operation on each memory cell transistor MT, channel pre-charging PB is performed by applying a voltage to the drain-side selection gate line SGD to electrically connect the channel layer 52 to the bit line BL, so that the voltage of the channel layer 52 becomes 0V. Therefore, in the writing operation for the second stack 32 (writing operation for the second sub-block BLKSB), after performing channel pre-charging PB using the drain-side selection gate line SGD, the writing operation is performed in the order of the memory cell transistor MT4, the memory cell transistor MT5, the memory cell transistor MT6, and the memory cell transistor MT7.

[0107] <8. Manufacturing method> Next, a manufacturing method of the semiconductor memory device 1 will be described. Figure 14A and Figure 14B are cross-sectional views for explaining the manufacturing method of the semiconductor memory device 1. In addition, hereinafter, for ease of explanation, illustrations related to the manufacturing process of the dummy word line WLD are omitted. In addition, hereinafter, the manufacturing process related to a plurality of word lines WL will be mainly described. The processes other than the following description can be implemented by known techniques.

[0108] First, an insulating layer 141 is formed on the insulating layer 42. The insulating layer 141 is a sacrificial layer that will be replaced with the source-side selection gate line SGS in the subsequent replacement process. Next, a stack 151 is formed above the insulating layer 141. The stack 151 is formed by repeatedly stacking the insulating layer 132A, the insulating layer 131A, and the insulating layer 42 in this order in the Z direction. Next, an intermediate insulating layer 33 (refer to Figure 14A ST1 in

[0109] Next, a hole HA that penetrates the intermediate insulating layer 33, the stack 151, and the insulating layer 141 in the Z direction is formed (refer to Figure 14AST2) in. Then, the inside of the hole HA is filled with the insulating portion 142. Then, a stacked body 152 is formed above the intermediate insulating layer 33. The stacked body 152 is formed by repeatedly stacking the insulating layer 131B, the insulating layer 132B, and the insulating layer 42 in this order in the Z direction. The insulating layer 131B is an example of the "first layer". The insulating layer 132B is an example of the "second layer". The insulating layer 42 is an example of the "third layer". Then, an insulating layer 143 is formed above the stacked body 152. The insulating layer 143 is a sacrificial layer that is replaced with the drain-side select gate line SGD in the replacement process described later (see Figure 14A ST3) in.

[0110] Next, a hole HB is formed that penetrates the insulating layer 143 and the stacked body 152 in the Z direction. Then, the insulating portion 142 in the hole HA is removed by etching through the hole HB (see Figure 14B ST4) in. Then, etching is performed by supplying a first etchant to the inside of the hole HA and the hole HB (e.g., wet etching). At this time, the second material contained in the insulating layer 132A and the insulating layer 132B is more easily removed by the first etchant than the first material contained in the insulating layer 131A and the insulating layer 131B. Therefore, the insulating layer 132A is cut more than the insulating layer 131A and retreats away from the hole HA with respect to the insulating layer 131A. As a result, a step is formed between the insulating layer 132A and the insulating layer 42. Similarly, the insulating layer 132B is cut more than the insulating layer 131B and retreats away from the hole HB with respect to the insulating layer 131B. As a result, a step is formed between the insulating layer 132B and the insulating layer 42 (see Figure 14B ST5) in.

[0111] Next, a memory pillar MH is formed inside the hole HA and the hole HB. That is, the memory pillar MH is formed by sequentially supplying the materials of the memory film 51, the channel layer 52, and the insulating core 53 inside the hole HA and the hole HB.

[0112] Next, a replacement process is performed. That is, the insulating layer 131A, the insulating layer 131B, the insulating layer 132A, the insulating layer 132B, the insulating layer 141, and the insulating layer 143 are removed by etching through a groove (not shown). Then, a word line WLA is formed by supplying a conductive material to the space after removing the insulating layer 131A and the insulating layer 132A. Similarly, a word line WLB is formed by supplying a conductive material to the space after removing the insulating layer 131B and the insulating layer 132B. A source-side select gate line SGS is formed by supplying a conductive material to the space after removing the insulating layer 141. A drain-side select gate line SGD is formed by supplying a conductive material to the space after removing the insulating layer 143 (see Figure 14Bin ST6). Thus, the manufacturing process related to the multiple word lines WL is completed.

[0113] <9. Function> Next, the function of the semiconductor memory device 1 will be described. Figure 15 is a cross-sectional view for explaining the function of the semiconductor memory device 1. Here, the effect will be described taking the word line WLB as an example.

[0114] As Figure 15 shown, the word line WLB has a base portion 101 and a recessed portion 102 located on the +Z direction side with respect to the base portion 101. Here, through the research of the present inventor, it has been confirmed that in the memory cell transistor MTB (for example, the memory cell transistor MTB-2) to be written, which is connected to the word line WLB having the recessed portion 102, charges are concentrated and stored in a region closer to the +Z direction side than the center in the Z direction of the memory cell transistor MTB.

[0115] Therefore, by providing the recessed portion 102 in the word line WLB, the region where charges are concentrated and stored in the memory cell transistor MTB-2 can be biased toward the +Z direction side in a manner away from the written memory cell transistor MTB (for example, the memory cell transistor MTB-1) with respect to the center in the Z direction of the memory cell transistor MTB-2. As a result, the influence of the write operation on the memory cell transistor MTB-2 on the written memory cell transistor MTB-1 (the influence of so-called adjacent interference) becomes smaller. Therefore, the electrical characteristics of the semiconductor memory device 1 are improved. The same applies to the word line WLA having the recessed portion 112.

[0116] (Second Embodiment) Next, the second embodiment will be described. The difference between the second embodiment and the first embodiment is that the memory pillar MH includes three columnar portions 71, 72, and 73. In addition, the configuration other than the following description is the same as that of the first embodiment.

[0117] Figure 16 is a cross-sectional view showing the semiconductor memory device 1A according to the second embodiment. In the present embodiment, the laminate 30 has a first laminate 31, a second laminate 32, an intermediate insulating layer 33, a third laminate 34, and an intermediate insulating layer 35.

[0118] The second stacked body 32 is disposed on the +Z direction side with respect to the first stacked body 31. The intermediate insulating layer 33 is disposed between the first stacked body 31 and the second stacked body 32 in the Z direction. The third stacked body 34 is disposed on the +Z direction side with respect to the second stacked body 32. The intermediate insulating layer 35 is disposed between the second stacked body 32 and the third stacked body 34 in the Z direction. The thickness of the intermediate insulating layer 35 in the Z direction is greater than the thickness of the insulating layer 42 in the Z direction. The intermediate insulating layer 35 contains, for example, silicon and oxygen.

[0119] The first stacked body 31, the second stacked body 32, and the third stacked body 34 each include a plurality of conductive layers 41 and a plurality of insulating layers 42. In each of the first stacked body 31, the second stacked body 32, and the third stacked body 34, the plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked layer by layer in the Z direction.

[0120] In the present embodiment, the word line WL included in the first stacked body 31 and the word line WL included in the lower half of the second stacked body 32 are the word line WLA. On the other hand, the word line WL included in the third stacked body 34 and the word line WL included in the upper half of the second stacked body 32 are the word line WLB. The third stacked body 34 has one or more dummy word lines WLD between the word line WLA and the word line WLB.

[0121] Each storage pillar MH is, for example, a three-stage columnar body in the Z direction, and includes a first columnar portion 71, a second columnar portion 72, and a third columnar portion 73. The first columnar portion 71 is disposed in the first stacked body 31 and the intermediate insulating layer 33. The second columnar portion 72 is disposed in the second stacked body 32 and the intermediate insulating layer 35. The third columnar portion 73 is disposed in the third stacked body 34. The diameters of the first columnar portion 71, the second columnar portion 72, and the third columnar portion 73 gradually decrease as they advance in the -Z direction. In other words, the widths of the first columnar portion 71, the second columnar portion 72, and the third columnar portion 73 in the X direction gradually decrease as they advance in the -Z direction.

[0122] In the present embodiment, a plurality of memory cell transistors MTA are formed at the intersection of the plurality of word lines WLA and the storage pillar MH. The plurality of memory cell transistors MTA include: memory cell transistors MTA-1, MTA-2, MTA-3 formed at the intersection of the first stacked body 31 and the first columnar portion 71; and memory cell transistors MTA-4, MTA-5 formed at the intersection of the second stacked body 32 and the second columnar portion 72. They are arranged in the -Z direction in the order of memory cell transistor MTA-5, memory cell transistor MTA-4, memory cell transistor MTA-3, memory cell transistor MTA-2, memory cell transistor MTA-1.

[0123] Similarly, a plurality of memory cell transistors MTB are formed at the intersections of a plurality of word lines WLB and memory columns MH. The plurality of memory cell transistors MTB include: memory cell transistors MTB-1 and MTB-2 formed at the intersection of the second stacked body 32 and the second columnar portion 72; and memory cell transistors MTB-3, MTB-4, and MTB-5 formed at the intersection of the third stacked body 34 and the third columnar portion 73. They are arranged in the -Z direction in the order of memory cell transistor MTB-5, memory cell transistor MTB-4, memory cell transistor MTB-3, memory cell transistor MTB-2, and memory cell transistor MTB-1.

[0124] In the present embodiment, data writing for the first sub-block BLKSA is performed through the following process: in the word line WL (word line WLA) corresponding to the first sub-block BLKSA, starting from the uppermost word line WLA, a programming voltage Vprg is sequentially applied to the lower word lines WLA one by one. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTA-5, then performs a writing operation of injecting charge into the memory cell transistor MTA-4, then performs a writing operation of injecting charge into the memory cell transistor MTA-3, then performs a writing operation of injecting charge into the memory cell transistor MTA-2, and then performs a writing operation of injecting charge into the memory cell transistor MTA-1.

[0125] On the other hand, data writing for the second sub-block BLKSB is performed through the following process: in the word line WL (word line WLB) corresponding to the second sub-block BLKSB, starting from the lowermost word line WLB, a programming voltage Vprg is sequentially applied to the upper word lines WLB one by one. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTB-1, then performs a writing operation of injecting charge into the memory cell transistor MTB-2, then performs a writing operation of injecting charge into the memory cell transistor MTB-3, then performs a writing operation of injecting charge into the memory cell transistor MTB-4, and then performs a writing operation of injecting charge into the memory cell transistor MTB-5.

[0126] According to such a configuration, similarly to the first embodiment, a semiconductor memory device 1A capable of improving electrical characteristics can be provided.

[0127] (Third Embodiment) Next, the third embodiment will be described. The difference between the third embodiment and the first embodiment is that the word line WL included in the first stacked body 31 is the word line WLA'. In addition, the configuration other than the following description is the same as that of the first embodiment.

[0128] Figure 17 FIG. 2 is a cross-sectional view showing the semiconductor memory device 1B according to the third embodiment. In the present embodiment, the word line WL (the word line corresponding to the first sub-block BLKSA) included in the first stack 31 is the word line WLA'. The word line WLA' is a word line WL that does not have the recessed portion 112. The operation of the control circuit 14 is the same as that of the first embodiment. Even with such a configuration, it is possible to provide, for example, a semiconductor memory device 1B that can achieve an improvement in electrical characteristics at least with respect to the word line WLB.

[0129] (Fourth Embodiment) Next, the fourth embodiment will be described. The difference between the fourth embodiment and the first embodiment is that the word line WL included in the first stack 31 is the word line WLB. In addition, the configuration other than the following description is the same as that of the first embodiment.

[0130] Figure 18 FIG. 3 is a cross-sectional view showing the semiconductor memory device 1C according to the fourth embodiment. In the present embodiment, the word line WL included in the first stack 31 is the word line WLB. Data writing for the first sub-block BLKSA is performed by the following process: In the word line WL (word line WLB) corresponding to the first sub-block BLKSA, starting from the lowermost word line WLB, a programming voltage Vprg is sequentially applied to the word lines WLB located above one by one. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTA-1, and then performs a writing operation of injecting charge into the memory cell transistor MTA-2, and then performs a writing operation of injecting charge into the memory cell transistor MTA-3. With such a configuration, it is possible to provide a semiconductor memory device 1C that can achieve an improvement in electrical characteristics.

[0131] (Fifth Embodiment) Next, the fifth embodiment will be described. The difference between the fifth embodiment and the first embodiment is that the word line WL included in the second stack 32 is the word line WLA. In addition, the configuration other than the following description is the same as that of the first embodiment.

[0132] Figure 19It is a cross-sectional view showing the semiconductor memory device 1D according to the fifth embodiment. The word line WL included in the second stack 32 is the word line WLA. In the present embodiment, the -Z direction side is an example of the "first side". The +Z direction side is an example of the "second side". The word line WLA-1 is an example of the "first gate electrode layer". The word line WLA-2 is an example of the "second gate electrode layer". The seventh edge E7, the eighth edge E8, the ninth edge E9, the tenth edge E10, the eleventh edge E11, and the twelfth edge E12 are respectively examples of the "first edge", the "second edge", the "third edge", the "fourth edge", the "fifth edge", and the "sixth edge". The fourth distance L4, the fifth distance L5, and the sixth distance L6 are respectively examples of the "first distance", the "second distance", and the "third distance".

[0133] Data writing for the second sub-block BLKSB is performed by the following process: In the word line WL (word line WLA) corresponding to the second sub-block BLKSB, starting from the uppermost word line WLA, a programming voltage Vprg is sequentially applied to the word lines WLA located below one by one. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTB-3, and then performs a writing operation of injecting charge into the memory cell transistor MTB-2, and then performs a writing operation of injecting charge into the memory cell transistor MTB-1. According to such a configuration, a semiconductor memory device 1D capable of improving electrical characteristics can be provided.

[0134] Above, some embodiments have been described, but the embodiments are not limited to the above examples. For example, some of the above embodiments can also be combined with each other to be implemented.

[0135] According to at least one of the embodiments described above, the semiconductor memory device includes a stack and a columnar body. When the distance between the first edge of the first gate electrode layer adjacent to the columnar body and the second edge of the first gate electrode layer adjacent to the columnar body from the side opposite to the first edge at the boundary between the first gate electrode layer and the first insulating layer is set as the first distance, the distance between the third edge of the first gate electrode layer adjacent to the columnar body and the fourth edge of the first gate electrode layer adjacent to the columnar body from the side opposite to the third edge at the boundary between the first gate electrode layer and the second insulating layer is set as the second distance, and the distance between the fifth edge of the second gate electrode layer adjacent to the columnar body and the sixth edge of the second gate electrode layer adjacent to the columnar body from the side opposite to the fifth edge at the boundary between the second gate electrode layer and the second insulating layer is set as the third distance, the second distance is greater than the first distance and greater than the third distance. According to such a configuration, improvement of electrical characteristics can be achieved.

[0136] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope equivalent to the invention described in the claims. [Description of Reference Numerals]

[0137] 1, 1A, 1B, 1C, 1D: Semiconductor memory device, 30: Stacked body, 41: Conductive layer (gate electrode layer), 42: Insulating layer, 51: Memory film, 52: Channel layer, 101: Base portion (first part), 102: Retracted portion (second part), WLB-1: Word line (first gate electrode layer), WLB-2: Word line (second gate electrode layer), WLA-1: Word line (third gate electrode layer), WLA-2: Word line (fourth gate electrode layer), 42B-1: Insulating layer (first insulating layer), 42B-2: Insulating layer (second insulating layer), 42A-1: Insulating layer (third insulating layer), 42A-2: Insulating layer (fourth insulating layer), MH: Memory column (columnar body).

Claims

1. A semiconductor storage device comprising: A stacked body comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately stacked layer by layer in a first direction; and a columnar body extending in the first direction within the stacked body and including a memory film and a channel layer, The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer, the second gate electrode layer being arranged on a first side in the first direction relative to the first gate electrode layer and being located next to the first gate electrode layer in the plurality of gate electrode layers, The plurality of insulating layers include a first insulating layer adjacent to the first gate electrode layer from a second side in the first direction, the second side being opposite to the first side, and a second insulating layer located between the first gate electrode layer and the second gate electrode layer. When a direction orthogonal to the first direction is taken as a second direction and observed at a cross section along the first direction and the second direction: A distance between a first edge of the first gate electrode layer adjacent to the column at a first boundary between the first gate electrode layer and the first insulating layer and along the second direction and a second edge of the first gate electrode layer adjacent to the column from a side opposite to the first edge is set as a first distance, a distance between a third edge of the first gate electrode layer adjacent to the column at a second boundary between the first gate electrode layer and the second insulating layer and along the second direction and a fourth edge of the first gate electrode layer adjacent to the column from a side opposite to the third edge as a second distance, When the distance between the fifth edge of the second gate electrode layer adjacent to the column at the third boundary between the second gate electrode layer and the second insulating layer and along the second direction and the sixth edge of the second gate electrode layer adjacent to the column from the side opposite to the fifth edge is set as the third distance, The second distance is greater than the first distance and greater than the third distance.

2. The semiconductor memory device according to claim 1, wherein: When viewed from the first direction, At the second boundary, an annular first boundary line is defined between the first gate electrode layer and the columnar body by the edge of the first gate electrode layer. At the third boundary, an edge of the second gate electrode layer defines a second annular boundary line between the second gate electrode layer and the columnar body. When viewed from the first direction, the second boundary line is located inside the first boundary line.

3. The semiconductor memory device according to claim 1, wherein: The first gate electrode layer includes a first portion and a second portion located at the first side relative to the first portion, The first portion has a first edge portion adjacent to the columnar body, The second portion has a second edge portion adjacent to the columnar body, The second edge portion is more inclined relative to the first direction than the first edge portion. The second gate electrode layer includes a third portion and a fourth portion located on the first side relative to the third portion, The third portion has a third edge portion adjacent to the columnar body, The fourth portion has a fourth edge portion adjacent to the columnar body, The fourth edge portion is more inclined with respect to the first direction than the third edge portion.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein: A shortest distance between the channel layer and the third edge of the first gate electrode layer is greater than a shortest distance between the channel layer and the first edge of the first gate electrode layer.

5. The semiconductor memory device according to any one of claims 1 to 3, wherein: The width of the end of the first side of the column in the second direction is greater than the width of the end of the second side of the column in the second direction, The third edge and the fourth edge are located on the first side relative to the first edge and the second edge.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein: The width of the end of the second side of the column in the second direction is greater than the width of the end of the first side of the column in the second direction, The third edge and the fourth edge are located on the first side relative to the first edge and the second edge.

7. The semiconductor memory device according to any one of claims 1 to 3, wherein: It also has a control circuit. A first memory cell transistor is formed at an intersection of the first gate electrode layer and the columnar body, and a second memory cell transistor is formed at an intersection of the second gate electrode layer and the columnar body. The control circuit can control the first memory cell transistor and the second memory cell transistor in such a manner that a second write operation is performed after a first write operation. The first writing operation includes an operation of injecting charge into the first memory cell transistor when writing data. The second writing operation includes an operation of injecting charge into the second memory cell transistor when writing data.

8. The semiconductor memory device according to any one of claims 1 to 3, wherein: The plurality of gate electrode layers include a third gate electrode layer and a fourth gate electrode layer, the third gate electrode layer being arranged on the second side relative to the first gate electrode layer, the fourth gate electrode layer being arranged between the first gate electrode layer and the third gate electrode layer and being located next to the third gate electrode layer among the plurality of gate electrode layers, The plurality of insulating layers include a third insulating layer and a fourth insulating layer, the third insulating layer is located between the third gate electrode layer and the fourth gate electrode layer, and the fourth insulating layer is adjacent to the fourth gate electrode layer from the first side, When observed at the cross section, a distance between a seventh edge of the third gate electrode layer adjacent to the column at a fourth boundary along the second direction between the third gate electrode layer and the third insulating layer and an eighth edge of the third gate electrode layer adjacent to the column from a side opposite to the seventh edge is set as a fourth distance, a fifth distance between a ninth edge of the fourth gate electrode layer adjacent to the column at a fifth boundary between the fourth gate electrode layer and the third insulating layer and along the second direction and a tenth edge of the fourth gate electrode layer adjacent to the column from a side opposite to the ninth edge, When the distance between the eleventh edge of the fourth gate electrode layer adjacent to the column at the sixth boundary between the fourth gate electrode layer and the fourth insulating layer and along the second direction and the twelfth edge of the fourth gate electrode layer adjacent to the column from the side opposite to the eleventh edge is set as the sixth distance, The fifth distance is greater than the fourth distance and greater than the sixth distance.

9. The semiconductor memory device according to claim 8, wherein: It also has a control circuit. A first memory cell transistor is formed at an intersection of the first gate electrode layer and the column, a second memory cell transistor is formed at an intersection of the second gate electrode layer and the column, a third memory cell transistor is formed at an intersection of the third gate electrode layer and the column, and a fourth memory cell transistor is formed at an intersection of the fourth gate electrode layer and the column. The control circuit can control the first memory cell transistor, the second memory cell transistor, the third memory cell transistor, and the fourth memory cell transistor in such a manner that a second write operation is performed after a first write operation, and a third write operation is performed after a fourth write operation. The first writing operation includes an operation of injecting charge into the first memory cell transistor when writing data. The second writing operation includes an operation of injecting charge into the second memory cell transistor when writing data. The third writing operation includes an operation of injecting charge into the third memory cell transistor when writing data. The fourth writing operation includes an operation of injecting charge into the fourth memory cell transistor when writing data.

10. A method for controlling a semiconductor memory device, The semiconductor storage device comprises: A stacked body comprising a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately stacked layer by layer in a first direction; and a columnar body extending in the first direction within the stacked body and including a memory film and a channel layer, The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, and a fourth gate electrode layer, the second gate electrode layer being arranged on a first side in the first direction relative to the first gate electrode layer and being located next to the first gate electrode layer among the plurality of gate electrode layers, the third gate electrode layer being arranged on a second side opposite to the first side in the first direction relative to the first gate electrode layer, the fourth gate electrode layer being arranged between the first gate electrode layer and the third gate electrode layer and being located next to the third gate electrode layer among the plurality of gate electrode layers, The plurality of insulating layers include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first insulating layer being adjacent to the first gate electrode layer from the second side, the second insulating layer being located between the first gate electrode layer and the second gate electrode layer, the third insulating layer being located between the third gate electrode layer and the fourth gate electrode layer, and the fourth insulating layer being adjacent to the fourth gate electrode layer from the first side, When a direction orthogonal to the first direction is taken as a second direction and observed at a cross section along the first direction and the second direction: A distance between a first edge of the first gate electrode layer adjacent to the column at a first boundary between the first gate electrode layer and the first insulating layer and along the second direction and a second edge of the first gate electrode layer adjacent to the column from a side opposite to the first edge is set as a first distance, a distance between a third edge of the first gate electrode layer adjacent to the column at a second boundary between the first gate electrode layer and the second insulating layer and along the second direction and a fourth edge of the first gate electrode layer adjacent to the column from a side opposite to the third edge as a second distance, When the distance between the fifth edge of the second gate electrode layer adjacent to the column at the third boundary between the second gate electrode layer and the second insulating layer and along the second direction and the sixth edge of the second gate electrode layer adjacent to the column from the side opposite to the fifth edge is set as the third distance, the second distance is greater than the first distance and greater than the third distance, A distance between a seventh edge of the third gate electrode layer adjacent to the column at a fourth boundary between the third gate electrode layer and the third insulating layer and along the second direction and an eighth edge of the third gate electrode layer adjacent to the column from a side opposite to the seventh edge is set as a fourth distance, a fifth distance between a ninth edge of the fourth gate electrode layer adjacent to the column at a fifth boundary between the fourth gate electrode layer and the third insulating layer and along the second direction and a tenth edge of the fourth gate electrode layer adjacent to the column from a side opposite to the ninth edge, When the distance between the eleventh edge of the fourth gate electrode layer adjacent to the column at the sixth boundary between the fourth gate electrode layer and the fourth insulating layer and along the second direction and the twelfth edge of the fourth gate electrode layer adjacent to the column from the side opposite to the eleventh edge is set as the sixth distance, The fifth distance is greater than the fourth distance and greater than the sixth distance, A first memory cell transistor is formed at an intersection of the first gate electrode layer and the column, a second memory cell transistor is formed at an intersection of the second gate electrode layer and the column, a third memory cell transistor is formed at an intersection of the third gate electrode layer and the column, and a fourth memory cell transistor is formed at an intersection of the fourth gate electrode layer and the column. When writing data, the control method includes the following processing: After a first writing operation of injecting charge into the first memory cell transistor, a second writing operation of injecting charge into the second memory cell transistor is performed. After the third writing operation of injecting charges into the third memory cell transistor, a fourth writing operation of injecting charges into the fourth memory cell transistor is performed.

11. A method for manufacturing a semiconductor memory device, comprising the following steps: A stacked body is formed by repeatedly stacking a first layer, a second layer that is more easily removed by a first etchant than the first layer, and an insulating third layer in the order of the first layer, the second layer, and the third layer in a first direction, a hole formed in the stacked body and extending in the first direction, The first etchant is supplied into the hole to perform etching to remove a portion of the second layer, thereby forming a step between the second layer and the third layer. forming a columnar body including a memory film and a channel layer inside the hole, The first layer and the second layer are removed by etching, and a gate electrode layer is formed in a space after the first layer and the second layer are removed.

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