Driver discharge circuit

Abstract

The driver includes first and second switches (SW1, SW2). The first transistor (M1) has a first control input and first and second current terminals. A resistor (R1) is coupled between a voltage supply terminal and the first control input. A configurable voltage clamping circuit (660) has a voltage clamping control input and a voltage clamping circuit output, the voltage clamping circuit output coupled to the first control input. A second transistor (M2) has a second control input and third and fourth current terminals. The logic circuit (620) includes a comparator (630) having a comparator output. The logic circuit (620) is coupled to the voltage supply terminal and the voltage clamp control input. The logic circuit (620) is configured to configure the voltage clamping circuit (660) at the voltage clamping circuit output for a first clamping voltage in response to the first switch (SW1) being turned on, and to configure the voltage clamping circuit (660) at the voltage clamping circuit output for a second clamping voltage based on a signal at the comparator output.

Description

Background Art

[0001] A circuit includes any one of a variety of electrical components, such as transistors, resistors, capacitors, diodes, inductors, etc. The circuit can perform any one of a variety of different functions. However, an electrical overstress condition may occur, which may be harmful to one or more of the components of the circuit. Summary of the Invention

[0002] A driver includes first and second switches. A first transistor has a first control input and first and second current terminals. A resistor is coupled between a voltage supply terminal and the first control input. A configurable voltage clamping circuit has a voltage clamping control input and a voltage clamping circuit output, and the voltage clamping circuit output is coupled to the first control input. A second transistor has a second control input and third and fourth current terminals. A logic circuit includes a comparator having a comparator output. The logic circuit is coupled to the voltage supply terminal and the voltage clamping control input. The logic circuit is configured to configure the voltage clamping circuit for a first clamping voltage at the voltage clamping circuit output in response to the first switch being turned on, and to configure the voltage clamping circuit for a second clamping voltage at the voltage clamping circuit output based on a signal at the comparator output. Description of the Drawings

[0003] Figure 1 is a circuit schematic diagram of a power system in an example, the power system including a transistor driver that can be subjected to an electrical overstress condition.

[0004] Figure 2 is a circuit schematic diagram of at least a part of a driver further illustrating an electrical potential overstress condition in an example.

[0005] Figure 3 is a graph of waveforms associated with a driver in which an electrical overstress condition may not occur Figure 2 and

[0006] Figure 4 is a graph of waveforms associated with a driver in which an electrical overstress condition may occur Figure 2 and

[0007] Figure 5 is a circuit schematic diagram of an example of a discharge circuit of a driver for mitigating an electrical overstress condition.

[0008] Figure 6 is a circuit schematic diagram of another example of a discharge circuit of a driver for mitigating an electrical overstress condition.

[0009] Figure 7 is a timing diagram illustrating Figure 6 the operation of the discharge circuit in an example.

[0010] Figure 8 is a schematic diagram of a comparator circuit of a discharge circuit for implementation in an example Figure 6 for the discharge circuit. DETAILED DESCRIPTION

[0011] Identical reference numerals or other reference indicators are used in the drawings to denote (functionally and / or structurally) identical or similar features.

[0012] The examples described herein relate to a discharge circuit for releasing energy from parasitic inductance to protect transistors within a driver from electro - overstress conditions. However, the principles described herein may be applied to other applications besides drivers.

[0013] Figure 1 is a schematic diagram of a circuit of system 100. System 100 includes a pulse - width modulator (PWM) controller 110, a driver integrated circuit (IC) 120, a high - side (HS) transistor, a low - side (LS) transistor, an output stage 130, and a power supply 140. The power supply 140 provides a power supply voltage (VDD referenced to VSS) to the power supply terminals 121 and 122 of the driver IC 120 (connections shown) and to the PWM controller 110 (connections not shown). In this example, the HS transistor and the LS transistor are n - channel field - effect transistors (NFETs). The voltage on the gate of the HS transistor is HSG, and the voltage on the gate of the LS transistor is LSG. The source of the HS transistor is coupled to the drain of the LS transistor at a switch node (SW). The output stage 130 is coupled to the SW node. The output stage 130 can generate an output voltage (VOUT). The output stage 130 also generates a feedback voltage (VFB) proportional to the output voltage (e.g., via a resistor divider not shown). The feedback voltage VFB is provided to an input of the PWM controller 110, and the PWM controller (which may be fabricated as a separate IC from the driver IC 120) generates a PWM control signal 115. The driver IC 120 includes a high - side driver 150 and a low - side driver 160, which control the on and off states of the respective HS and LS transistors. The PWM control signal 115 is provided to an input of the high - side driver 150, and the logical inverse of the PWM control signal 115 is provided to an input of the low - side driver 160 via an inverter 125. The PWM controller 110, the driver IC 120, the HS and LS transistors, the output stage 130, and the power supply 140 may be mounted on a printed circuit board (PCB) 105 or other suitable medium for interconnecting components.

[0014] System 100 can be implemented to provide any of a variety of functions. For example, system 100 can be a switched voltage converter, such as a buck converter, a boost converter, a buck-boost converter, a half-bridge converter, a full-bridge converter, etc. The output stage 130 is specific to a particular type of converter. For example, in the case of a buck converter, the output stage 130 includes an inductor coupled to an output capacitor. One terminal of the inductor is coupled to a switch node. The other terminal of the inductor is coupled to the output capacitor and provides the output voltage VOUT. By another example, in the case of a half-bridge converter, the output stage 130 includes a transformer. The primary side of the transformer can be coupled to the switch node. The output stage also includes a rectifier that is coupled to the secondary side of the transformer to generate the output voltage VOUT. In other examples, system 100 can be a motor controller or a class-D audio amplifier.

[0015] Figure 1 Shows parasitic inductances L1 and L2. Parasitic inductance L1 includes the parasitic inductance of a trace (or other type of conductive element) of the PCB between the VDD output of the power supply and the power supply terminal 121 of the driver IC 120. Parasitic inductance L1 can also include the parasitic inductance of a connection (e.g., bond wire, pin) between the PCB and the voltage supply terminal 121 of the driver IC. Similarly, parasitic inductance L2 includes the parasitic inductance of a PCB / driver IC connection (e.g., bond wire, pin) between the PCB trace and the VSS output of the power supply and the power supply ground terminal 122 of the driver IC. Parasitic inductances L1 and L2 can cause electro-overstress conditions in the high-side driver 150 and / or the low-side driver 160, as described below with respect to Figure 2 as described.

[0016] Figure 2 is a schematic diagram of at least a portion of the high-side driver 150 and the low-side driver 160. Figure 2 The input signal in is the PWM control signal 115, which is the input signal to the high-side driver 150. The input signal to the low-side driver 160 is the logical inverse of the PWM control signal 115 through the inverter 125, as described above in the example of Figure 1 Each driver includes a first switch SW1 coupled in series between the power supply terminals 121 and 122 to a second switch SW2. In one example, switches SW1 and SW2 are transistors, and in one particular example, the transistors are NFETs. The connection 202 between switches SW1 and SW2 is the output of the driver, which is coupled to the gate of the corresponding HS or LS transistor. In Figure 2 , the HS or LS transistor coupled to the driver is modeled as a capacitive load C1 on the driver 150(160). The capacitive load C1 represents the gate-to-source capacitance of the corresponding HS or LS transistor and the parasitic capacitance of the PCB, and is referred to herein as the parasitic capacitance C1.

[0017] When the PWM control signal 115 is logic high, switch SW1 is turned on and SW2 is turned off. With switch SW1 turned on, current flows from the power supply VDD voltage through the parasitic inductor L1 and switch SW1 to charge the parasitic capacitance C1 of the corresponding HS or LS transistor. As current flows to charge the parasitic capacitance C1, the voltage across the parasitic capacitance C1 increases approximately linearly. The voltage across the parasitic capacitance C1 is HSG for the HS transistor (or LSG for the LS transistor). When a time-varying current flows through the inductor, energy is stored in the inductor, resulting in a voltage being generated across the inductor. When current flows into the gate of the HS (or LS) transistor, the voltage HSG across the parasitic capacitance C1 increases and the voltage across the parasitic inductor L1 (VDD - HSG) changes, so energy is stored in the parasitic inductor L1.

[0018] When the parasitic capacitance C1 is fully charged (HSG reaches VDD), the voltage drop across the parasitic inductor L1 decreases to approximately 0V and the energy in the inductor L1 decreases. Some energy is transferred to the parasitic capacitance C1 and some energy is lost as heat. If at this time (little or no energy is stored in the inductor L1), the PWM control signal 115 transitions to the logic low state, then switch SW1 is turned off and switch SW2 is turned on, and there is little energy in the inductor L1 that needs to be released.

[0019] However, if the PWM control signal 115 transitions to the logic low state while the parasitic capacitance C1 is still charging (i.e., HSG has not reached VDD), then when switch SW1 is turned off, energy remains stored in the parasitic inductor L1, and the voltage on the power supply terminal 121 may increase due to the sudden stop of the current through switch SW1 to the gate of the HS (or LS) transistor unless the energy stored in the parasitic inductor L1 is released. As described above, switch SW1 is implemented as a transistor. The rated voltage of the transistor implementing switch SW1 is the maximum acceptable voltage between its terminals. For example, the maximum acceptable drain-to-source voltage (Vds) of the transistor of switch SW1 may be 30V. In this example, a Vds exceeding 30V may damage the transistor. For this reason, the examples described herein include a discharge circuit to release the energy that may be stored in the parasitic inductor L1 when switch SW1 is to be turned off.

[0020] When the pulse width (PW1, Figure 2 ) is short enough such that the parasitic capacitance C1 of the HS (or LS) transistor is not fully charged to VDD before the end of the pulse of the PWM control signal 115, the problems described above may occur. Figure 3 and 4 are signal waveforms that jointly illustrate the problem. In Figure 3In this case, the width of the PWM pulse is PW1A, and PW1A is long enough such that HSG (the voltage across the parasitic capacitance C1) can reach VDD before the end (falling edge 301) of the PWM pulse. Since HSG reaches VDD before the switch SW1 turns off (which occurs when the falling edge 301 of the PWM pulse appears), little or no energy is stored in the parasitic inductance L1.

[0021] However, in Figure 4 this case, the width PW1B of the PWM pulse is short enough such that HSG does not have time to reach VDD before the falling edge 401 of the PWM pulse occurs to turn off the switch SW1. The amount of energy stored in the parasitic inductance L1 is a function of the voltage difference (VDD - HSG) when the current stops flowing through the switch SW1 and thus stops flowing through the parasitic inductance L1.

[0022] The width of the pulse of the PWM control signal 115 can vary according to the load conditions on the switching converter. For example, at light load or when the system 100 starts up, the width of the PWM pulse may be relatively small.

[0023] Figure 5 is a schematic diagram of an example driver 505, which includes a discharge circuit 510, switches SW1 and SW2, and an inverter 125. The connection between the switches SW1 and SW2 and the inverter 125 is the same as described above with respect to Figure 2 The voltage on the power supply terminal 121 is labeled VDD_PAD. The voltage VDD_PAD is typically equal to VDD from the power supply 140, but this voltage can be higher than VDD due to the sudden stop of current flow when there is energy stored in the parasitic inductance. As described below, in response to the voltage VDD_PAD reaching a threshold voltage that can be the maximum safe operating voltage of the driver IC 120, the discharge circuit 510 is triggered to release the energy stored in the parasitic inductance L1. The discharge circuit 510 disconnects the current path to allow the energy from the parasitic inductance L1 to flow to ground, thereby preventing the voltage VDD_PAD from increasing to a level that could damage the transistor implementing the switch SW1.

[0024] In Figure 5In an example, the discharge circuit 510 includes resistors R1 and R2, a voltage clamping circuit 520, transistors M1 and M2, and a Zener diode 535. Transistor M1 is a p-channel field effect transistor (PFET) and transistor M2 is an NFET, but in other examples, transistor M1 and / or M2 may be implemented as other types of transistors. Resistor R1 is coupled between the power supply terminal 121 and the gate of transistor M1 and the voltage clamping circuit 520. The source of transistor M1 is coupled to the power supply terminal 121. The drain of transistor M1 is coupled to resistor R2, the cathode of Zener diode 535, and the gate of transistor M2. Resistor R2 and Zener diode 535 are coupled in parallel between the gate of transistor M2 and the ground power supply terminal 122. The drain of transistor M2 is coupled to the power supply terminal 121. If and when transistor M2 is turned on, the current path is disconnected to allow current Isink to flow from the parasitic inductance L1 to VSS.

[0025] In this example, the voltage clamping circuit 520 is a fixed voltage clamping circuit that includes a plurality of Zener diodes 521 coupled in series between resistor R1 and the ground power supply terminal 122. If switch SW1 is turned off and the parasitic capacitance C1 is still charging (and thus the HSG has not reached VDD), the voltage VDD_PAD on the power supply terminal 121 can vary large enough such that the voltage across each Zener diode 521 reaches its Zener breakdown voltage. The Zener breakdown voltage may be the same for each Zener diode 521 or may vary between the diodes. In response to all Zener diodes 521 having reached their breakdown voltages, current I_R1 flows through resistor R1 and through the stack of Zener diodes 521 to VSS.

[0026] Until VDD_PAD is large enough to cause the Zener diodes to reach their breakdown voltages, the current I_R1 through resistor R1 is 0A, and thus the gate of transistor M1 is pulled up to the same voltage as its source (VDD_PAD). In this state, transistor M1 is turned off. With transistor M1 turned off, no drain current flows through transistor M1 and resistor R2. Therefore, the voltage on the gate of transistor M2 is low enough (e.g., 0V) to turn off transistor M2. The state of transistors M1 and M2 being turned off is the state of the discharge circuit 510 when the voltage VDD_PAD is not large enough to otherwise damage the transistor implementing switch SW1.

[0027] However, if the pulse width of the PWM pulse is short enough such that the parasitic capacitance C1 cannot be charged to VDD (HSG is less than VDD), then when the switch SW1 is turned off, the voltage VDD_PAD can rise as described above. Eventually, VDD_PAD rises to a high enough level such that the Zener diode 521 reaches its breakdown voltage. When this occurs, the current I_R1 flows through R1 and the Zener diode 521 of the voltage clamping circuit 520. The stack of Zener diodes 521 clamps the voltage (Vclamp) on the gate of the transistor M1 at a level equal to the sum of the breakdown voltages of the Zener diodes 521. The voltage Vclamp is dedicated and set by the number of Zener diodes 521 in the voltage clamping circuit and the specific breakdown voltage of each Zener diode. The value of Vclamp is set such that when the voltage level of VDD_PAD is approximately equal to the maximum allowable VDD of the driver 505, the Zener diode 521 starts to conduct the current I_R1. The voltage formed across the resistor R1 is VDD minus the clamping voltage Vclamp applied by the voltage clamping circuit 520 when the Zener diode 521 reaches its breakdown voltage. The voltage drop of the current I_R1 across R1 is large enough (e.g., greater than the threshold voltage of M1) such that the transistor M1 is turned on. In response to the transistor M1 being turned on, the current I_R2 flows through the transistor M1 and reaches VSS through the resistor R2. The voltage across the resistor R2 increases, thereby turning on the transistor M2. The transistor M2 is turned on, thereby disconnecting the current path to safely release the energy stored in the parasitic inductance L1, and thus not damaging the switch SW1. The Zener diode 535 clamps the voltage on the gate of the transistor M2 to protect the transistor M2 from harmful gate-source voltage (Vgs).

[0028] In Figure 5 the example of the discharge circuit 510 involves a two-phase operation in response to VDD_PAD becoming large enough to potentially damage the switch SW1. First, the transistor M1 is turned on, and second, after the transistor M1 is turned on, the transistor M2 is then turned on. As the transistors M1 and M2 are turned on in sequence, the voltage VDD_PAD continues to increase as described above. The voltage VDD_PAD continues to increase until the transistor M2 is turned on, thereby disconnecting the current path (Isink) to release the energy in the parasitic inductance L1. Since the voltage VDD_PAD continues to increase when the discharge circuit 510 responds as described above, the transistors used to implement the switch SW1 may need to be sized larger than would be required for the maximum rated VDD of the original driver. Therefore, the transistors implementing the switch SW2 can also be sized the same as those of the switch SW1, and the transistor M2 can also be sized the same. The sizing of the transistors of SW1 and SW2 and the transistor M2 undesirably results in a relatively large overall size of the driver 505.

[0029] Figure 6 is a schematic diagram of an example driver 605, the driver including a discharge circuit 610, the discharge circuit solving the problems mentioned above regarding the transistors of SW1 and SW2 and Figure 5 the transistor M2 of the discharge circuit 510. Compared with the case of the discharge circuit 510, Figure 6 the discharge circuit 610 of Figure 6 responds faster to an increase in the voltage VDD_PAD. In addition to the discharge circuit 610,

[0030] Figure 6 the illustrative discharge circuit 610 in

[0031] includes a logic circuit 620, a configurable voltage clamp circuit 660, resistors R1 and R2, transistors M1 and M2, and a Zener diode 535. The logic circuit 620 includes a comparator 630, a one-shot circuit 640, a logic gate 650 (an OR gate in this example), and a transistor M3. The comparator 630 includes a positive (+) input, a negative (-) input, and an output. The positive input of the comparator 630 is coupled to the power supply terminal 121 of the driver and thus receives the voltage VDD_PAD. The negative input of the comparator 630 is coupled to the connection between the switches SW1 and SW2 (connection 202) and thus receives the voltage HSG (or LSG). The comparator 630 outputs a comparator output signal COMP_OUT 631, which is at one logic level (e.g., logic high) when HSG is less than VDD and at another logic level (e.g., logic low) when HSG is within the offset of the comparator with respect to VDD (e.g., HSG equals VDD (within the offset of the comparator)).

[0032] As mentioned above regarding Figure 5As described, resistor R2 and Zener diode 535 are coupled in parallel between the gate of transistor M2 and VSS. Transistor M3 (an NFET in this example) is coupled across resistor R2. When transistor M3 is turned on, resistor R2 is shorted, forcing transistor M2 to turn off, and when transistor M3 is turned off, resistor R2 is not shorted, and if transistor M1 is turned on, then transistor M2 will turn on. A PWM control signal 115 is provided to the gate of transistor M3.

[0033] In this example, configurable voltage clamp circuit 660 includes four Zener diodes 662, 663, 664, and 665, but the number of Zener diodes for configurable voltage clamp circuit 660 is specific. Configurable voltage clamp circuit 660 also includes a transistor M4 (e.g., an NFET) coupled across at least one but not all of Zener diodes 662 - 665. In this example, transistor M4 is coupled across two of the four Zener diodes 664 and 665. When transistor M4 is turned on, Zener diodes 664 and 665 are shorted, and when transistor M4 is turned off, Zener diodes 664 and 665 are not shorted. The gate of transistor M4 is voltage clamp control input 658 of configurable voltage clamp circuit 660.

[0034] Logic circuit 620 configures configurable voltage clamp circuit 660 for a first clamp voltage at voltage clamp circuit output 661 in response to switch SW1 being turned on, and configures configurable voltage clamp circuit 660 for a second clamp voltage at voltage clamp circuit output 661 based on COMP_OUT signal 631 from comparator 630. The first clamp voltage may be less than the second clamp voltage. Monostable circuit 640 generates a fixed duration output pulse 642 (e.g., 10 ns) on its output 641 in response to the rising edge of PWM control signal 115. Through logic gate 650, the output pulse 642 of the monostable circuit is coupled to the gate of transistor M4, thereby turning on transistor M4. The rising edge of PWM control signal 115 initiates the process of closing switch SW1 to turn on the HS (or LS) transistor. Thus, when the HS (or LS) transistor is turned on, output pulse 642 of the monostable circuit occurs. In an example where logic gate 650 is an OR gate (as in Figure 6In the example of, the logic gate 650 responds to the output pulse 642 of the monostable circuit by transitioning its output signal 652 to a logic high state to turn on the transistor M3 for at least the duration of the output pulse of the monostable circuit. If the COMP_OUT signal 631 from the comparator 630 (which is logically ORed with the pulse 642 of the monostable circuit through the logic gate 650) is logic high during the pulse 642 from the monostable circuit 640 and remains logic high for a period of time thereafter, the logic gate 650 can keep the transistor M3 turned on for a duration longer than the width of the pulse 642 from the monostable circuit 640. In this example, the COMP_OUT signal 631 is logic high if HSG is less than VDD, which can occur if the parasitic capacitance C1 of the HS (or LS) transistor cannot be fully charged to VDD before the switch SW1 is turned off, as described above.

[0035] By turning on the transistor M3 when the switch SW1 is closed, the Zener diodes 664 and 665 are short-circuited at least for the duration of the pulse 642 of the monostable circuit 640, thereby reducing the voltage level of the VDD_PAD at which the Zener diodes 662 and 663 in the configurable voltage clamp circuit 660 reach their breakdown voltage. Therefore, the configurable voltage clamp circuit 660 turns on the transistor M1 in response to a lower VDD_PAD level than in the case of the voltage clamp circuit 520 of Figure 5 The transistor M1 in turns on in response to the switch SW1 being turned on, rather than conducting in response to the switch SW1 being turned off as in the case of the discharge circuit 510 of Figure 6 in. Figure 5 When the PWM control signal 115 is logic high (to turn on the switch SW1 and the HS transistor), the transistor M3 is also turned on, thereby short-circuiting the resistor R2 and preventing the transistor M2 from turning on, even though the transistor M1 is turned on. At the end of the positive pulse of the PWM control signal 115, the switch SW1 is turned off and the transistor M3 is turned off. If the transistor M1 is still turned on at the end of the positive pulse of the PWM control signal 115, then at this time, the transistor M1 is turned on and the transistor M2 then turns on, thereby disconnecting the discharge current path through the transistor M2 for the current Isink from the parasitic inductor L1. Since the transistor M1 was previously turned on (when the switch SW1 was initially closed), the time delay associated with turning on the transistor M1 when the switch SW1 in

[0036] is turned off is avoided. Therefore, compared with the discharge circuit 510 of Figure 5 when the switch SW1 is turned off, Figure 5 in Figure 6The discharge circuit 610 can respond faster to release the energy stored in the parasitic inductor L1. Since the discharge circuit 610 responds faster than the discharge circuit, the amplitude of the voltage VDD_PAD is maintained at a smaller level than in the case of the discharge circuit 610, and thus the transistors implementing the switches SW1 and SW2 and the transistor M2 can be advantageously made smaller than their corresponding parts in Figure 5 the discharge circuit 510.

[0037] Figure 7 is associated with Figure 6 An example timing diagram of some signals associated with the discharge circuit 610. The signals include the PWM control signal 115, the output pulse 642 of the one-shot circuit, the COMP_OUT signal 631 from the comparator 630, and the current Isink. Figure 7 The timing diagram of shows three scenarios 710, 720, and 730. Scenarios 710 and 720 illustrate that the PWM control signal pulse widths are short enough such that the parasitic capacitance C1 of the HS (or LS) transistor does not have time to fully charge to VDD. Scenario 730 illustrates a PWM control signal pulse width long enough to allow the parasitic capacitance C1 of the HS (or LS) transistor to fully charge to VDD. However, scenario 710 illustrates the width 712 of the PWM control signal 115, which is short enough such that the comparator 630 does not have time to respond to the difference between HSG (LSG) and VDD, and thus the COMP_OUT signal 631 is not asserted to logic high. However, the rising edge 711 of the PWM control signal 710 still causes the one-shot circuit 640 to generate an output pulse 642 (see reference numeral 713), which turns on the transistor M4 through the logic gate 650, thereby turning on the transistor M1. At the end of the pulse of the PWM control signal for scenario 710, which occurs before the end of the output pulse of the one-shot circuit, the transistor M1 has been turned on and the transistor M3 is turned off, thereby turning on the transistor M2, allowing the energy from the parasitic inductor L1 to be dissipated as the current Isink (see reference numeral 714) through the transistor M2.

[0038] For scenario 720, the width 722 of the PWM control signal 115 is longer than that of scenario 710, but still short enough such that the parasitic capacitance C1 does not have time to charge to VDD. The one-shot circuit 640 still generates a pulse, as indicated by reference numeral 723. In this scenario, the comparator 630 has time to react, and its output signal COMP_OUT 642 goes logic high (see reference numeral 725) in response to HSG (or LSG) being less than VDD. The output signal 652 from the logic gate 650 is the logical OR of the pulse 642 from the one-shot circuit 640 and the COMP_OUT 631 from the comparator 630. The duration 726 of the output signal 652 is long enough such that when the PWM control signal pulse ends at the falling edge 727, the transistor M1 is turned on and the transistor M3 is turned off, thereby turning on the transistor M2 to allow the Isink current (reference numeral 728) to flow from the parasitic inductor L1 to VSS.

[0039] For scenario 730, the signaling is similar to that of scenario 720, but the parasitic capacitance C1 is fully charged to VDD before the falling edge 737 of the PWM control signal 115 occurs. Thus, the output signal 651 of the comparator is logic low, and the output pulse 642 of the one-shot circuit has ended when the switch SW1 is turned off, so the transistor M3 is also turned off through the logic gate 650. In this state, the logic circuit configures the configurable voltage clamp circuit 660 for a higher clamp voltage associated with the level of VDD_PAD that is higher than the maximum allowable VDD of the driver. The level of VDD_PAD sufficient to activate the voltage clamp circuit 660 to turn on the transistor M1 is not reached because the parasitic capacitance C1 is fully charged to VDD and little or no energy is stored in the parasitic inductor L1.

[0040] Figure 8Schematic diagram of an example implementation of comparator 630, the comparator including transistors M5, M6, and M7, current source 632, and Schmitt trigger circuit 634. In this example, transistors M5 - M7 are p-type field effect transistors (PFETs). The sources of transistors M5 and M6 are coupled to VDD_PAD. Transistors M5 and M6 are configured as a current mirror. Transistor M7 is biased by a fixed voltage reference and is coupled between the drain of transistor M5 and HSG (or LSG). If the voltage of VDD_PAD is greater than that of HSG (parasitic capacitance C1 is not fully charged), then drain current flows through transistors M5 and M7. If the voltage of HSG has reached VDD, no current flows through transistor M5. The current flowing through transistor M5 is mirrored by transistor M6 (e.g., a 1:1 current mirror ratio). If the current flowing through transistor M6 is greater than the current magnitude of current source 632, the input voltage of Schmitt trigger circuit 634 will be logic high, otherwise if no current flows through transistor M6, the input voltage of Schmitt trigger circuit 634 will be logic low.

[0041] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, provided that intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A through the control signal generated by device A.

[0042] Also, in this specification, the statement "based on" means "at least partially based on". Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0043] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by the manufacturer to perform the function when manufactured, and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through the firmware and / or software programming of the device, through the construction and / or layout of hardware components, and the interconnection of the device, or a combination thereof.

[0044] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their ends.

[0045] A circuit or apparatus described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuit system or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may instead include semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within only a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., when or after being fabricated by an end user and / or a third party.

[0046] While the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the rest of the circuit system. For example, field effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used instead of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0047] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0048] As used herein, referring to an FET as “on” means that there is a conductive channel of the FET and a drain current can flow through the FET. Referring to an FET as “off” as used herein means that there is no conductive channel and a drain current does not flow through the FET. However, an “off” FET may have a current flowing through the body diode of the transistor.

[0049] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide a certain amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0050] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0051] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this description. In this specification, unless otherwise specified, "about," "substantially," or "essentially" in front of a parameter means within + / - 10% of the stated parameter, or if the parameter is zero, within a reasonable value that is approximately zero.

[0052] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A driver, comprising: A first switch; A second switch coupled between a voltage supply terminal and the first switch at a switch output, the second switch having a switch control input; A first transistor having a first control input and first and second current terminals; A resistor coupled between the voltage supply terminal and the first control input; A configurable voltage clamping circuit having a voltage clamping control input and a voltage clamping circuit output, the voltage clamping circuit output being coupled to the first control input; A second transistor having a second control input and third and fourth current terminals, the second control input being coupled to the second current terminal, and the third current terminal being coupled to the voltage supply terminal; And A logic circuit including a comparator having a comparator output, the logic circuit being coupled to the voltage supply terminal and the voltage clamping control input, the logic circuit being configured to configure the configurable voltage clamping circuit for a first clamping voltage at the voltage clamping circuit output in response to the first switch being turned on and to configure the configurable voltage clamping circuit for a second clamping voltage at the voltage clamping circuit output based on a signal at the comparator output.

2. The driver according to claim 1, wherein the logic circuit includes a one-shot circuit, and wherein the logic circuit is configured to configure the voltage clamping circuit for the first clamping voltage for a period of time at least based on a pulse duration of a pulse generated by the one-shot circuit in response to the first switch being turned on.

3. The driver according to claim 2, wherein the logic circuit is configured to configure the voltage clamping circuit for the first clamping voltage for a period of time equal to a duration of the pulse generated by the one-shot circuit, and when the comparator output is in a first logic state during the pulse generated by the one-shot circuit, after the pulse from the one-shot circuit, for a period of time until the signal at the comparator output changes from the first logic state to a second logic state.

4. The driver according to claim 1, wherein the first clamping voltage is less than the second clamping voltage.

5. The driver according to claim 1, wherein the comparator has a first comparator input and a second comparator input, the first comparator input being coupled to the voltage supply terminal, and the second comparator input being coupled to the switch output.

6. The driver according to claim 5, wherein the logic circuit includes a one-shot circuit and a logic gate having first and second logic gate inputs and a logic gate output, the first switch having a switch control input, the first logic gate input being coupled to the comparator output, and the one-shot circuit being coupled between the switch control input and the second logic gate input.

7. The driver according to claim 6, wherein the logic gate is an OR gate.

8. The driver according to claim 1, wherein the configurable voltage clamping circuit includes: A first Zener diode; A second Zener diode serially coupled with the first Zener diode between the first control input and the ground terminal; and A third transistor coupled across the second Zener diode.

9. The driver according to claim 8, wherein the third transistor has a third control input as the voltage clamping control input.

10. The driver according to claim 1, wherein the configurable voltage clamping circuit comprises: At least four Zener diodes serially coupled between the first control input and the ground terminal; and A third transistor coupled across at least two of the Zener diodes, the third transistor having a third control input as the voltage clamping control input.

11. A driver comprising: A first switch having a switch control input; A second switch coupled between the voltage supply terminal and the first switch at a switch output; A first transistor having a first control input and first and second current terminals; A resistor coupled between the voltage supply terminal and the first control input; A configurable voltage clamping circuit having a voltage clamping control input and a voltage clamping circuit output, the voltage clamping circuit output being coupled to the first control input; A second transistor having a second control input and third and fourth current terminals, the second control input being coupled to the second current terminal, and the third current terminal being coupled to the voltage supply terminal; and A logic circuit comprising a monostable circuit, the logic circuit being coupled to the voltage supply terminal, the switch control input, and the voltage clamping control input, the logic circuit being configured to configure the configurable voltage clamping circuit for a first clamping voltage at the voltage clamping circuit output in response to the first switch being turned on, and to configure the configurable voltage clamping circuit for a second clamping voltage at the voltage clamping circuit output in response to the voltage at the switch output reaching a threshold associated with the voltage at the voltage supply terminal.

12. The driver according to claim 11, wherein the logic circuit is configured to configure the voltage clamping circuit for the first clamping voltage for a period of time at least based on the pulse duration of a pulse generated by the monostable circuit in response to the first switch being turned on.

13. The driver according to claim 11, wherein the first clamping voltage is less than the second clamping voltage.

14. The driver according to claim 11, wherein the logic circuit includes a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being coupled to the voltage supply terminal, and the second comparator input being coupled to the switch output.

15. The driver according to claim 14, wherein the first switch has a switch control input, and the logic circuit includes a logic gate having first and second logic gate inputs and a logic gate output, the first logic gate input being coupled to the comparator output, and the one-shot circuit being coupled between the switch control input and the second logic gate input.

16. The driver according to claim 1, wherein the configurable voltage clamp circuit includes: A first Zener diode; A second Zener diode serially coupled with the first Zener diode between the first control input and the ground terminal; And A third transistor coupled across the second Zener diode, the third transistor having a control input as the voltage clamp control input.

17. A driver comprising: A first switch; A second switch coupled between the voltage supply terminal and the first switch at a switch output; A comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being coupled to the voltage supply terminal, and the second comparator input being coupled to the switch output; A first transistor having a first control input and first and second current terminals; A resistor coupled between the voltage supply terminal and the first control input; A plurality of Zener diodes serially coupled between the first control input and the ground terminal; A second transistor having a second control input and third and fourth current terminals, the second control input being coupled to the second current terminal, and the third current terminal being coupled to the voltage supply terminal; A third transistor coupled across some but not all of the plurality of Zener diodes, the third transistor having a third control input; And A logic gate having a logic gate input and a logic gate output, the logic gate input being coupled to the comparator output, and the logic gate output being coupled to the third control input.

18. The driver according to claim 17, wherein the logic gate input is a first logic gate input and the logic gate has a second logic gate input, the first switch has a switch control input, and the driver further includes a one-shot circuit coupled between the switch control input and the second logic gate input.

19. The driver according to claim 17, wherein the logic gate is an OR gate.

20. The driver according to claim 17, wherein the resistor is a first resistor, and the driver further includes: A second resistor coupled between the second control input and the ground terminal; And A fourth transistor coupled across the second resistor.

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