Address mapping method and device and electronic equipment

Abstract

The invention relates to the technical field of data memories, and provides an address mapping method and device and electronic equipment. The address mapping method comprises the following steps: configuring an ECC protection area in a controller of the DRAM; obtaining an AXI address; calculating a to-be-protected AXI address and a non-protected AXI address in the AXI addresses according to the address range of the ECC protection area; the AXI address to be protected is subjected to address mapping by adopting a first mapping method, the non-protected AXI address is subjected to address mapping by adopting a second mapping method, and the first mapping method is different from the second mapping method. The method comprises the following steps: firstly, configuring an ECC (Error Correction Code) protection area in a DRAM (Dynamic Random Access Memory), calculating and distinguishing a to-be-protected AXI address of which the AXI address falls into the ECC protection area and a non-protected AXI address of which the AXI address falls out of the ECC protection area according to an address range of the ECC protection area, and executing different address mapping methods on the to-be-protected AXI address and the non-protected AXI address. Resource waste caused by the fact that the ECC mapping method is adopted when the AXI address does not need ECC protection is avoided, and the performance and the resource utilization rate of the DRAM are improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of data memories, and in particular, to an address mapping method, apparatus, and electronic device. Background Art

[0002] As the core storage medium of a computer system, the reliability of Dynamic Random Access Memory (DRAM) directly affects data integrity. In high-reliability scenarios such as servers and data centers, Error Correction Code (ECC) technology is generally used to detect and correct errors in DRAM storage units. With the growth of memory capacity requirements, the system only needs to enable ECC protection for some key data regions, rather than full-space protection.

[0003] The traditional ECC address mapping scheme adopts a global ECC address mapping strategy. That is, when ECC protection is enabled in the DRAM system, whether all are protected regions or only some are protected regions, the global address mapping rule is applied, and the ECC codes are centrally stored in a fixed region, so that the ECC codes and the corresponding data blocks are located in the same DRAM row (Page) to optimize the access efficiency of the ECC region.

[0004] However, when the system only needs to enable ECC protection for some regions, the traditional scheme still forcibly applies the global address mapping rule, resulting in waste of resources in non-ECC protected regions and degradation of DRAM performance. Summary of the Invention

[0005] To solve the above problems, the present application provides an address mapping method, apparatus, and electronic device, which can solve the technical problems of waste of resources in non-ECC protected regions and degradation of DRAM performance caused by the global address mapping rule.

[0006] To achieve the above object, in a first aspect, the present application provides an address mapping method, including: configuring an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where the address range of the ECC protection area is defined by a start address register and an address space register; wherein, the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of bits of the address space of the ECC protection area; obtaining a physical memory AXI address to be mapped; calculating a protected AXI address and an unprotected AXI address in the AXI address according to the address range of the ECC protection area; wherein, the protected AXI address includes the AXI addresses falling within the ECC protection area, and the unprotected AXI address includes the AXI addresses falling outside the ECC protection area; performing address mapping on the protected AXI address by using a first mapping method, and performing address mapping on the unprotected AXI address by using a second mapping method, and the first mapping method is different from the second mapping method.

[0007] The address mapping method provided by the present application first configures an ECC protection area in the DRAM controller, calculates and distinguishes a protected AXI address whose AXI address falls within the ECC protection area and an unprotected AXI address whose AXI address falls outside the ECC protection area according to the address range of the ECC protection area, and performs different address mapping methods on the protected AXI address and the unprotected AXI address, avoiding resource waste caused by using the ECC mapping method when the AXI address does not require ECC protection, and improving the DRAM performance and resource utilization rate.

[0008] In a realizable manner of the first aspect, calculating a protected AXI address and an unprotected AXI address in the AXI address according to the address range of the ECC protection area includes: performing a first unit conversion on the start address to obtain a start AXI address falling within the ECC protection area, and the unit of the start AXI address is the same as the unit of the AXI address; performing a second unit conversion on the number of bits of the address space to obtain the number of bits of the AXI address space falling within the ECC protection area; the unit of the number of bits of the AXI address space is the same as the unit of the AXI address; adding the start AXI address and the number of bits of the AXI address space to obtain an end AXI address falling within the ECC protection area; determining the AXI addresses falling within the range of the start AXI address and the end AXI address as the protected AXI address, and determining the AXI addresses falling outside the range of the start AXI address and the end AXI address as the unprotected AXI address.

[0009] In the above method, the starting address and the address space bit number of the ECC protection area configured in the DRAM controller are subjected to unit conversion, converted into the same form as the AXI address unit, and the end address is calculated according to the starting address and the address space bit number, so as to determine whether the AXI address falls into the ECC protection area, thereby distinguishing the AXI address to be protected and the non-protected AXI address, and improving the efficiency of address mapping.

[0010] In an implementable manner of the first aspect, before performing the second unit conversion on the address space bit number to obtain the AXI address space bit number falling within the ECC protection area, the address mapping method further includes: obtaining the size of the AXI address space bit number; if the size of the AXI address space bit number is 0, determining the AXI address as a non-protected AXI address.

[0011] In the above method, determining the AXI address with an address space bit number of 0 as a non-protected AXI address improves the accuracy of judgment.

[0012] In an implementable manner of the first aspect, performing address mapping on the AXI address to be protected by using the first mapping method includes: dividing the AXI address to be protected into a high-address segment AXI address and a low-address segment AXI address; wherein, the high-address segment AXI address is used to determine the position of the AXI address to be protected in the AXI address, and the low-address segment AXI address is used to determine the size of the ECC protection area; dividing the low-address segment AXI address into a first address segment AXI address and a second address segment AXI address; wherein, the first address segment AXI address is used to divide the ECC protection area into 8 sub-areas of equal size, and the second address segment AXI address is used for conventional address mapping; dividing the column address in the DRAM into a high-address segment column address and a low-address segment column address; wherein, the high-address segment column address is used to divide the ECC protection area into 8 sub-areas of equal size, and the low-address segment column address is used for conventional address mapping; mapping the first address segment AXI address to the high-address segment column address, and sequentially mapping the high-address segment AXI address and the second address segment AXI to the low-address segment column address, BANK address, row address, and RANK address; wherein, the BANK address, row address, and RANK address are all addresses in the DRAM.

[0013] In the above method, both the AXI address and the column address in the DRAM are divided into different address segments, and a part of the address segments are used to divide the ECC protection area into 8 sub-areas of the same size for realizing the separate mapping and storage of ECC, while the conventional data other than ECC is sequentially mapped, increasing the mapping efficiency and improving the performance of the DRAM.

[0014] In an implementable manner of the first aspect, the AXI address to be protected is divided into a high-address-segment AXI address and a low-address-segment AXI address, including: dividing the Nth bit to the highest bit in the AXI address to be protected into the high-address-segment AXI address; dividing the 0th bit to the (N - 1)th bit in the AXI address to be protected into the low-address-segment AXI address; where N is a positive integer, and the value of N is the same as the number of bits of the address space of the ECC protection area.

[0015] In the above method, by dividing the AXI address to be protected into a high-address-segment AXI address and a low-address-segment AXI address, the position of the AXI address to be protected in the overall AXI address can be accurately determined, avoiding the phenomenon of mapping errors.

[0016] In an implementable manner of the first aspect, the low-address-segment AXI address is divided into a first-address-segment AXI address and a second-address-segment AXI address, including: dividing the (N - 3)th bit to the (N - 1)th bit in the AXI address to be protected into the first-address-segment AXI address; dividing the 0th bit to the (N - 4)th bit in the AXI address to be protected into the second-address-segment AXI address.

[0017] In the above method, the highest 3 bits of the address in the low-address-segment AXI address are divided into the first-address-segment AXI address, and the ECC protection area is divided into 8 sub-areas according to the first-address-segment AXI address, which is used to distinguish the mapping of ECC and regular data, improving the efficiency of address mapping.

[0018] In an implementable manner of the first aspect, the column address in the DRAM is divided into a high-address-segment column address and a low-address-segment column address, including: dividing the 7th bit to the 9th bit in the column address in the DRAM into the high-address-segment column address; dividing the 0th bit to the 6th bit in the column address in the DRAM into the low-address-segment column address.

[0019] In the above method, the highest 3 bits of the column address in the DRAM are divided into the high-address-segment column address, and the ECC protection area is divided into 8 sub-areas according to the high-address-segment column address, which is used to distinguish the storage locations of ECC and regular data, improving the efficiency of address mapping.

[0020] In an implementable manner of the first aspect, the address mapping method further includes: obtaining the bit value of the high-address-segment column address; when the bit value of the high-address-segment column address is 111, the sub-area is used to store ECC; otherwise, the sub-area is used to store regular data.

[0021] In the above method, the sub-region for storing ECC and the sub-region for storing regular data can be distinguished according to the bit values of the column addresses in the high address segment, improving the efficiency and accuracy of ECC mapping.

[0022] In an implementable manner of the first aspect, address mapping is performed on the non-protected AXI address by using a second mapping method, including: sequentially mapping the non-protected AXI address to the column address, BANK address, row address, and RANK address in the DRAM.

[0023] In the above method, when mapping the non-protected AXI address, it is not necessary to distinguish between ECC and regular data. Therefore, the mapping efficiency can be improved by the sequential mapping method, enhancing the performance of the DRAM.

[0024] In a second aspect, the present application further provides an address mapping device, including: a protection area configuration module configured to configure an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where the address range of the ECC protection area is defined by a start address register and an address space register; among them, the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of bits of the address space of the ECC protection area; an AXI address acquisition module configured to acquire a physical memory AXI address to be mapped; an AXI address division module configured to calculate a to-be-protected AXI address and a non-protected AXI address in the AXI address according to the address range of the ECC protection area; where the to-be-protected AXI address includes the AXI addresses falling within the ECC protection area, and the non-protected AXI address includes the AXI addresses falling outside the ECC protection area; an address mapping module configured to perform address mapping on the to-be-protected AXI address by using a first mapping method, and perform address mapping on the non-protected AXI address by using a second mapping method, and the first mapping method is different from the second mapping method.

[0025] In a third aspect, the present application further provides an electronic device, characterized by including: one or more processors; a memory configured to store one or more programs; where when the one or more programs are executed by the one or more processors, the one or more processors implement the address mapping method in the first aspect and any of its optional implementation manners.

[0026] It can be understood that for the beneficial effects that can be achieved by the technical solutions provided in the second aspect and the third aspect above, reference can be made to the beneficial effects in the first aspect and any of its optional implementation manners, which will not be elaborated here.

[0027] As can be seen from the above technical solutions, the present application provides an address mapping method, apparatus, and electronic device. The address mapping method includes: configuring an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where the address range of the ECC protection area is defined by a start address register and an address space register; wherein, the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of bits of the address space of the ECC protection area; obtaining the physical memory AXI address to be mapped; calculating the protected AXI address and the unprotected AXI address in the AXI address according to the address range of the ECC protection area; wherein, the protected AXI address includes the AXI addresses falling within the ECC protection area, and the unprotected AXI address includes the AXI addresses falling outside the ECC protection area; performing address mapping on the protected AXI address by using a first mapping method, and performing address mapping on the unprotected AXI address by using a second mapping method, where the first mapping method is different from the second mapping method.

[0028] The address mapping method provided by the present application first configures an ECC protection area in the DRAM controller, calculates and distinguishes the protected AXI addresses whose AXI addresses fall within the ECC protection area and the unprotected AXI addresses falling outside the ECC protection area through the address range of the ECC protection area, and performs different address mapping methods on the protected AXI addresses and the unprotected AXI addresses, avoiding resource waste caused by using the ECC mapping method when the AXI address does not require ECC protection, and improving the performance and resource utilization rate of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0030] Figure 1 FIG. is a schematic flowchart of an address mapping method provided by an embodiment of the present application;

[0031] Figure 2 FIG. is a schematic diagram of the allocation of the ECC protection area in the DRAM controller provided by an embodiment of the present application;

[0032] Figure 3 FIG. is a schematic diagram of a calculation method for protected AXI addresses and unprotected AXI addresses provided by an embodiment of the present application;

[0033] Figure 4 FIG. is a schematic diagram of continuously accessing the same row provided by an embodiment of the present application;

[0034] Figure 5Schematic diagram of data storage in an ECC protection area provided by an embodiment of the present application;

[0035] Figure 6 Schematic diagram of single - access line - feed provided by an embodiment of the present application;

[0036] Figure 7 Schematic diagram of a first mapping method for an AXI address to be protected provided by an embodiment of the present application;

[0037] Figure 8 Schematic diagram of an address mapping device provided by an embodiment of the present application;

[0038] Figure 9 Schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0039] The embodiments will be described in detail below, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application detailed in the claims.

[0040] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the following described implementation manners, rather than intending to limit the implementation manners of the present application. Unless otherwise specified, these terms should be understood in their ordinary and common meanings.

[0041] The terms "first", "second", "third", etc. in the specification, claims and the above - mentioned drawings of the present application are used to distinguish similar or homogeneous objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that such terms can be interchanged under appropriate circumstances.

[0042] For the convenience of understanding the solution, the following explains relevant terms:

[0043] Dynamic Random Access Memory (DRAM): A volatile semiconductor memory, which consists of transistors and capacitors to form basic storage units, and represents binary data (0 or 1) through the charging and discharging of capacitors. Its core function is to serve as the main memory (RAM) of a computer, temporarily storing programs and data required for the operation of the processor, supporting high - speed reading and writing to ensure the smooth operation of the system. It is widely used in devices such as computers and mobile phones, undertaking the task of quickly accessing data during system operation.

[0044] Error Correction Code (ECC): A technology used to detect and correct data errors, commonly found in memory (such as ECC DRAM) and storage systems. Its core function is to use redundant check algorithms to detect and correct single-bit errors caused by electromagnetic interference, cosmic rays, etc. during data transmission or storage in real time, and at the same time detect multi-bit errors, thereby preventing system crashes, data corruption, or program anomalies.

[0045] Address mapping: The process of converting a system address (such as an AXI address) into an address within DRAM (such as row and column addresses within a DRAM chip), ensuring that data is accurately stored in the specified storage unit. In DRAM, address mapping resolves the address requested by the CPU into specific rows and columns by the controller to access the data stored in the capacitors.

[0046] DRAM can be used as the core storage medium of an electronic device. To enable the electronic device to access DRAM efficiently, the AXI address needs to be mapped to DRAM. DRAM includes column addresses, row addresses, BANK addresses, and RANK addresses. The conventional address mapping method can sequentially map the AXI address to the column address, row address, BANK address, and RANK address. To improve the reliability of data, ECC technology needs to be applied to detect and correct errors in DRAM storage units during address mapping. At this time, the ECC address mapping method needs to be adopted for address mapping: A separate storage space for storing ECC is set up in DRAM.

[0047] Due to the characteristics of DRAM's capacitor for storing data and the specific form of the DRAM circuit, the circuit access steps of DRAM are: idle > row activation > read data (1 or multiple bursts) > precharge > idle. For access to the same BANK, if the data to be accessed belongs to the same row, subsequent accesses can avoid reactivating and precharging this BANK again. Only one row activation is required before the first access, and one precharge is required after the last access.

[0048] However, since during address mapping with ECC data, every 7 parts of regular data correspond to 1 part of ECC data. Therefore, a new row needs to be accessed each time, resulting in the performance of the ECC mapping method being lower than that of the conventional address mapping method.

[0049] Traditional address mapping schemes applicable to ECC adopt a global ECC address mapping method. That is, when ECC protection is enabled in a DRAM system, regardless of whether the entire memory area or only a part of the memory area is protected, the ECC address mapping method will be applied. When the system only needs to enable ECC protection for some areas, for the memory areas that do not require ECC protection, the ECC address mapping method will still be forcibly applied, resulting in waste of resources in the non-ECC protected areas, thereby increasing access latency and reducing the overall performance of the DRAM.

[0050] To solve the above problems, embodiments of the present application provide an address mapping method, apparatus, and electronic device. By setting the address range of the ECC protection area in the DRAM controller, distinguishing between the AXI addresses to be protected and the non-protected AXI addresses in the AXI address, and adopting different address mapping methods for the AXI addresses to be protected and the non-protected AXI addresses, the non-protected AXI addresses adopt an address mapping method with higher resource utilization rate, improving the address mapping efficiency and the performance of the DRAM.

[0051] Next, the specific implementation manner of the address mapping method will be introduced. The execution subject of this method can be an electronic device.

[0052] Figure 1 It is a schematic flowchart of an address mapping method provided by an embodiment of the present application. As Figure 1 shown, the address mapping method includes steps S100 - S400.

[0053] S100: Configure an ECC protection area in the DRAM controller. The address range of the ECC protection area is defined by a start address register and an address space register.

[0054] In some embodiments, the address range of the ECC protection area is jointly determined by the start address and the number of address space bits. Therefore, two sets of registers are required to set the address range of the ECC protection area, namely the start address register and the address space register. Among them, the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of address space bits of the ECC protection area.

[0055] It should be understood that based on the need to protect some memory in the DRAM, multiple different ECC protection areas can be configured segmentally in the DRAM controller. That is, the start address register can store the start addresses of multiple segments of ECC protection areas, and the address space register can store the number of address space bits of multiple segments of ECC protection areas. Moreover, each start address corresponds to the number of address space bits, indicating the address range of each ECC protection area.

[0056] Exemplarily, two ECC protection areas are configured in the DRAM controller.Figure 2 Schematic diagram of ECC protection area configuration in a DRAM controller provided by an embodiment of the present application. As Figure 2 shown, the DRAM is divided into 4 regions, where regions 0, 2, and 4 are non-ECC protected regions, and regions 1 and 3 are ECC protected regions. The specific configuration information of the start address register and the address space register for defining the address ranges of regions 1 and 3 is shown in Table 1.

[0057] Table 1

[0058]

[0059]

[0060] Among them, "DDRMC_CFG34" is the address space register with a bit width of 32 bits. "rf_block_space0" is the address space bit number field of region 0, and the corresponding bit positions are [11:6]. "rf_block_space1" is the address space bit number field of region 3, and the corresponding bit positions are [23:18]. "DDRMC_CFG34" is the start address register with a bit width of 32 bits. "rf_block_addr_start0" is the start address field of region 0, and the corresponding bit positions are [15:0]. "rf_block_addr_start1" is the start address field of region 3, and the corresponding bit positions are [31:16].

[0061] In some embodiments, the number of address space bits stored in the address space bit number register can be expressed as 1 << rf_block_space*, where << represents the left shift operator, and rf_block_space* represents the number of bits to be shifted. To satisfy the different storage capabilities of each region of the DRAM, the sizes of the address space bits of different regions can be different.

[0062] Exemplarily, if it is necessary to configure the size of the address space bits of region 0 to 1GB, 1GB = 2 30 Byte, that is, set rf_block_space0 to 1 << 30.

[0063] Another exemplarily, if it is necessary to configure the size of the address space bits of region 3 to 1MB, 1MB = 2 30 Byte, that is, set rf_block_space1 to 1 << 20.

[0064] S200: Obtain the AXI address to be mapped.

[0065] In some embodiments, to perform mapping on the AXI address, it is first necessary to obtain the AXI address to be mapped. When obtaining the AXI address to be mapped, to ensure that the AXI address is mapped to the corresponding position in the DRAM, it is necessary to first remove the low - order address in the AXI address according to the DRAM_DATA_WIDTH bit width in the DRAM.

[0066] Exemplarily, if the DRAM bit width is 16 bit, the AXI address to be mapped is determined as [15:1]; if the DRAM bit width is 32 bit, the AXI address to be mapped is determined as [33:2].

[0067] S300: Calculate the AXI addresses to be protected and non - protected in the AXI address according to the address range of the ECC protection area.

[0068] In some embodiments, to distinguish the addresses in the AXI address that need to be protected by ECC and the addresses that do not need to be protected by ECC, that is, the AXI addresses to be protected and non - protected AXI addresses, and then perform different mapping methods on the two AXI addresses to reduce resource waste, it is necessary to calculate the AXI addresses to be protected that fall within the ECC protection area and the non - protected AXI addresses that fall outside the ECC protection area according to the address range of the ECC protection area configured in step S100.

[0069] Figure 3 This is a schematic diagram of a calculation method for the AXI addresses to be protected and non - protected provided by the embodiments of the present application.

[0070] As Figure 3 shown, calculating the AXI addresses to be protected and non - protected in the AXI address according to the address range of the ECC protection area includes the following steps:

[0071] S301: Perform a first unit conversion on the starting address to obtain the starting AXI address that falls within the ECC protection area.

[0072] In some embodiments, the unit of the starting address stored in the starting address register and the unit of the AXI address to be mapped may be different. Therefore, to achieve the address mapping from AXI to DRAM, it is first necessary to make the unit of the starting address consistent with the unit of the AXI address to be mapped. Therefore, a first unit conversion is performed on the starting address in the starting address register to convert the starting address into a starting AXI address.

[0073] Exemplarily, the unit of the starting address stored in the starting address register is MB, while the unit of the AXI address is Byte. Therefore, a first unit conversion is performed on the starting address. By the conversion method of 1MB = 2 20 Byte, the MB is converted to Byte.

[0074] S302: Perform a second unit conversion on the number of bits of the address space to obtain the number of bits of the AXI address space that falls within the ECC protection region.

[0075] In some embodiments, similar to the principle of the above starting address, the units of the number of bits of the address space stored in the address space register and the unit of the AXI address to be mapped may also be different. Therefore, perform a second unit conversion on the number of bits of the address space in the address space register to convert the number of bits of the address space into the number of bits of the AXI address space.

[0076] Exemplarily, the unit of the number of bits of the address space stored in the address space register is bit, while the unit of the AXI address is Byte. Therefore, perform a second unit conversion on the starting address, and the number of bits shifted left by the number of bits of the address space to convert bit to Byte.

[0077] In some embodiments, when performing a second unit conversion on the number of bits of the address space, to avoid the situation where the number of bits of the address space is 0, resulting in an error in the unit conversion, before performing a second unit conversion on the number of bits of the address space, it is necessary to determine the size of the AXI address space bits. If the size of the AXI address space bits is 0, it means that there is no AXI address to be protected in this region, and the AXI address can be directly determined as a non-protected AXI address without further performing a second unit conversion.

[0078] S303: Add the starting AXI address and the number of bits of the AXI address space to obtain the ending AXI address that falls within the ECC protection region.

[0079] In some embodiments, since the AXI address to be protected is an address range, this range can be determined based on the starting address and the ending address. Therefore, after obtaining the starting AXI address and the number of bits of the AXI address space that fall within the ECC protection region, add the two to obtain the ending AXI address that falls within the ECC protection region, and then it is possible to determine whether the AXI address falls within the ECC protection region based on the starting AXI address and the ending AXI address.

[0080] Specifically, determine whether the AXI address is greater than the starting AXI address and less than the ending AXI address. If the AXI address is greater than the starting AXI address and less than the ending AXI address, then the AXI address falls within the range of the starting AXI address and the ending AXI address; otherwise, the AXI address falls outside the range of the starting AXI address and the ending AXI address.

[0081] If the AXI address falls within the range of the starting AXI address and the ending AXI address, perform step S3041: Determine the AXI address as the AXI address to be protected.

[0082] Exemplarily, if the start address field "rf_block_addr_start0" in the start address register and the address space bit number field "rf_block_space0" in the address space register jointly determine an ECC protection area. The start address stored in the "rf_block_addr_start0" field and the address space bit number stored in the "rf_block_space0" field are respectively subjected to the first unit conversion and the second unit conversion to obtain the first start AXI address and the first AXI address space bit number, and then the first start AXI address and the first AXI address space bit number are added to obtain the first end AXI address. If the AXI address of area 1 falls within the range of the first start AXI address and the first end AXI address, the AXI address of area 1 is determined as the AXI address to be protected.

[0083] Otherwise, execute step S3042: Determine the AXI address as a non-protected AXI address.

[0084] Exemplarily, as shown in Table 1, if there are two start address fields "rf_block_addr_start0" and "rf_block_addr_start1" in the start address register in the current DRAM controller for determining the start address of the ECC protection area, correspondingly, there are two address space bit number fields "rf_block_space0" and "rf_block_space1" in the address space register for determining the address space bit number of the ECC protection area, indicating that two ECC protection areas are configured in the DRAM controller. According to the above method, the first AXI start address, the first AXI end address, the second AXI start address, and the second AXI end address can be calculated from the data stored in the four fields of "rf_block_addr_start0", "rf_block_addr_start1", "rf_block_space0", and "rf_block_space1". If the AXI address of area 2 neither falls within the address range of the first AXI start address and the first AXI end address nor falls within the address range of the second AXI start address and the second AXI end address, the AXI address of area 2 is determined as a non-protected AXI address.

[0085] S400: Perform address mapping on the AXI address to be protected using the first mapping method, and perform address mapping on the non-protected AXI address using the second mapping method, where the first mapping method is different from the second mapping method.

[0086] In some embodiments, due to the characteristics of the DRAM capacitor for storing data and the specific form of the DRAM circuit, for access to the same BANK, if the data to be accessed belongs to the same row, subsequent accesses can avoid re-performing row activation and pre-charging on this BANK. Only one row activation needs to be performed before the first access, and one pre-charging needs to be performed after the last access. Figure 4 FIG. is a schematic diagram of continuous access to the same row provided by an embodiment of the present application.

[0087] However, for areas that require ECC protection, during address mapping, regular data and ECC data need to be separated. In the DRAM, the ECC data is stored in the upper 1 / 8 bits of this area, and the regular data is stored in the lower 7 / 8 bits of this area. Figure 5 FIG. is a schematic diagram of data storage in an ECC protection area provided by an embodiment of the present application.

[0088] To achieve this purpose, for address mapping of the ECC protection area, line wrapping needs to be performed during each access. Figure 6 FIG. is a schematic diagram of single access line wrapping provided by an embodiment of the present application. This access method increases the number of row activations and pre-charges, making the mapping performance of the ECC protection area lower than that of ordinary address mapping. Therefore, if the ECC address mapping method is used for both the protected AXI address and the non-protected AXI address, it increases the resource waste during address mapping of the non-protected AXI address and reduces the performance of the DRAM.

[0089] In some embodiments, to improve the performance of the DRAM and reduce resource waste, the ECC address mapping method (the first mapping method) can be used to perform address mapping on the protected AXI address, while the conventional address mapping method (the second mapping method) can be used to perform address mapping on the non-protected AXI address.

[0090] Figure 7 FIG. is a schematic diagram of performing the first mapping method on the protected AXI address provided by an embodiment of the present application.

[0091] As Figure 7 shown, performing address mapping on the protected AXI address using the first mapping method includes the following steps:

[0092] S701: Divide the protected AXI address into a high-address segment AXI address and a low-address segment AXI address.

[0093] In some embodiments, to determine the specific position of the AXI address to be protected in the entire AXI address area and the size of the ECC protection area corresponding to the AXI address to be protected. First, the AXI address to be protected is divided into a high-address segment AXI address for determining the position of the AXI address to be protected and a low-address segment AXI address for determining the size of the ECC protection area.

[0094] Specifically, the Nth bit to the highest bit in the AXI address to be protected are divided into the high-address segment AXI address; the 0th bit to the (N - 1)th bit in the AXI address to be protected are divided into the low-address segment AXI address; where N is a positive integer, and the value of N is the same as the number of bits of the address space of the ECC protection area.

[0095] Exemplarily, assume that the number of bits of the AXI address to be protected is 34 bits, and the highest bit is 33. If the size of the "rf_block_space0" field in the address space register is 20, then N = 20, and [33:20] is divided into the high-address segment AXI address; [19:0] is divided into the low-address segment AXI address.

[0096] S702: Divide the low-address segment AXI address into a first address segment AXI address and a second address segment AXI address.

[0097] In some embodiments, since the address mapping including ECC needs to store ECC data and regular data separately, that is, the upper 1 / 8 stores ECC data and the lower 7 / 8 stores regular data, it is necessary to divide the low-address segment AXI address into a first address segment and a first address segment. The first address segment is used to divide the ECC protection area into 8 sub-areas of equal size and map the ECC data to the upper 1 / 8 sub-areas, while the second address segment AXI address is used for regular address mapping.

[0098] Specifically, the (N - 3)th bit to the (N - 1)th bit in the AXI address to be protected are divided into the first address segment AXI address; the 0th bit to the (N - 4)th bit in the AXI address to be protected are divided into the second address segment AXI address.

[0099] Exemplarily, assume that the number of bits of the AXI address to be protected is 34 bits, and the highest bit is 33. If the size of the "rf_block_space0" field in the address space register is 20, then N = 20, and [19:0] is the low-address segment AXI address divided in step S701. In the low-address segment of [19:0], [19:17] is divided into the first address segment AXI address, and [16:0] is divided into the second address segment AXI address.

[0100] In some embodiments, since the ECC data is stored in the highest sub-region among the 8 sub-regions, the first address segment AXI address determines the data type stored in the 8 sub-regions according to the magnitude of the bit values.

[0101] Specifically, when the bit value of [19:17] is 111, which is converted to decimal as 7, it is used to store ECC data;

[0102] When the bit value of [19:17] is 000, which is converted to decimal as 0, it is used to store normal data;

[0103] When the bit value of [19:17] is 001, which is converted to decimal as 1, it is used to store normal data;

[0104] When the bit value of [19:17] is 010, which is converted to decimal as 2, it is used to store normal data;

[0105] When the bit value of [19:17] is 011, which is converted to decimal as 3, it is used to store normal data;

[0106] When the bit value of [19:17] is 100, which is converted to decimal as 4, it is used to store normal data;

[0107] When the bit value of [19:17] is 101, which is converted to decimal as 5, it is used to store normal data;

[0108] When the bit value of [19:17] is 110, which is converted to decimal as 6, it is used to store normal data.

[0109] S703: Divide the column address in the DRAM into a high-address segment column address and a low-address segment column address.

[0110] In some embodiments, to achieve a one-to-one correspondence of address mapping, corresponding to the AXI address to be protected, 8 sub-regions also need to be divided in the DRAM. The highest sub-region is used to store ECC data, and the remaining 7 regions are used to store normal data. The column address in the DRAM can be divided into a high-address segment column address and a low-address segment column address. The high-address segment column address is used to split the ECC protection region into 8 equal-sized sub-regions and distinguish the region for storing ECC data and the region for storing normal data, and the low-address segment column address is used for normal address mapping.

[0111] Specifically, the 7th bit to the 9th bit in the column address of the DRAM are divided into the high-address segment column address; the 0th bit to the 6th bit in the column address of the DRAM are divided into the low-address segment column address.

[0112] Exemplarily, c* represents the bit positions of the column address in DRAM, that is, [c9:c7] is divided into the column address of the high address segment, and [c6:c0] is divided into the column address of the low address segment.

[0113] The method for determining the data types stored in 8 sub-regions according to the magnitude of the bit values of the column address of the high address segment in DRAM is the same as that of the AXI address of the first address segment: when the bit value is 111, it is used to store ECC data; when the bit value is other values, it is used to store regular data, which will not be elaborated here.

[0114] S704: Map the AXI address of the first address segment to the column address of the high address segment, and map the AXI address of the high address segment and the AXI of the second address segment sequentially to the column address of the low address segment, BANK address, row address, and RANK address in DRAM; where the BANK address, row address, and RANK address are all addresses in DRAM.

[0115] In some embodiments, after respectively determining the storage area of the AXI address to be protected and the ECC data in DRAM, map the ECC data correspondingly, that is, map the AXI address of the first address segment to the column address of the high address segment. For regular data, the AXI address is linear and continuous. Therefore, for other AXI addresses to be protected, use the sequential mapping method, that is, map the AXI address of the high address segment and the AXI of the second address segment sequentially to the column address of the low address segment, BANK address, row address, and RANK address in DRAM.

[0116] It should be noted that during the address mapping process from the AXI address to the DRAM address, the low address bits in the AXI address will be removed according to the data bit width of DRAM. For example, if the data bit width of the AXI address is 34bit and the data bit width of DRAM is 32bit, the lowest 2 bits [1:0] of the AXI address will not perform address mapping.

[0117] Table 2 shows the complete address mapping process from the AXI address to be protected to the ECC address in DRAM, taking the data bit width of the AXI address to be protected as 34bit, the data bit width of DRAM as 32bit, and the data size stored in the "rf_block_space0" field of the ECC protection area as 20 as an example.

[0118] Table 2

[0119] 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cs0 r17 r16 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 c9 c8 c7

[0120] Table 2 (continued)

[0121]

[0122]

[0123] Among them, c* represents the column address, b* represents the BANK address, r* represents the row address, and cs* represents the RANK address.

[0124] In some embodiments, for non-protected AXI addresses, to reduce the number of row activations and precharges and thus improve the performance of the DRAM, a second mapping method (conventional mapping method) is used to perform address mapping: simply map the non-protected AXI addresses sequentially to the column address, BANK address, row address, and RANK address in the DRAM, which will not be elaborated here.

[0125] The address mapping method in the embodiments of the present application distinguishes between protected AXI addresses and non-protected AXI addresses and uses different address mapping methods, which can reduce the resource waste phenomenon during the mapping of non-protected AXI addresses. Through performance simulation comparison, when not distinguishing between protected AXI addresses and non-protected AXI addresses and both using the ECC address mapping method for address mapping, the memory utilization rate of non-protected AXI addresses is 64.93%, while the memory utilization rate of non-protected AXI addresses in the embodiments of the present application is 77.87%, improving the performance of the DRAM during address mapping.

[0126] Some embodiments of the present application also provide an address mapping device. Figure 8 It is a schematic diagram of the address mapping device provided in the embodiments of the present application. As Figure 8 shown, the address mapping device includes: a protection area configuration module 801, configured to configure an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where the address range of the ECC protection area is defined by a start address register and an address space register; among them, the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of bits of the address space of the ECC protection area; an AXI address acquisition module 802, configured to acquire a physical memory AXI address to be mapped; an AXI address division module 803, configured to calculate a protected AXI address and a non-protected AXI address in the AXI address according to the address range of the ECC protection area; among them, the protected AXI address includes AXI addresses falling within the ECC protection area, and the non-protected AXI address includes AXI addresses falling outside the ECC protection area; an address mapping module 804, configured to perform address mapping on the protected AXI address using a first mapping method, and perform address mapping on the non-protected AXI address using a second mapping method, where the first mapping method is different from the second mapping method.

[0127] Some embodiments of the present application further provide an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the address mapping method provided by some embodiments of the present application. For example, Figure 9 is a schematic diagram of an electronic device provided by an embodiment of the present application. As Figure 9 shown, the electronic device includes a processor 901, at least one communication bus 902, a user interface 903, at least one external communication interface 904, and a memory 905. Among them, the communication bus 902 is configured to implement connection communication between these components. The user interface 903 may include a display screen, and the external communication interface 904 may include a standard wired interface and a wireless interface. A computer program is stored in the memory 905. The processor 901 is used to execute the computer program stored in the memory 905.

[0128] As can be seen from the above technical solutions, the present application provides an address mapping method, apparatus, and electronic device. The address mapping method includes: configuring an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where the address range of the ECC protection area is defined by a start address register and an address space register; where the start address register is used to store the start address of the ECC protection area, and the address space register is used to store the number of bits of the address space of the ECC protection area; obtaining a physical memory AXI address to be mapped; calculating a protected AXI address and an unprotected AXI address in the AXI address according to the address range of the ECC protection area; where the protected AXI address includes AXI addresses falling within the ECC protection area, and the unprotected AXI address includes AXI addresses falling outside the ECC protection area; performing address mapping on the protected AXI address using a first mapping method, and performing address mapping on the unprotected AXI address using a second mapping method, where the first mapping method is different from the second mapping method.

[0129] The address mapping method provided by the present application first configures an ECC protection area in the DRAM controller, calculates and distinguishes a protected AXI address whose AXI address falls within the ECC protection area and an unprotected AXI address that falls outside the ECC protection area through the address range of the ECC protection area, and performs different address mapping methods on the protected AXI address and the unprotected AXI address, avoiding wasting resources by using the ECC mapping method when the AXI address does not require ECC protection, and improving the performance and resource utilization rate of the DRAM.

[0130] For the similar parts between the embodiments provided in this application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other embodiments extended based on the solution of this application without creative efforts belong to the protection scope of this application.

Claims

1. An address mapping method, characterized in that, The method includes: Configuring an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where an address range of the ECC protection area is defined by a start address register and an address space register; wherein, the start address register is used to store a start address of the ECC protection area, and the address space register is used to store a number of bits of an address space of the ECC protection area; Obtaining a physical memory AXI address to be mapped; Calculating a protected AXI address and an unprotected AXI address in the AXI address according to the address range of the ECC protection area; wherein, the protected AXI address includes the AXI address falling within the ECC protection area, and the unprotected AXI address includes the AXI address falling outside the ECC protection area; Performing address mapping on the protected AXI address by using a first mapping method, and performing address mapping on the unprotected AXI address by using a second mapping method, where the first mapping method is different from the second mapping method.

2. The address mapping method according to claim 1, wherein The calculating the protected AXI address and the unprotected AXI address in the AXI address according to the address range of the ECC protection area includes: Performing a first unit conversion on the start address to obtain a start AXI address falling within the ECC protection area, where a unit of the start AXI address is the same as a unit of the AXI address; Performing a second unit conversion on the number of bits of the address space to obtain a number of bits of the AXI address space falling within the ECC protection area; the unit of the number of bits of the AXI address space is the same as the unit of the AXI address; Adding the start AXI address and the number of bits of the AXI address space to obtain an end AXI address falling within the ECC protection area; Determining the AXI address falling within a range of the start AXI address and the end AXI address as the protected AXI address, and determining the AXI address falling outside the range of the start AXI address and the end AXI address as the unprotected AXI address.

3. The address mapping method according to claim 2, wherein Before performing the second unit conversion on the number of bits of the address space to obtain the number of bits of the AXI address space falling within the ECC protection area, the method further includes: Obtaining a size of the number of bits of the AXI address space; If the size of the number of bits of the AXI address space is 0, determining the AXI address as the unprotected AXI address.

4. The address mapping method according to claim 1, wherein The performing address mapping on the protected AXI address by using the first mapping method includes: Dividing the protected AXI address into a high address segment AXI address and a low address segment AXI address; wherein, the high address segment AXI address is used to determine a position of the protected AXI address in the AXI address, and the low address segment AXI address is used to determine a size of the ECC protection area. Divide the low - address - segment AXI address into a first - segment AXI address and a second - segment AXI address; wherein, the first - segment AXI address is used to divide the ECC protection area into 8 sub - areas of equal size, and the second - segment AXI address is used for normal address mapping; Divide the column address in the DRAM into a high - address - segment column address and a low - address - segment column address; wherein, the high - address - segment column address is used to divide the ECC protection area into 8 sub - areas of equal size, and the low - address - segment column address is used for normal address mapping; Map the first - segment AXI address to the high - address - segment column address, and sequentially map the high - address - segment AXI address and the second - segment AXI address to the low - address - segment column address, BANK address, row address, and RANK address; wherein, the BANK address, the row address, and the RANK address are all addresses in the DRAM.

5. The address mapping method according to claim 4, wherein The step of dividing the to - be - protected AXI address into a high - address - segment AXI address and a low - address - segment AXI address includes: Divide the bits from the N - th bit to the highest bit in the to - be - protected AXI address into the high - address - segment AXI address; Divide the bits from the 0 - th bit to the (N - 1) - th bit in the to - be - protected AXI address into the low - address - segment AXI address; wherein, N is a positive integer, and the value of N is the same as the number of bits of the address space of the ECC protection area.

6. The address mapping method according to claim 5, wherein The step of dividing the low - address - segment AXI address into a first - segment AXI address and a second - segment AXI address includes: Divide the bits from the (N - 3) - th bit to the (N - 1) - th bit in the to - be - protected AXI address into the first - segment AXI address; Divide the bits from the 0 - th bit to the (N - 4) - th bit in the to - be - protected AXI address into the second - segment AXI address.

7. The address mapping method according to claim 4, characterized in that, The step of dividing the column address in the DRAM into a high - address - segment column address and a low - address - segment column address includes: Divide the bits from the 7 - th bit to the 9 - th bit in the column address of the DRAM into the high - address - segment column address; Divide the bits from the 0 - th bit to the 6 - th bit in the column address of the DRAM into the low - address - segment column address.

8. The address mapping method according to claim 4, wherein The method further includes: Obtain the bit value of the high - address - segment column address; When the bit value of the high - address - segment column address is 111, the sub - area is used to store ECC; otherwise, the sub - area is used to store normal data.

9. The address mapping method according to claim 1, wherein The step of performing address mapping on the non - protected AXI address using a second mapping method includes: Sequentially map the non - protected AXI address to the column address, BANK address, row address, and RANK address in the DRAM.

10. An address mapping device, characterized in that, The device includes: A protection area configuration module, configured to: configure an error correction code (ECC) protection area in a controller of a dynamic random access memory (DRAM), where an address range of the ECC protection area is defined by a start address register and an address space register; wherein, the start address register is used to store a start address of the ECC protection area, and the address space register is used to store a number of bits of an address space of the ECC protection area; An AXI address acquisition module, configured to: acquire an AXI address of a physical memory to be mapped; An AXI address division module, configured to: calculate a protected AXI address and an unprotected AXI address in the AXI address according to the address range of the ECC protection area; wherein, the protected AXI address includes the AXI address falling within the ECC protection area, and the unprotected AXI address includes the AXI address falling outside the ECC protection area; An address mapping module, configured to: perform address mapping on the protected AXI address by using a first mapping method, and perform address mapping on the unprotected AXI address by using a second mapping method, where the first mapping method is different from the second mapping method.

11. An electronic device, characterized in that, Comprising: One or more processors; A memory, configured to store one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the address mapping method according to any one of claims 1-9.

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