Lightweight serial interface and isolated serial interface conversion circuit

Abstract

The invention relates to an interface conversion circuit, in particular to a lightweight serial interface and isolated serial interface conversion circuit, which is characterized in that a long pulse conversion unit is used for respectively converting a rising edge and a falling edge of a serial interface chip selection signal CS into a long + 1 pulse and a long-1 pulse of an isolated serial interface; the short pulse conversion unit is used for respectively converting a serial interface clock signal SCK and a serial interface input data signal SDI received by the serial interface digital-to-analog conversion module PORTAPAD into a short + 1 pulse and a short-1 pulse of an isolated serial interface; the SDO conversion unit is used for converting a short + 1 pulse and a short-1 pulse of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTB ANA into a serial interface output data signal SDO; according to the technical scheme provided by the invention, the defect that the communication rate of the conversion circuit from the serial interface to the isolated serial interface is difficult to improve under the condition that the working clock frequency is relatively low can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to an interface conversion circuit, and more particularly to a conversion circuit between a lightweight serial interface and an isolated serial interface. Background Art

[0002] The serial interface adopted by the MCU is mainly a common serial interface. In order to increase the wide application of the isolated serial interface, the conversion circuit between the serial interface and the isolated serial interface is indispensable.

[0003] Currently, the communication rate of the isolated serial interface can reach up to 2 MHz at most. Therefore, the communication rate of the conversion circuit from the serial interface to the isolated serial interface also needs to be increased to 2 MHz accordingly. However, if the communication rate of the conversion circuit from the serial interface to the isolated serial interface is increased to 2 MHz, considering the two-way delay time of the twisted pair, in order to ensure the communication timing, the working clock frequency of the conversion circuit from the serial interface to the isolated serial interface needs to be increased to 200 MHz, which greatly increases the power consumption and area of the circuit. Summary of the Invention

[0004] (I) Technical Problems to be Solved

[0005] In view of the above-mentioned disadvantages existing in the prior art, the present invention provides a conversion circuit between a lightweight serial interface and an isolated serial interface, which can effectively overcome the defect that it is difficult to improve the communication rate of the conversion circuit from the serial interface to the isolated serial interface under the condition of a relatively low working clock frequency existing in the prior art.

[0006] (II) Technical Solutions

[0007] To achieve the above object, the present invention is realized through the following technical solutions:

[0008] A conversion circuit between a lightweight serial interface and an isolated serial interface includes a serial interface digital-to-analog conversion module PORTA PAD, an isolated serial interface analog-to-digital conversion module PORTB ANA, a long pulse conversion unit, a short pulse conversion unit, and an SDO conversion unit;

[0009] The long pulse conversion unit converts the rising edge and falling edge of the serial interface chip select signal CS received by the serial interface digital-to-analog conversion module PORTA PAD into a long +1 pulse and a long -1 pulse of the isolated serial interface respectively;

[0010] The short pulse conversion unit converts the serial interface clock signal SCK and the serial interface input data signal SDI received by the serial interface digital-to-analog conversion module PORTA PAD into a short +1 pulse and a short -1 pulse of the isolated serial interface respectively;

[0011] The SDO conversion unit converts the short +1 pulse and short -1 pulse of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTBANA into a serial interface output data signal SDO.

[0012] Preferably, the long pulse conversion unit includes a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, and a long pulse counting unit. The first register Reg1, the second register Reg2, the third register Reg3, and the long pulse counting unit are all connected to the clock signal CLK;

[0013] The first register Reg1 is connected to the serial interface chip select signal CS and outputs CS_R1 to the second register Reg2. The second register Reg2 outputs CS_R2 to the third register Reg3, the first inverter N1, and the second AND gate A2;

[0014] The third register Reg3 outputs CS_R3 to the first AND gate A1 and the second inverter N2. The first inverter N1 outputs CS_N1 to the first AND gate A1. The first AND gate A1 outputs CS_A1 to the first OR gate O1. The second inverter N2 outputs CS_N2 to the second AND gate A2. The second AND gate A2 outputs CS_A2 to the first OR gate O1, the fourth OR gate O4, the first selector M1, and the third OR gate O3. The first OR gate O1 outputs CS_O1 to the long pulse counting unit and the second OR gate O2;

[0015] The long pulse counting unit outputs a long pulse count value CS_CNT to the first comparator E1, the second comparator E2, and the third comparator E3. The first comparator E1 outputs CS_E1 to the second OR gate O2. The second OR gate O2 outputs CS_O2 to the second selector M2 and the third selector M3. The second comparator E2 outputs CS_E2 to the second selector M2 and the third selector M3;

[0016] The third comparator E3 outputs CS_E3 to the fourth OR gate O4. The fourth OR gate O4 outputs CS_O4 to the first clock gating G1. The first clock gating G1 is connected to the clock signal CLK and outputs the clock signal CLK to the fourth register Reg4 under the control of CS_O4. The first selector M1 is connected to 0 and 1 and outputs CS_M1 to the fourth register Reg4 under the control of CS_A2. The fourth register Reg4 outputs CS_R4 to the third OR gate O3;

[0017] The third OR gate O3 outputs CS_O3 to the second selector M2 and the third selector M3. The second selector M2 selects and outputs TXPB_CS from CS_O2 and CS_E2 under the control of CS_O3. The third selector M3 selects and outputs TXMB_CS from CS_O2 and CS_E2 under the control of CS_O3. TXPB_CS and TXMB_CS form the long +1 pulse or long -1 pulse of the isolated serial interface.

[0018] Among them, CS_A1 is the falling-edge pulse of CS_R2, CS_A2 is the rising-edge pulse of CS_R2, and CS_O1 is the edge pulse of CS_R2.

[0019] Preferably, the short pulse conversion unit includes a fifth register Reg5, a sixth register Reg6, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a short pulse counting unit. The fifth register Reg5, the sixth register Reg6, the seventh register Reg7, the ninth register Reg9, the tenth register Reg10, and the short pulse counting unit are all connected to the clock signal CLK.

[0020] The fifth register Reg5 is connected to the serial interface clock signal SCK and outputs SCK_R5 to the sixth register Reg6. The sixth register Reg6 outputs SCK_R6 to the seventh register Reg7 and the third AND gate A3. The seventh register Reg7 outputs SCK_R7 to the third inverter N3. The third inverter N3 outputs SCK_N3 to the third AND gate A3. The third AND gate A3 outputs SCK_A3 to the fourth AND gate A4, the short pulse counting unit, and the fifth OR gate O5.

[0021] The ninth register Reg9 is connected to the serial interface input data signal SDI and outputs SDI_R9 to the tenth register Reg10. The tenth register Reg10 outputs SDI_R10 to the fourth AND gate A4. The fourth AND gate A4 outputs SCK_A4 to the sixth OR gate O6, the fourth selector M4, and the seventh OR gate O7.

[0022] The short pulse counting unit outputs the short pulse count value SCK_CNT to the fourth comparator E4, the fifth comparator E5, and the sixth comparator E6. The fourth comparator E4 outputs SCK_E4 to the fifth OR gate O5. The fifth OR gate O5 outputs SCK_O5 to the fifth selector M5 and the sixth selector M6. The fifth comparator E5 outputs SCK_E5 to the fifth selector M5 and the sixth selector M6.

[0023] The sixth comparator E6 outputs SCK_E6 to the sixth OR gate O6. The sixth OR gate O6 outputs SCK_O6 to the second clock gating G2. The second clock gating G2 receives the clock signal CLK and outputs the clock signal CLK to the eighth register Reg8 under the control of SCK_O6. The fourth selector M4 receives 0 and 1 and outputs SCK_M4 to the eighth register Reg8 under the control of SCK_A4. The eighth register Reg8 outputs SCK_R8 to the seventh OR gate O7;

[0024] The seventh OR gate O7 outputs SCK_O7 to the fifth selector M5 and the sixth selector M6. The fifth selector M5 selects and outputs TXPB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. The sixth selector M6 selects and outputs TXMB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. The TXPB_SCK and TXMB_SCK form the short +1 pulse or short -1 pulse of the isolated serial interface;

[0025] Among them, SCK_A3 is the rising edge pulse of SCK_R6.

[0026] Preferably, in the short pulse conversion unit, when the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at the high level, it is converted into the short +1 pulse of the isolated serial interface;

[0027] When the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at the low level, it is converted into the short -1 pulse of the isolated serial interface.

[0028] Preferably, the SDO conversion unit includes the eleventh register Reg11, the twelfth register Reg12, the thirteenth register Reg13, the fourteenth register Reg14, and the fifteenth register Reg15. The eleventh register Reg11, the twelfth register Reg12, and the thirteenth register Reg13 all receive the clock signal CLK;

[0029] The eleventh register Reg11 receives the serial interface clock signal SCK and outputs SCK_R11 to the twelfth register Reg12. The twelfth register Reg12 outputs SCK_R12 to the thirteenth register Reg13 and the fourth inverter N4. The thirteenth register Reg13 outputs SCK_R13 to the fifth AND gate A5. The fourth inverter N4 outputs SCK_N4 to the fifth AND gate A5. The fifth AND gate A5 outputs SCK_A5 as the reset signal to the fourteenth register Reg14 and the fifteenth register Reg15;

[0030] The fourteenth register Reg14 accesses the isolation serial interface pulse signal RXMB_L and outputs SDO_R14 to the fifteenth register Reg15;

[0031] The fifteenth register Reg15 accesses the isolation serial interface pulse signal RXPB_L and outputs SDO_R15 to the fifth inverter N5, and the fifth inverter N5 outputs the serial interface output data signal SDO;

[0032] Wherein, SCK_A5 is the falling edge pulse of SCK_R12, and the isolation serial interface pulse signal RXMB_L and the isolation serial interface pulse signal RXPB_L form a short +1 pulse or a short -1 pulse of the isolation serial interface received by the isolation serial interface analog-to-digital conversion module PORTBANA.

[0033] Preferably, in the SDO conversion unit, when the isolation serial interface analog-to-digital conversion module PORTB ANA receives the short +1 pulse of the isolation serial interface, the serial interface output data signal SDO is at a high level;

[0034] When the isolation serial interface analog-to-digital conversion module PORTBANA receives the short -1 pulse of the isolation serial interface, the serial interface output data signal SDO is at a low level.

[0035] (III) Advantageous Effects

[0036] Compared with the prior art, a lightweight serial interface and isolation serial interface conversion circuit provided by the present invention can support a communication rate of 2 MHz, and can reduce the operating clock frequency of the serial interface and isolation serial interface conversion circuit to 40 MHz, greatly reducing the power consumption and area of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0038] Figure 1 It is a system schematic diagram of the present invention;

[0039] Figure 2 It is a circuit schematic diagram of the long pulse conversion unit in the present invention;

[0040] Figure 3 It is a circuit schematic diagram of the short pulse conversion unit in the present invention;

[0041] Figure 4 This is the circuit schematic diagram of the SDO conversion unit in the present invention. Specific Embodiments

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0043] A lightweight serial interface and isolated serial interface conversion circuit, as Figure 1 shown, includes a serial interface digital-to-analog conversion module PORTAPAD, an isolated serial interface analog-to-digital conversion module PORTB ANA, a long pulse conversion unit, a short pulse conversion unit, and an SDO conversion unit;

[0044] The long pulse conversion unit converts the rising edge and falling edge of the serial interface chip select signal CS received by the serial interface digital-to-analog conversion module PORTAPAD into long +1 pulses and long -1 pulses of the isolated serial interface respectively;

[0045] The short pulse conversion unit converts the serial interface clock signal SCK and the serial interface input data signal SDI received by the serial interface digital-to-analog conversion module PORTAPAD into short +1 pulses and short -1 pulses of the isolated serial interface respectively;

[0046] The SDO conversion unit converts the short +1 pulses and short -1 pulses of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTBANA into a serial interface output data signal SDO.

[0047] As Figure 2 shown, the long pulse conversion unit includes a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, and a long pulse counting unit. The first register Reg1, the second register Reg2, the third register Reg3, and the long pulse counting unit are all connected to a clock signal CLK (in the technical solution of this application, the frequency of the clock signal CLK is 40 MHz);

[0048] The first register Reg1 is connected to the serial interface chip select signal CS and outputs CS_R1 to the second register Reg2, and the second register Reg2 outputs CS_R2 to the third register Reg3, the first inverter N1, and the second AND gate A2;

[0049] The third register Reg3 outputs CS_R3 to the first AND gate A1 and the second inverter N2. The first inverter N1 outputs CS_N1 to the first AND gate A1. The first AND gate A1 outputs CS_A1 to the first OR gate O1. The second inverter N2 outputs CS_N2 to the second AND gate A2. The second AND gate A2 outputs CS_A2 to the first OR gate O1, the fourth OR gate O4, the first selector M1, and the third OR gate O3. The first OR gate O1 outputs CS_O1 to the long pulse counting unit and the second OR gate O2;

[0050] The long pulse counting unit outputs the long pulse count value CS_CNT to the first comparator E1, the second comparator E2, and the third comparator E3. The first comparator E1 outputs CS_E1 to the second OR gate O2. The second OR gate O2 outputs CS_O2 to the second selector M2 and the third selector M3. The second comparator E2 outputs CS_E2 to the second selector M2 and the third selector M3;

[0051] The third comparator E3 outputs CS_E3 to the fourth OR gate O4. The fourth OR gate O4 outputs CS_O4 to the first clock gating G1. The first clock gating G1 accesses the clock signal CLK and outputs the clock signal CLK to the fourth register Reg4 under the control of CS_O4. The first selector M1 accesses 0 and 1 and outputs CS_M1 to the fourth register Reg4 under the control of CS_A2. The fourth register Reg4 outputs CS_R4 to the third OR gate O3;

[0052] The third OR gate O3 outputs CS_O3 to the second selector M2 and the third selector M3. The second selector M2 selects and outputs TXPB_CS from CS_O2 and CS_E2 under the control of CS_O3. The third selector M3 selects and outputs TXMB_CS from CS_O2 and CS_E2 under the control of CS_O3. TXPB_CS and TXMB_CS form the long +1 pulse or long -1 pulse of the isolated serial interface;

[0053] Among them, CS_A1 is the falling edge pulse of CS_R2, CS_A2 is the rising edge pulse of CS_R2, and CS_O1 is the edge pulse of CS_R2.

[0054] In the technical solution of this application, the working principle of the long pulse conversion unit is as follows:

[0055] The serial interface chip select signal CS is synchronously generated as CS_R2 through two - stage registers Reg1 and Reg2. CS_R2 generates CS_R3 through one - stage register Reg3. CS_R2 generates CS_N1 through inverter N1. CS_N1 and CS_R3 generate CS_A1 through AND gate A1. CS_A1 is the falling edge pulse of CS_R2;

[0056] CS_R3 passes through inverter N2 to generate CS_N2. CS_N2 and CS_R2 pass through AND gate A2 to generate CS_A2. CS_A2 is the rising-edge pulse of CS_R2.

[0057] CS_A1 and CS_A2 pass through OR gate O1 to generate CS_O1. CS_O1 is the edge pulse of CS_R2.

[0058] The long-pulse counting unit is a counter for long pulses. When CS_O1 is 1, the long-pulse counting unit starts counting. When the long-pulse count value CS_CNT reaches 11, the count value is reset to 0. The long-pulse count value CS_CNT passes through comparator E1. When the long-pulse count value CS_CNT is greater than or equal to 1 and less than or equal to 5, the output CS_E1 of comparator E1 is 1. CS_E1 and CS_O1 pass through OR gate O2 to generate CS_O2.

[0059] The long-pulse count value CS_CNT passes through comparator E2. When the long-pulse count value CS_CNT is greater than or equal to 6 and less than or equal to 11, the output CS_E2 of comparator E2 is 1.

[0060] The long-pulse count value CS_CNT passes through comparator E3. When the long-pulse count value CS_CNT is 11, the output CS_E3 of comparator E3 is 1. CS_E3 and CS_A2 pass through OR gate O4 to generate CS_O4. CS_O4 is the enable signal of clock gating G1. When CS_O4 is 1, the clock signal CLK is sent to register Reg4 through clock gating G1. When CS_A2 is 1, the output CS_M1 of selector M1 is 1, and the output CS_R4 of register Reg4 is 1. When CS_A2 is 0, the output CS_M1 of selector M1 is 0, and the output CS_R4 of register Reg4 is 0.

[0061] CS_R4 and CS_A2 pass through OR gate O3 to generate CS_O3. When CS_O3 is 1, selector M2 outputs TXPB_CS as CS_O2, and selector M3 outputs TXMB_CS as CS_E2. TXPB_CS and TXMB_CS form the long +1 pulse of the isolated serial interface. When CS_O3 is 0, selector M2 outputs TXPB_CS as CS_E2, and selector M3 outputs TXMB_CS as CS_O2. TXPB_CS and TXMB_CS form the long -1 pulse of the isolated serial interface.

[0062] As Figure 3As shown, the short pulse conversion unit includes a fifth register Reg5, a sixth register Reg6, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a short pulse counting unit. The fifth register Reg5, the sixth register Reg6, the seventh register Reg7, the ninth register Reg9, the tenth register Reg10, and the short pulse counting unit are all connected to the clock signal CLK;

[0063] The fifth register Reg5 is connected to the serial interface clock signal SCK and outputs SCK_R5 to the sixth register Reg6. The sixth register Reg6 outputs SCK_R6 to the seventh register Reg7 and the third AND gate A3. The seventh register Reg7 outputs SCK_R7 to the third inverter N3. The third inverter N3 outputs SCK_N3 to the third AND gate A3. The third AND gate A3 outputs SCK_A3 to the fourth AND gate A4, the short pulse counting unit, and the fifth OR gate O5;

[0064] The ninth register Reg9 is connected to the serial interface input data signal SDI and outputs SDI_R9 to the tenth register Reg10. The tenth register Reg10 outputs SDI_R10 to the fourth AND gate A4. The fourth AND gate A4 outputs SCK_A4 to the sixth OR gate O6, the fourth selector M4, and the seventh OR gate O7;

[0065] The short pulse counting unit outputs the short pulse count value SCK_CNT to the fourth comparator E4, the fifth comparator E5, and the sixth comparator E6. The fourth comparator E4 outputs SCK_E4 to the fifth OR gate O5. The fifth OR gate O5 outputs SCK_O5 to the fifth selector M5 and the sixth selector M6. The fifth comparator E5 outputs SCK_E5 to the fifth selector M5 and the sixth selector M6;

[0066] The sixth comparator E6 outputs SCK_E6 to the sixth OR gate O6. The sixth OR gate O6 outputs SCK_O6 to the second clock gating G2. The second clock gating G2 is connected to the clock signal CLK and outputs the clock signal CLK to the eighth register Reg8 under the control of SCK_O6. The fourth selector M4 is connected to 0 and 1 and outputs SCK_M4 to the eighth register Reg8 under the control of SCK_A4. The eighth register Reg8 outputs SCK_R8 to the seventh OR gate O7;

[0067] The seventh OR gate O7 outputs SCK_O7 to the fifth selector M5 and the sixth selector M6. The fifth selector M5 selects and outputs TXPB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. The sixth selector M6 selects and outputs TXMB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. TXPB_SCK and TXMB_SCK form a short +1 pulse or a short -1 pulse of the isolated serial interface;

[0068] Among them, SCK_A3 is the rising edge pulse of SCK_R6.

[0069] Specifically, in the short pulse conversion unit, when the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at a high level, it is converted into a short +1 pulse of the isolated serial interface;

[0070] When the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at a low level, it is converted into a short -1 pulse of the isolated serial interface.

[0071] In the technical solution of this application, the working principle of the short pulse conversion unit is as follows:

[0072] The serial interface clock signal SCK is synchronized through two - stage registers Reg5 and Reg6 to generate SCK_R6. SCK_R6 generates SCK_R7 through a one - stage register Reg7. SCK_R7 generates SCK_N3 through an inverter N3. SCK_N3 and SCK_R6 generate SCK_A3 through an AND gate A3. SCK_A3 is the rising edge pulse of SCK_R6;

[0073] The serial interface input data signal SDI is synchronized through two - stage registers Reg9 and Reg10 to generate SDI_R10. SDI_R10 and SCK_A3 generate SCK_A4 through an AND gate A4;

[0074] The short pulse counting unit is a counter for short pulses. When SCK_A3 is 1, the short pulse counting unit starts counting. When the short pulse count value SCK_CNT reaches 3, the count value is reset to 0. The short pulse count value SCK_CNT passes through a comparator E4. When the short pulse count value SCK_CNT is 1, the output SCK_E4 of the comparator E4 is 1. SCK_E4 and SCK_A3 generate SCK_O5 through an OR gate O5;

[0075] The short pulse count value SCK_CNT passes through a comparator E5. When the short pulse count value SCK_CNT is greater than or equal to 2 and less than or equal to 3, the output SCK_E5 of the comparator E5 is 1;

[0076] The short pulse count value SCK_CNT passes through comparator E6. When the short pulse count value SCK_CNT is 3, the output SCK_E6 of comparator E6 is 1; SCK_E6 and SCK_A4 pass through OR gate O6 to generate SCK_O6. SCK_O6 is the enable signal for clock gating G2. When SCK_O6 is 1, the clock signal CLK is sent to register Reg8 through clock gating G2: When SCK_A4 is 1, the output SCK_M4 of selector M4 is 1, and the output SCK_R8 of register Reg8 is 1; when SCK_A4 is 0, the output SCK_M4 of M4 is 0, and the output SCK_R8 of register Reg8 is 0.

[0077] SCK_R8 and SCK_A4 pass through OR gate O7 to generate SCK_O7: When SCK_O7 is 1, the output TXPB_SCK of selector M5 is SCK_O5, and the output TXMB_SCK of selector M6 is SCK_E5. TXPB_SCK and TXMB_SCK form the short +1 pulse of the isolated serial interface; when SCK_O7 is 0, the output TXPB_SCK of selector M5 is SCK_E5, and the output TXMB_SCK of selector M6 is SCK_O5. TXPB_SCK and TXMB_SCK form the short -1 pulse of the isolated serial interface.

[0078] As Figure 4 shown, the SDO conversion unit includes the eleventh register Reg11, the twelfth register Reg12, the thirteenth register Reg13, the fourteenth register Reg14, and the fifteenth register Reg15. The eleventh register Reg11, the twelfth register Reg12, and the thirteenth register Reg13 are all connected to the clock signal CLK;

[0079] The eleventh register Reg11 is connected to the serial interface clock signal SCK and outputs SCK_R11 to the twelfth register Reg12. The twelfth register Reg12 outputs SCK_R12 to the thirteenth register Reg13 and the fourth inverter N4. The thirteenth register Reg13 outputs SCK_R13 to the fifth AND gate A5. The fourth inverter N4 outputs SCK_N4 to the fifth AND gate A5. The fifth AND gate A5 outputs SCK_A5 as the reset signal to the fourteenth register Reg14 and the fifteenth register Reg15;

[0080] The fourteenth register Reg14 is connected to 1 and the isolated serial interface pulse signal RXMB_L and outputs SDO_R14 to the fifteenth register Reg15;

[0081] The fifteenth register, Reg15, receives the isolated serial interface pulse signal RXPB_L and outputs SDO_R15 to the fifth inverter N5. The fifth inverter N5 outputs the serial interface output data signal SDO.

[0082] Among them, SCK_A5 is the falling-edge pulse of SCK_R12. The isolated serial interface pulse signal RXMB_L and the isolated serial interface pulse signal RXPB_L form the short +1 pulse or short -1 pulse of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTBANA.

[0083] Specifically, in the SDO conversion unit, when the isolated serial interface analog-to-digital conversion module PORTB ANA receives the short +1 pulse of the isolated serial interface, the serial interface output data signal SDO is at a high level.

[0084] When the isolated serial interface analog-to-digital conversion module PORTBANA receives the short -1 pulse of the isolated serial interface, the serial interface output data signal SDO is at a low level.

[0085] In the technical solution of this application, the working principle of the SDO conversion unit is as follows:

[0086] The serial interface clock signal SCK is synchronized through two-stage registers Reg11 and Reg12 to generate SCK_R12. SCK_R12 generates SCK_R13 through one-stage register Reg13. SCK_R12 generates SCK_N4 through inverter N4. SCK_N4 and SCK_R13 generate SCK_A5 through AND gate A5. SCK_A5 is the falling-edge pulse of SCK_R12.

[0087] SCK_A5 is the reset signal of register Reg14. The isolated serial interface pulse signal RXMB_L is the clock signal of register Reg14. At the rising edge of RXMB_L, the output SDO_R14 of register Reg14 is 1. When SCK_A5 is 1, the output SDO_R14 of register Reg14 is 0.

[0088] SCK_A5 is the reset signal of register Reg15. The isolated serial interface pulse signal RXPB_L is the clock signal of register Reg15. At the rising edge of RXPB_L, the output SDO_R15 of register Reg15 is the value of SDO_R14. When SCK_A5 is 1, the output SDO_R15 of register Reg15 is 0.

[0089] SDO_R15 generates the serial interface output data signal SDO through inverter N5.

[0090] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A lightweight serial interface and isolated serial interface conversion circuit, characterized in that: It includes a serial interface digital-to-analog conversion module PORTAPAD, an isolated serial interface analog-to-digital conversion module PORTBANA, a long pulse conversion unit, a short pulse conversion unit, and an SDO conversion unit; The long pulse conversion unit converts the rising edge and falling edge of the serial interface chip select signal CS received by the serial interface digital-to-analog conversion module PORTAPAD into long +1 pulses and long -1 pulses of the isolated serial interface respectively; The short pulse conversion unit converts the serial interface clock signal SCK and the serial interface input data signal SDI received by the serial interface digital-to-analog conversion module PORTAPAD into short +1 pulses and short -1 pulses of the isolated serial interface respectively; The SDO conversion unit converts the short +1 pulses and short -1 pulses of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTBANA into the serial interface output data signal SDO.

2. The lightweight serial interface and isolated serial interface conversion circuit according to claim 1, characterized in that: The long pulse conversion unit includes a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, and a long pulse counting unit. The first register Reg1, the second register Reg2, the third register Reg3, and the long pulse counting unit are all connected to the clock signal CLK; The first register Reg1 is connected to the serial interface chip select signal CS and outputs CS_R1 to the second register Reg2. The second register Reg2 outputs CS_R2 to the third register Reg3, the first inverter N1, and the second AND gate A2; The third register Reg3 outputs CS_R3 to the first AND gate A1 and the second inverter N2. The first inverter N1 outputs CS_N1 to the first AND gate A1. The first AND gate A1 outputs CS_A1 to the first OR gate O1. The second inverter N2 outputs CS_N2 to the second AND gate A2. The second AND gate A2 outputs CS_A2 to the first OR gate O1, the fourth OR gate O4, the first selector M1, and the third OR gate O3. The first OR gate O1 outputs CS_O1 to the long pulse counting unit and the second OR gate O2; The long pulse counting unit outputs the long pulse count value CS_CNT to the first comparator E1, the second comparator E2, and the third comparator E3. The first comparator E1 outputs CS_E1 to the second OR gate O2. The second OR gate O2 outputs CS_O2 to the second selector M2 and the third selector M3. The second comparator E2 outputs CS_E2 to the second selector M2 and the third selector M3; The third comparator E3 outputs CS_E3 to the fourth OR gate O4. The fourth OR gate O4 outputs CS_O4 to the first clock gating G1. The first clock gating G1 is connected to the clock signal CLK and outputs the clock signal CLK to the fourth register Reg4 under the control of CS_O4. The first selector M1 is connected to 0 and 1 and outputs CS_M1 to the fourth register Reg4 under the control of CS_A2. The fourth register Reg4 outputs CS_R4 to the third OR gate O3; The third OR gate O3 outputs CS_O3 to the second selector M2 and the third selector M3. The second selector M2 selects and outputs TXPB_CS from CS_O2 and CS_E2 under the control of CS_O3. The third selector M3 selects and outputs TXMB_CS from CS_O2 and CS_E2 under the control of CS_O3. TXPB_CS and TXMB_CS form the long +1 pulse or long -1 pulse of the isolated serial interface; Among them, CS_A1 is the falling-edge pulse of CS_R2, CS_A2 is the rising-edge pulse of CS_R2, and CS_O1 is the edge pulse of CS_R2.

3. The lightweight serial interface and isolated serial interface conversion circuit according to claim 1, wherein: The short pulse conversion unit includes a fifth register Reg5, a sixth register Reg6, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a short pulse counting unit. The fifth register Reg5, the sixth register Reg6, the seventh register Reg7, the ninth register Reg9, the tenth register Reg10, and the short pulse counting unit are all connected to the clock signal CLK; The fifth register Reg5 is connected to the serial interface clock signal SCK and outputs SCK_R5 to the sixth register Reg6. The sixth register Reg6 outputs SCK_R6 to the seventh register Reg7 and the third AND gate A3. The seventh register Reg7 outputs SCK_R7 to the third inverter N3. The third inverter N3 outputs SCK_N3 to the third AND gate A3. The third AND gate A3 outputs SCK_A3 to the fourth AND gate A4, the short pulse counting unit, and the fifth OR gate O5; The ninth register Reg9 is connected to the serial interface input data signal SDI and outputs SDI_R9 to the tenth register Reg10. The tenth register Reg10 outputs SDI_R10 to the fourth AND gate A4. The fourth AND gate A4 outputs SCK_A4 to the sixth OR gate O6, the fourth selector M4, and the seventh OR gate O7; The short pulse counting unit outputs the short pulse count value SCK_CNT to the fourth comparator E4, the fifth comparator E5, and the sixth comparator E6. The fourth comparator E4 outputs SCK_E4 to the fifth OR gate O5. The fifth OR gate O5 outputs SCK_O5 to the fifth selector M5 and the sixth selector M6. The fifth comparator E5 outputs SCK_E5 to the fifth selector M5 and the sixth selector M6; The sixth comparator E6 outputs SCK_E6 to the sixth OR gate O6. The sixth OR gate O6 outputs SCK_O6 to the second clock gating G2. The second clock gating G2 is connected to the clock signal CLK and outputs the clock signal CLK to the eighth register Reg8 under the control of SCK_O6. The fourth selector M4 is connected to 0 and 1 and outputs SCK_M4 to the eighth register Reg8 under the control of SCK_A4. The eighth register Reg8 outputs SCK_R8 to the seventh OR gate O7; The seventh OR gate O7 outputs SCK_O7 to the fifth selector M5 and the sixth selector M6. The fifth selector M5 selects and outputs TXPB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. The sixth selector M6 selects and outputs TXMB_SCK from SCK_O5 and SCK_E5 under the control of SCK_O7. TXPB_SCK and TXMB_SCK form a short +1 pulse or a short -1 pulse of the isolated serial interface; Among them, SCK_A3 is the rising edge pulse of SCK_R6.

4. The lightweight serial interface and isolated serial interface conversion circuit according to claim 3, wherein: In the short pulse conversion unit, when the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at the high level, it is converted into a short +1 pulse of the isolated serial interface; When the serial interface clock signal SCK is at the rising edge and the serial interface input data signal SDI is at the low level, it is converted into a short -1 pulse of the isolated serial interface.

5. The lightweight serial interface and isolated serial interface conversion circuit according to claim 1, wherein: The SDO conversion unit includes the eleventh register Reg11, the twelfth register Reg12, the thirteenth register Reg13, the fourteenth register Reg14, and the fifteenth register Reg15. The eleventh register Reg11, the twelfth register Reg12, and the thirteenth register Reg13 are all connected to the clock signal CLK; The eleventh register Reg11 is connected to the serial interface clock signal SCK and outputs SCK_R11 to the twelfth register Reg12. The twelfth register Reg12 outputs SCK_R12 to the thirteenth register Reg13 and the fourth inverter N4. The thirteenth register Reg13 outputs SCK_R13 to the fifth AND gate A5. The fourth inverter N4 outputs SCK_N4 to the fifth AND gate A5. The fifth AND gate A5 outputs SCK_A5 as a reset signal to the fourteenth register Reg14 and the fifteenth register Reg15; The fourteenth register Reg14 is connected to 1 and the isolated serial interface pulse signal RXMB_L and outputs SDO_R14 to the fifteenth register Reg15; The fifteenth register Reg15 is connected to the isolated serial interface pulse signal RXPB_L and outputs SDO_R15 to the fifth inverter N5. The fifth inverter N5 outputs the serial interface output data signal SDO; Among them, SCK_A5 is the falling edge pulse of SCK_R12. The isolated serial interface pulse signal RXMB_L and the isolated serial interface pulse signal RXPB_L form a short +1 pulse or a short -1 pulse of the isolated serial interface received by the isolated serial interface analog-to-digital conversion module PORTBANA; 6. The lightweight serial interface and isolated serial interface conversion circuit according to claim 5, characterized in that: In the SDO conversion unit, when the isolated serial interface analog-to-digital conversion module PORTBANA receives a short +1 pulse of the isolated serial interface, the serial interface output data signal SDO is at the high level; When the isolated serial interface analog-to-digital conversion module PORTBANA receives a short -1 pulse of the isolated serial interface, the serial interface output data signal SDO is at the low level.

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