Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with at least one first metal wiring layer; depositing and forming a first dielectric layer on the first metal wiring layer; depositing and forming a second dielectric layer on the first dielectric layer; sequentially etching the second dielectric layer and the first dielectric layer by adopting first etching gas until the first metal wiring layer is exposed, and forming a plurality of through holes in the first dielectric layer and initial grooves in the through holes; and sequentially etching the second dielectric layer and the first dielectric layer by adopting second etching gas with the etching selection ratio of 6: 1 to 10: 1 until the first metal wiring layer is exposed, and forming a plurality of through holes in the first dielectric layer and initial grooves in the through holes. In the process of etching the second dielectric layer to form the groove, the first dielectric layer can serve as an etching stop layer, the groove is located on the first metal wiring layer, the etching through phenomenon of the groove is avoided, and the integrity of the semiconductor device is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] On an integrated circuit, electrical connections are achieved between different components through metal. With the continuous progress of integrated circuit manufacturing processes, the size is getting smaller and smaller, and higher device performance and stability are required. Metal copper has low resistance, high power consumption efficiency, and low electromigration, and is a very good conductive metal for smaller feature sizes. However, it is very difficult to etch metal copper using dry etching. The current mainstream damascene process utilizes the existing interlayer dielectric, etches trenches and vias for the electrical conduction path, then fills the metal and removes the excess metal through chemical mechanical polishing to achieve metal copper interconnection at one time.

[0003] However, the performance of existing semiconductor devices with a dual damascene structure needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the performance of semiconductor devices.

[0005] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate having at least one first metal wiring layer thereon; depositing a first dielectric layer on the first metal wiring layer; depositing a second dielectric layer on the first dielectric layer, wherein the material of the first dielectric layer is different from the material of the second dielectric layer; using a first etching gas to etch the second dielectric layer and the first dielectric layer in sequence until the first metal wiring layer is exposed, forming a plurality of vias located in the first dielectric layer and initial trenches located on the vias, wherein the first etching gas includes CF4 and O2, and the proportion range of O2 is 10% to 20%; using a second etching gas with an etching selectivity of 6:1 to 10:1 to etch the second dielectric layer on both sides of the initial trench until the first dielectric layer is exposed, forming a plurality of trenches located in the second dielectric layer, wherein the second etching gas includes CF4 and O2, and the proportion range of CF4 and O2 is 1:1 to 1:2.

[0006] Optionally, the materials of the first dielectric layer and the second dielectric layer are low dielectric constant thin film materials.

[0007] Optionally, the material of the first dielectric layer is SiOF, and the material of the second dielectric layer is one or a combination of SiOCH, SiO2, and SiOC.

[0008] Optionally, the thickness range of the first dielectric layer is from 350 angstroms to 500 angstroms, and the thickness range of the second dielectric layer is from 2800 angstroms to 3000 angstroms.

[0009] Optionally, the step of forming the plurality of through-holes includes: forming a first photoresist layer on the second dielectric layer; performing first exposure and development on the first photoresist layer to form a first photoresist layer with a through-hole pattern; using the first photoresist layer with a through-hole pattern as a mask, etching the second dielectric layer and the first dielectric layer in sequence until the first metal wiring layer is exposed, forming a plurality of through-holes and initial trenches on the through-holes; the step of forming a plurality of trenches includes: spin-coating an anti-reflection layer into the through-holes, the initial trenches and on the second dielectric layer; depositing and forming a hard mask layer on the anti-reflection layer; forming a second photoresist layer on the hard mask layer; performing second exposure and development on the second photoresist layer to form a second photoresist layer with a trench pattern; using the second photoresist layer with a trench pattern as a mask, etching the second dielectric layer on both sides of the initial trench until the first dielectric layer is exposed, forming a plurality of trenches; removing the anti-reflection layer.

[0010] Optionally, before the step of forming the first dielectric layer, it further includes: depositing and forming an etch stop layer on the first metal wiring layer; depositing and forming a first adhesion layer on the etch stop layer; after the step of forming the second dielectric layer, it further includes: depositing and forming a second adhesion layer on the second dielectric layer.

[0011] Optionally, after the step of forming the through-holes and trenches, it further includes: forming a seed layer on the sidewall surfaces and bottom surfaces of the through-holes and the trenches; filling the through-holes and the trenches with a conductive material to form a second metal wiring layer.

[0012] Correspondingly, the present invention further provides a semiconductor structure, including: a substrate, having at least one layer of first metal wiring layer on the substrate; a first dielectric layer, located on the first metal wiring layer; a second dielectric layer, located on the first dielectric layer, wherein the material of the first dielectric layer is different from the material of the second dielectric layer; through-holes, located in the second dielectric layer and the first dielectric layer, and the bottom of the through-holes exposes the first metal wiring layer; trenches, located in the second dielectric layer, and the bottom of the trenches exposes the first dielectric layer, and the opening size of the trenches is larger than the opening size of the through-holes.

[0013] Optionally, the materials of the first dielectric layer and the second dielectric layer are low dielectric constant thin film materials.

[0014] Optionally, the material of the first dielectric layer is SiOF, and the material of the second dielectric layer is SiOCH.

[0015] Optionally, the thickness range of the first dielectric layer is from 350 angstroms to 500 angstroms, and the thickness range of the second dielectric layer is from 2800 angstroms to 3000 angstroms.

[0016] Optionally, the trench is located on the via hole and the trench communicates with the via hole.

[0017] Optionally, the trench is located on the first dielectric layer.

[0018] Optionally, the semiconductor structure further includes: an etch stop layer located on the first metal wiring layer; a first adhesion layer located on the etch stop layer; and a second adhesion layer located on the second dielectric layer.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] In the method for forming a semiconductor structure according to the technical solution of the present invention, a first dielectric layer and a second dielectric layer are formed on the first metal wiring layer, and a via hole and a trench are etched using etch gases with different etch selectivity ratios. The bottom of the trench exposes the first dielectric layer, so that during the process of etching the second dielectric layer to form the trench, the first dielectric layer can serve as an etch stop layer, realizing that the trench is located on the first metal wiring layer, avoiding the phenomenon of etching through the trench, ensuring the integrity of the semiconductor device, and ensuring the accuracy of the electrical connection between the first metal wiring layer and the second metal wiring layer formed subsequently, improving the performance of the semiconductor device.

[0021] Furthermore, in the technical solution of the present invention, by setting the thickness range of the first dielectric layer to be from 350 angstroms to 500 angstroms and the thickness range of the second dielectric layer to be from 2800 angstroms to 3000 angstroms, the thickness of the dielectric layer is increased, and then the etch window of the trench is increased, so that the trench is located on the first metal wiring layer, avoiding the over-etching phenomenon at the bottom of the trench, realizing the accuracy of device electrical connection, and improving the reliability and performance of the device.

[0022] In the semiconductor structure according to the technical solution of the present invention, the first dielectric layer and the second dielectric layer are formed on the first metal wiring layer to form the first dielectric layer and the second dielectric layer, realizing an increase in the thickness of the dielectric layer, and then making the trench located within the second dielectric layer, avoiding the phenomenon of etching through the trench, ensuring the integrity of the semiconductor device, and ensuring the accuracy of the electrical connection between the first metal wiring layer and the second metal wiring layer formed subsequently, improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0024] Figures 2 to 8It is a schematic diagram of the formation process of a semiconductor structure in an embodiment of the present invention. Detailed implementation manners

[0025] It should be noted that the "surface" and "on" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0026] For the current method of forming a semiconductor structure, please refer to Figure 1 , provide a substrate 100, and there is at least one first metal wiring layer 101 on the substrate 100; deposit and form a dielectric layer on the first metal wiring layer 101; etch the dielectric layer until the first metal wiring layer 101 is exposed to form a plurality of through holes 103; etch the dielectric layer on both sides of the through holes 103 to form a plurality of trenches 102.

[0027] In this embodiment, the depth range of the trench 102 is 2800 Å to 3000 Å.

[0028] In this embodiment, an over-etching 104 phenomenon occurs at the bottom of some of the trenches 102, and some of the trenches 102 are located within the substrate 100.

[0029] Among them, the over-etching 104 phenomenon is characterized in that when etching the trench 102, the depth of the trench 102 exceeds the maximum depth value allowed for the trench 102.

[0030] In the above solution, when etching the trench 102 in the dielectric layer, there are situations of different etching rates and a narrow corresponding window of etching time and etching thickness, which in turn causes the over-etching 104 phenomenon of the trench 102. After subsequent filling with a conductor, it is easy to cause electrical property and yield losses, affecting the performance of semiconductor devices.

[0031] To solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same. A first dielectric layer and a second dielectric layer are formed on the first metal wiring layer, and a through hole is etched and formed by using a first etching gas with an etching selectivity ratio of 1:1, and the bottom of the trench exposes the first dielectric layer, so that in the process of etching the second dielectric layer to form a trench by using a second etching gas with an etching selectivity ratio of 6:1 to 10:1, the first dielectric layer can serve as an etching stop layer, realizing that the trench is located on the first metal wiring layer, avoiding the phenomenon of trench breakthrough, ensuring the integrity of the semiconductor device, and ensuring the accuracy of the electrical connection between the first metal wiring layer and the second metal wiring layer formed subsequently, improving the performance of the semiconductor device.

[0032] To make the above objects, features and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0033] Please refer to Figure 2 , a substrate 200 is provided, and at least one first metal wiring layer 204 is disposed on the substrate 200.

[0034] In some embodiments of the present invention, the material of the substrate 200 is silicon.

[0035] In other embodiments, the material of the substrate 200 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate 200 may also be a silicon-on-insulator substrate 200 or a germanium-on-insulator substrate 200.

[0036] In some embodiments of the present invention, the first metal wiring layer 204 is a single layer.

[0037] In a specific embodiment of the present invention, the method for forming the first metal wiring layer 204 includes: depositing an interlayer dielectric layer 201 on the substrate 200; forming a plurality of contact holes (not shown in the figure) in the interlayer dielectric layer 201; depositing a first etch stop layer 2021 on the interlayer dielectric layer 201; forming a third dielectric layer 203 on the first etch stop layer 2021; sequentially etching the third dielectric layer 203, the first etch stop layer 2021, and a part of the interlayer dielectric layer 201 until the top surface of the contact hole is exposed, to form a plurality of first through holes 211 (not shown in the figure); filling a conductive material into the first through holes 211 to form the first metal wiring layer 204, and the first metal wiring layer 204 is electrically connected to the contact hole.

[0038] In some embodiments of the present invention, the first metal wiring layer 204 adopts a single damascene process.

[0039] In some embodiments of the present invention, the first etch stop layer 2021 is a low dielectric constant (Low-k) barrier layer, specifically a carbon / nitrogen compound of silicon.

[0040] In some embodiments, the material of the first etch stop layer 2021 is silicon nitride or silicon carbide.

[0041] In some embodiments of the present invention, the material of the first metal wiring layer 204 includes one or more combinations of copper, titanium, tantalum, and tungsten.

[0042] In some embodiments of the present invention, the first metal wiring layer 204 is filled with metal by an electroplating process.

[0043] In other embodiments of the present invention, before forming the first metal wiring layer 204, it further includes: forming a seed layer on the surface of the first through holes 211 by atomic layer deposition (ALD) technology.

[0044] Among them, the material of the seed layer includes one or a combination of more of: copper, titanium, tantalum, and tungsten.

[0045] The seed layer is used to improve the adhesion and conductivity of the subsequent first metal wiring layer 204.

[0046] Please refer to Figure 3 , deposit and form a first dielectric layer 206 on the first metal wiring layer 204; deposit and form a second dielectric layer 207 on the first dielectric layer 206, where the material of the first dielectric layer 206 is different from the material of the second dielectric layer 207.

[0047] In some embodiments of the present invention, the materials of the first dielectric layer 206 and the second dielectric layer 207 are low dielectric constant thin film materials.

[0048] In some embodiments of the present invention, the material of the first dielectric layer 206 is SiOF, and the material of the second dielectric layer 207 is one or a combination of more of SiOCH, SiO2, and SiOC.

[0049] In some embodiments of the present invention, the first metal wiring layer 204 is a single-layer metal wiring layer. When the subsequently formed second metal wiring layer 216 is a single-layer metal wiring layer on the first metal wiring layer 204, the thickness range of the first dielectric layer 206 is 350 Å to 500 Å, and the thickness range of the second dielectric layer 207 is 2800 Å to 3000 Å.

[0050] In this embodiment, by setting the thickness range of the first dielectric layer 206 to 350 Å to 500 Å and the thickness range of the second dielectric layer 207 to 2800 Å to 3000 Å, the thickness of the dielectric layer is increased, thereby increasing the etching window of the trench 215, so that the trench 215 is located on the first metal wiring layer 204, avoiding over-etching at the bottom of the trench 215, realizing the accuracy of device electrical connection, and improving device reliability and performance.

[0051] In a specific embodiment of the present invention, before the step of forming the first dielectric layer 206, it further includes: depositing and forming an etching barrier layer 2022 on the first metal wiring layer 204; depositing and forming a first adhesion layer 205 on the etching barrier layer 2022.

[0052] Among them, the etching barrier layer 2022 is a low dielectric constant (Low-k) barrier layer, specifically a carbon / nitrogen compound of silicon. In some embodiments, the material of the etching barrier layer 2022 is silicon nitride or silicon carbide.

[0053] Among them, the material of the first adhesion layer 205 is tetraethoxysilane. The first adhesion layer 205 is used to enhance the adhesion between the etch stop layer 2022 and the first dielectric layer 206, avoiding the risk of film peeling.

[0054] In a specific embodiment of the present invention, after the step of forming the second dielectric layer 207, it further includes: depositing and forming a second adhesion layer 208 on the second dielectric layer 207.

[0055] Among them, the material of the second adhesion layer 208 is tetraethoxysilane. The second adhesion layer 208 is used to enhance the adhesion between the second dielectric layer 207 and the subsequent anti-reflection coating 212, avoiding the risk of film peeling.

[0056] Please refer to Figure 4 , forming a first photoresist layer 209 on the second dielectric layer 207; performing first exposure and development on the first photoresist layer 209 to form a first photoresist layer 209 with a via hole 211 pattern.

[0057] Please refer to Figure 5 , using the first photoresist layer 209 with a via hole 211 pattern as a mask, and using a first etching gas, sequentially etching the second dielectric layer 207 and the first dielectric layer 206 until the first metal wiring layer 204 is exposed, forming a plurality of via holes 211 in the first dielectric layer 206 and an initial trench 210 on the via holes 211.

[0058] In some embodiments of the present invention, the first etching gas includes CF4 and O2, and the proportion of O2 ranges from 10% to 20%.

[0059] In some embodiments of the present invention, the etching process used is anisotropic dry etching.

[0060] In a specific embodiment of the present invention, under the etching conditions of the first etching gas, the etching rate ratio of the second dielectric layer 207 to the first dielectric layer 206 is 1:1.

[0061] It should be noted that the present invention does not limit the etching selectivity of the first etching gas, and other etching selectivities that can simultaneously etch the second dielectric layer and the first dielectric layer are within the protection scope of the present invention.

[0062] Among them, etching the second dielectric layer 207 and the first dielectric layer 206 with a first etching gas having an etching selectivity ratio of 1:1 can make the etching rates of the second dielectric layer 207 and the first dielectric layer 206 the same, and then a through hole 211 located in the first dielectric layer 206 and an initial trench 210 located in the second dielectric layer 207 can be formed.

[0063] In some embodiments of the present invention, it further includes: etching the first adhesion layer 205 at the bottom of the first dielectric layer 206 and a part of the etching barrier layer 2022.

[0064] Please refer to Figure 6 , spin-coat an anti-reflection layer into the through hole 211 and on the second dielectric layer 207; deposit and form a hard mask layer 213 on the anti-reflection layer; form a second photoresist layer 214 on the hard mask layer 213; perform second exposure and development on the second photoresist layer 214 to form a second photoresist layer 214 having a trench 215 pattern.

[0065] Please refer to Figure 7 , using the second photoresist layer 214 having a trench 215 pattern as a mask, etching the second dielectric layer 207 on both sides of the initial trench 210 with a second etching gas having an etching selectivity ratio of 6:1 to 10:1 until the first dielectric layer 206 is exposed, and forming a plurality of trenches 215 located in the second dielectric layer 207.

[0066] In some embodiments of the present invention, the second etching gas includes CF4 and O2, and the ratio of the CF4 to the O2 gas is 1:1 to 1:2.

[0067] In some embodiments of the present invention, the etching process used is anisotropic dry etching.

[0068] In a specific embodiment of the present invention, under the etching conditions of the second etching gas, the ratio of the etching rate of the second dielectric layer 207 to the etching rate of the first dielectric layer 206 is 6:1 to 10:1.

[0069] Among them, the ratio of the etching rate of the second dielectric layer 207 to the etching rate of the first dielectric layer 206 is 6:1 to 10:1. It can be seen that the etching rate of the second dielectric layer 207 is greater than the etching rate of the first dielectric layer 206. Furthermore, the position where the trench 215 is formed can be accurately controlled, so that the etched trench 215 is located in the second dielectric layer 207, protecting the integrity of the structure of the first metal wiring layer 204, and ensuring the accuracy of the electrical connection between the first metal wiring layer 204 and the second metal wiring layer 216 formed subsequently, improving the performance of the semiconductor device.

[0070] In other embodiments of the present invention, after the step of forming a plurality of trenches 215, it further includes: removing the antireflection layer.

[0071] In some embodiments of the present invention, it further includes: etching the etch stop layer 2022 at the bottom of the through hole 211 until the top surface of the first metal wiring layer 204 is exposed.

[0072] Please refer to Figure 8 , after the steps of forming the through hole 211 and the trenches 215, it further includes: forming a seed layer (not shown in the figure) on the side wall surfaces and the bottom surface of the through hole 211 and the trenches 215; filling the through hole 211 and the trenches 215 with a conductive material to form a second metal wiring layer 216.

[0073] In some embodiments of the present invention, the material of the second metal wiring layer 216 includes: one or a combination of more of copper, titanium, tantalum, and tungsten.

[0074] In some embodiments of the present invention, the second metal wiring layer 216 is filled with metal by an electroplating process.

[0075] In other embodiments of the present invention, before forming the second metal wiring layer 216, it further includes: using atomic layer deposition (ALD) technology to form a seed layer on the surfaces of the through hole 211 and the trenches 215.

[0076] Wherein, the material of the seed layer includes: one or a combination of more of copper, titanium, tantalum, and tungsten.

[0077] The seed layer is used to improve the adhesion and conductivity of the subsequent second metal wiring layer 216.

[0078] In some embodiments of the present invention, the second metal wiring layer 216 adopts a dual damascene process.

[0079] In the above solution, a first dielectric layer 206 and a second dielectric layer 207 are formed on the first metal wiring layer 204, and etch gases with different etch selectivity ratios are used to etch and form the through hole 211 and the trenches 215. The bottom of the trenches 215 exposes the first dielectric layer 206, so that during the process of etching the second dielectric layer 207 to form the trenches 215, the first dielectric layer 206 can serve as an etch stop layer, enabling the trenches 215 to be located on the first metal wiring layer 204, avoiding the phenomenon of the trenches 215 being etched through, ensuring the integrity of the semiconductor device, and ensuring the accuracy of the electrical connection between the first metal wiring layer 204 and the subsequently formed second metal wiring layer 216, thereby improving the performance of the semiconductor device.

[0080] Correspondingly, the present invention further provides a semiconductor structure, including: a substrate 200, on which there is at least one layer of first metal wiring layer 204; a first dielectric layer 206, located on the first metal wiring layer 204; a second dielectric layer 207, located on the first dielectric layer 206, wherein the material of the first dielectric layer 206 is different from that of the second dielectric layer 207; a via hole 211, located in the second dielectric layer 207 and the first dielectric layer 206, and the bottom of the via hole 211 exposes the first metal wiring layer 204; a trench 215, located in the second dielectric layer 207, and the bottom of the trench 215 exposes the first dielectric layer 206, and the opening size of the trench 215 is larger than the opening size of the via hole 211.

[0081] In some embodiments of the present invention, the materials of the first metal wiring layer 204 and the second metal wiring layer 216 include: one or a combination of copper, titanium, tantalum, and tungsten.

[0082] In some embodiments of the present invention, the materials of the first dielectric layer 206 and the second dielectric layer 207 are low dielectric constant thin film materials.

[0083] In some embodiments of the present invention, the material of the first dielectric layer 206 is SiOF, and the material of the second dielectric layer 207 is SiOCH.

[0084] In some embodiments of the present invention, the first metal wiring layer 204 is a single layer of metal wiring layer. When the subsequently formed second metal wiring layer 216 is a single layer of metal wiring layer on the first metal wiring layer 204, the thickness range of the first dielectric layer 206 is 350 Å to 500 Å, and the thickness range of the second dielectric layer 207 is 2800 Å to 3000 Å.

[0085] In this embodiment, by setting the thickness range of the first dielectric layer 206 to 350 Å to 500 Å and the thickness range of the second dielectric layer 207 to 2800 Å to 3000 Å, the thickness of the dielectric layer is increased, and then the etching window of the trench 215 is increased, so that the trench 215 is located on the first metal wiring layer 204, avoiding over-etching at the bottom of the trench 215, realizing the accuracy of device electrical connection, and improving device reliability and performance.

[0086] In some embodiments of the present invention, the first metal wiring layer 204 adopts a single damascene process.

[0087] In some embodiments of the present invention, the trench 215 is located on the via hole 211, and the trench 215 communicates with the via hole 211.

[0088] In some embodiments of the present invention, the trench 215 is located on the first dielectric layer 206.

[0089] In some embodiments of the present invention, the semiconductor structure further includes: an etch stop layer 2022 located on the first metal wiring layer 204; a first adhesion layer 205 located on the etch stop layer 2022; and a second adhesion layer 208 located on the second dielectric layer 207.

[0090] In this embodiment, the etch stop layer 2022 is a low dielectric constant (Low-k) barrier layer, specifically a carbon / nitrogen compound of silicon. In some embodiments, the material of the etch stop layer 2022 is silicon nitride or silicon carbide.

[0091] In this embodiment, the materials of the first adhesion layer 205 and the second adhesion layer 208 are tetraethoxysilane. The first adhesion layer 205 is used to enhance the adhesion between the etch stop layer 2022 and the first dielectric layer 206, avoiding the risk of film peeling; the second adhesion layer 208 is used to enhance the adhesion between the second dielectric layer 207 and the subsequent anti-reflection coating 212, avoiding the risk of film peeling.

[0092] In some embodiments of the present invention, the semiconductor structure further includes: a second metal wiring layer 216, and the second metal wiring layer 216 is located in the through hole 211 and the trench 215.

[0093] In some embodiments of the present invention, the material of the second metal wiring layer 216 includes: one or a combination of copper, titanium, tantalum, and tungsten.

[0094] In some embodiments of the present invention, the semiconductor structure further includes: a seed layer located on the surfaces of the through hole 211 and the trench 215.

[0095] Among them, the material of the seed layer includes: one or a combination of copper, titanium, tantalum, and tungsten.

[0096] The seed layer is used to improve the adhesion and conductivity of the subsequent second metal wiring layer 216.

[0097] In the above solution, in the semiconductor structure of the technical solution of the present invention, the first dielectric layer 206 and the second dielectric layer 207 are formed on the first metal wiring layer 204 to form the first dielectric layer 206 and the second dielectric layer 207, so as to increase the thickness of the dielectric layer. Further, the trench 215 is located within the second dielectric layer 207, avoiding the phenomenon of the trench 215 being etched through, ensuring the integrity of the semiconductor device, and ensuring the accuracy of the electrical connection between the first metal wiring layer 204 and the subsequently formed second metal wiring layer 216, thereby improving the performance of the semiconductor device.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate having at least one first metal wiring layer thereon; Depositing a first dielectric layer on the first metal wiring layer; Depositing a second dielectric layer on the first dielectric layer, wherein the material of the first dielectric layer is different from the material of the second dielectric layer; Using a first etching gas to etch the second dielectric layer and the first dielectric layer in sequence until the first metal wiring layer is exposed, forming a plurality of through holes in the first dielectric layer and initial trenches on the through holes, wherein the first etching gas includes CF4 and O2, and the proportion range of O2 is 10% to 20%; Using a second etching gas with an etching selectivity ratio of 6:1 to 10:1 to etch the second dielectric layer on both sides of the initial trench until the first dielectric layer is exposed, forming a plurality of trenches in the second dielectric layer, wherein the second etching gas includes CF4 and O2, and the proportion range of CF4 and O2 is 1:1 to 1:

2.

2. The method for forming a semiconductor structure according to claim 1, wherein, The materials of the first dielectric layer and the second dielectric layer are low dielectric constant thin film materials.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the first dielectric layer is SiOF, and the material of the second dielectric layer is one or a combination of SiOCH, SiO2, and SiOC.

4. The method for forming a semiconductor structure according to claim 1, wherein, The thickness range of the first dielectric layer is 350 Å to 500 Å, and the thickness range of the second dielectric layer is 2800 Å to 3000 Å.

5. The method for forming a semiconductor structure according to claim 1, wherein, The steps of forming the plurality of through holes include: Forming a first photoresist layer on the second dielectric layer; Performing first exposure and development on the first photoresist layer to form a first photoresist layer with a through hole pattern; Using the first photoresist layer with a through hole pattern as a mask to etch the second dielectric layer and the first dielectric layer in sequence until the first metal wiring layer is exposed, forming a plurality of through holes and initial trenches on the through holes; The steps of forming a plurality of trenches include: Spin-coating an anti-reflection layer into the through holes, the initial trenches, and on the second dielectric layer; Depositing a hard mask layer on the anti-reflection layer; Forming a second photoresist layer on the hard mask layer; Performing second exposure and development on the second photoresist layer to form a second photoresist layer with a trench pattern; Using the second photoresist layer with a trench pattern as a mask to etch the second dielectric layer on both sides of the initial trench until the first dielectric layer is exposed, forming a plurality of trenches; Removing the anti-reflection layer.

6. The method for forming a semiconductor structure according to claim 1, wherein, Before the step of forming the first dielectric layer, further comprising: Depositing an etching barrier layer on the first metal wiring layer; Depositing a first adhesion layer on the etching barrier layer; After the step of forming the second dielectric layer, further comprising: Depositing a second adhesion layer on the second dielectric layer.

7. The method for forming a semiconductor structure according to claim 1, wherein, After the steps of forming the through holes and the trenches, further comprising: Forming a seed layer on the sidewall surfaces and bottom surfaces of the through holes and the trenches; Filling a conductive material into the through holes and the trenches to form a second metal wiring layer.

8. A semiconductor structure, characterized in that, Comprising: A substrate having at least one first metal wiring layer thereon; A first dielectric layer located on the first metal wiring layer; A second dielectric layer, located on the first dielectric layer, wherein the material of the first dielectric layer is different from that of the second dielectric layer; A via hole, located in the second dielectric layer and the first dielectric layer, and the bottom of the via hole exposes the first metal wiring layer; A trench, located in the second dielectric layer, and the bottom of the trench exposes the first dielectric layer, and the opening size of the trench is larger than that of the via hole.

9. The semiconductor structure according to claim 8, wherein The materials of the first dielectric layer and the second dielectric layer are low dielectric constant thin film materials.

10. The semiconductor structure according to claim 9, wherein The material of the first dielectric layer is SiOF, and the material of the second dielectric layer is one or a combination of SiOCH, SiO2, and SiOC.

11. The semiconductor structure according to claim 8, wherein, The thickness range of the first dielectric layer is 350 Å to 500 Å, and the thickness range of the second dielectric layer is 2800 Å to 3000 Å.

12. The semiconductor structure according to claim 8, wherein, The trench is located above the via hole and is in communication with the via hole.

13. The semiconductor structure according to claim 8, wherein The trench is located on the first dielectric layer.

14. The semiconductor structure according to claim 8, wherein, Further comprising: An etch stop layer, located on the first metal wiring layer; a first adhesion layer, located on the etch stop layer; A second adhesion layer, located on the second dielectric layer.

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