Monostable feedback device in PUF code generator, generator and generation method

Abstract

The invention relates to a monostable feedback device in a PUF (Physical Unclonable Function) code generator, the generator and a generation method. Wherein the monostable feedback device comprises a plurality of double-open single-control switches and a bit unit circuit; the bit unit circuit is used for realizing voltage reversal and outputting the voltage of the input end from the output end after the voltage is reversed; the second terminal of the first switch and the first terminal of the second switch of one double-open single-control switch are respectively connected with the input end and the output end of the bit unit circuit of the branch circuit where the double-open single-control switch is located; a first node where the first wiring ends of the first switches of all the double-open single-control switches are connected together is connected with a second node where the second wiring ends of the second switches of all the double-open single-control switches are connected together, and the second node serves as the output end of the monostable feedback device. When the monostable feedback device is applied to the PUF code generator, PUF code sources are richer, so that more types of PUF codes are generated, and strong PUF codes are obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of information security, and in particular to a monostable feedback device in a PUF code generator, a generator and a generating method. Background Art

[0002] With the rapid development of technologies such as artificial intelligence, the Internet of Things, and big data, security and confidentiality have become key technical issues that must be addressed and resolved in today's era. As a new type of security technology, the physical unclonable function PUF naturally has the characteristics of physical unclonability and tamper-proof. It is called a "physical fingerprint" and is widely used in security scenarios such as key generation, authorization, and authentication.

[0003] Traditional PUFs are mainly divided into two categories: delay PUF and storage PUF. The most common delay PUF is the ring oscillator RO PUF, but the response time of this type of PUF is relatively long. The most common storage PUF is SARM PUF, but this type of PUF will be affected by the initial value of power-on. Based on the above analysis, the application of traditional PUF will be limited. Summary of the invention

[0004] The present invention aims to provide a monostable feedback device, a generator and a generation method in a PUF code generator; so that the response time of the architecture PUF code generator is short, and the response value will not be affected by the initial value of power-on. At the same time, the architecture PUF code generator makes the PUF code source richer by gating the double-open single-control switch in the monostable feedback device, and can generate more types of PUF codes to obtain strong PUF codes.

[0005] The present invention discloses a monostable feedback device in a PUF code generator, wherein the monostable feedback device comprises M double-open single-control switches C1 to C2. M , M bit unit circuits U1~U M ;

[0006] The bit unit circuit is used to achieve voltage inversion, and the voltage at the input end is inverted and then output from the output end;

[0007] The double-open single-control switch C m The first switch C m-1 The second connection terminal of the second switch C m-2 The first terminals of the bit unit circuits U m The input and output terminals are connected;

[0008] A first node where the first terminals of all double-open single-control switches are connected together is connected to a second node where the second terminals of all double-open single-control switches are connected together, and the second node serves as the output end of the monostable feedback device; m=1,…,M.

[0009] Further, the bit cell circuit includes: an inverter circuit INV, a first auxiliary regulation circuit, and a second auxiliary regulation circuit;

[0010] The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary regulation circuit, and a node connected to the second auxiliary regulation circuit;

[0011] A first auxiliary regulation circuit is connected between the node where the inverter circuit is connected to the first auxiliary regulation circuit and the power supply VDD; a second auxiliary regulation circuit is connected between the node connected to the second auxiliary regulation circuit and the ground GND;

[0012] The input voltage Vin applied to the voltage input terminal is inverted by the inverter circuit INV and the voltage Vout is output from the voltage output terminal;

[0013] The first auxiliary regulation circuit and the second auxiliary regulation circuit are used to limit the current and divide the voltage of the bit cell circuit.

[0014] Further, the first auxiliary regulation circuit and the second auxiliary regulation circuit are electronic devices or circuits with current limiting and voltage dividing functions including resistors and MOS diodes, and are used to limit the current and divide the voltage of the bit cell circuit.

[0015] The present invention also discloses a PUF code generator, including N PUF cores arranged in parallel; each PUF core is used to generate a 1Bit PUF code; N PUF cores generate an N Bit PUF code in total;

[0016] Each PUF core includes: a monostable feedback module, a strengthening verification module, and a digitization module; wherein,

[0017] The monostable feedback module is used to generate the voltage value T of the source of the 1Bit PUF code of this PUF core; the voltage values T in each PUF core are distributed in a non-linear law;

[0018] The strengthening verification module is used to drive the voltage value T step by step and output the voltage Y;

[0019] The digitization module is used to digitize the output voltage Y and output the 1Bit PUF code of this PUF core;

[0020] The monostable feedback modules in the N PUF cores all adopt the above-mentioned monostable feedback devices.

[0021] Further, the PUF code generator further includes a digital logic circuit; the digital logic circuit is respectively connected to the monostable feedback modules in each PUF core and provides gating control for M double-open single-control switches in each monostable feedback module.

[0022] Furthermore, different gating control logics are configured for the M double-break single-pole switches in the monostable feedback module of each PUF core through digital logic circuits, and bit cell circuits at the same or different positions and in the same or different quantities are gated in the monostable feedback modules of different PUF cores; different voltage values T are output by the monostable feedback modules in each PUF core, and finally PUF codes are obtained after passing through the enhancement verification module and the digitization module; by changing the gating control logic in the digital logic circuit, a strong PUF is realized.

[0023] Furthermore, the enhancement verification module includes cascaded bit cell circuits; the input end of the first-stage bit cell circuit in the cascade is connected to the output end T of the monostable feedback module, and the output end of the last-stage bit cell in the cascade outputs voltage Y.

[0024] Each stage of the bit cell circuit serves as a single-ended comparator, comparing its input voltage with its own flip voltage Vtrip; the cascaded bit cell circuits gradually amplify the deviation of their input voltage relative to their own flip voltage Vtrip, and the outputs of the cascaded bit cell circuits gradually approach VDD or GND, and finally an output voltage Y approximately equal to VDD or GND is output.

[0025] Furthermore, a Buf module is included in the digitization module circuit; the input end of the Buf module is connected to the output end Y of the enhancement verification module, and the output end outputs a 1Bit PUF code OUT.

[0026] When the voltage value of the output voltage Y is near VDD, the Buf module outputs "1".

[0027] When the voltage value of the output voltage Y is near GND, the Buf module outputs "0".

[0028] The present invention also discloses a PUF code generation method using the PUF code generator as described above, including:

[0029] Step S1, initialize the PUF code generator, and set PUF working conditions including the supply voltage VDD and the excitation gating control.

[0030] Step S2, after the power supply works stably, perform gating logic control on the M double-break single-pole switches in the monostable feedback modules of the N PUF cores in the PUF code generator, and gate bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback modules of different PUF cores.

[0031] Step S3, after each PUF core works, output an N Bit PUF code.

[0032] Step S4: Extract the N-bit PUF code output in Step S3.

[0033] The present invention also discloses another PUF code generation method using the PUF code generator as described above, including:

[0034] Step S1: Initialize the PUF code generator and set the PUF working conditions including the supply voltage VDD and the excitation strobe control.

[0035] Step S2: After the power supply works stably, perform strobe logic control on the M double-open single-control switches in the monostable feedback device of each PUF core in the PUF code generator, and strobe the bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback devices of different PUF cores.

[0036] Step S3: After each PUF core works, output the first group of N-bit PUF codes.

[0037] Step S4: Extract the N-bit PUF code output in Step S3.

[0038] Step S5: Disconnect the power supply, power on again, and after the power supply is stable, change the positions and quantities of the strobed bit cell circuits in the monostable feedback device of each PUF core.

[0039] Step S6: After each PUF core works, output the second group of N-bit PUF codes.

[0040] Step S7: Extract the N-bit PUF code output in Step S6.

[0041] Step S8: Repeat Steps S5, S6, and S7 multiple times to obtain multiple groups of PUF codes without changing the circuit scale, thereby implementing a strong PUF.

[0042] The present invention can achieve one of the following beneficial effects:

[0043] The monostable feedback device, generator and generation method in the PUF code generator disclosed by the present invention; by controlling the gating of the double-open single-control switch in the monostable feedback device, the bit cell circuit combinations at the same position and quantity or different positions and quantities in the monostable feedback devices of different PUF cores work together, resulting in different output voltages for the monostable feedback devices of each PUF core, that is, PUF codes from different sources, and finally obtaining a unique PUF code. The response time of this PUF code generator is short, and the response value is not affected by the initial power-on value; by changing the gating control of the double-open single-control switch in the monostable feedback device multiple times, the sources of PUF codes are made richer, thereby generating more types of PUF codes, obtaining a strong PUF, whose excitation response grows exponentially relative to the PUF with a finite type of excitation response pair, and has a small overhead and strong anti-attack ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings are only for the purpose of showing specific embodiments and are not considered as a limitation to the present invention. Throughout the drawings, the same reference signs denote the same components;

[0045] Figure 1 It is a schematic connection diagram of the composition of the monostable feedback device in the embodiment of the present invention;

[0046] Figure 2 It is a schematic connection diagram of the composition of the bit cell circuit in the embodiment of the present invention;

[0047] Figure 3 It is a schematic connection diagram of the composition of an example of the bit cell circuit in the embodiment of the present invention;

[0048] Figure 4 It is a schematic connection diagram of the composition of the PUF code generator in the embodiment of the present invention;

[0049] Figure 5 It is a schematic connection diagram of the composition of the enhanced verification module in the embodiment of the present invention;

[0050] Figure 6 It is a schematic connection diagram of the composition of the digitalization module circuit in the embodiment of the present invention;

[0051] Figure 7 It is a schematic connection diagram of the composition of the PUF code generator including digital logic circuits in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] The following will specifically describe the preferred embodiments of the present invention with reference to the drawings, wherein the drawings form a part of this application and are used together with the embodiments of the present invention to explain the principle of the present invention.

[0053] Embodiment 1

[0054] An embodiment of the present invention discloses a monostable feedback device in a PUF code generator, as Figure 1 shown. The monostable feedback device includes M double-break single-pole switches C1 to C M , and M bit cell circuits U1 to U M ;

[0055] The bit cell circuit is used to reverse the voltage and output the reversed voltage from the output end after reversing the voltage at the input end;

[0056] For the double-break single-pole switch C m , the second terminal of the first switch C m-1 and the first terminal of the second switch C m-2 are respectively connected to the input end and the output end of the bit cell circuit U m ;

[0057] The first node where the first terminals of the first switches of all double-break single-pole switches are connected together is connected to the second node where the second terminals of the second switches of all double-break single-pole switches are connected together. The second node serves as the output end of the monostable feedback device; m = 1,..., M.

[0058] After the power supply VDD is stable, after each path of the double-break single-pole switch C m is controlled to conduct, through the connection relationship between the first node and the second node, the input end and the output end of the bit cell circuit U m are connected, and the output voltage is fed back to the input end to form a monostable state. The output voltage value of the bit cell circuit U m is approximately equal to VDD / 2;

[0059] When multiple paths of double-break single-pole switches are controlled to conduct, multiple paths of bit cell circuits form their respective feedback loops through the conduction states of the double-break single-pole switches connected to them and the connection relationship between the first node and the second node; after the output voltages of each path of bit cell circuits are synthesized at the output end of the monostable feedback device, the output voltage of the monostable feedback device is obtained;

[0060] Taking the example where two paths of double-break single-pole switches C1 and C2 are controlled to conduct; after the double-break single-pole switch C1 conducts, the output voltage value V1 of the bit cell circuit U1 is approximately 2.4V (VDD is 5V), and after the double-break single-pole switch C2 conducts, the output voltage value V2 of the bit cell circuit U2 is approximately 2.55V; then through the loop formed by the first node and the second node, the voltage T after the circuit is stable is the average value of the output voltages of these two bit cell circuits, approximately 2.475V, and this value is closer to VDD / 2 than V1 and V2.

[0061] The on-off selection control of the M double-pole single-throw switches in the monostable feedback device based on this embodiment can generate a larger number of output voltages at the output end of the monostable feedback device, making the voltage T after the circuit stabilizes closer to VDD / 2. When the monostable feedback device of this embodiment is applied to the generation of PUF codes, the source of PUF codes is richer, thereby generating more types of PUF codes.

[0062] As Figure 2 shown, each bit cell circuit in the monostable feedback device includes an inverter circuit INV, a first auxiliary adjustment circuit, and a second auxiliary adjustment circuit;

[0063] The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary adjustment circuit, and a node connected to the second auxiliary adjustment circuit.

[0064] A first auxiliary adjustment circuit is connected between the node of the inverter circuit connected to the first auxiliary adjustment circuit and the power supply VDD; a second auxiliary adjustment circuit is connected between the node of the inverter circuit connected to the second auxiliary adjustment circuit and the ground GND;

[0065] The input voltage Vin applied to the voltage input terminal is inverted by the inverter circuit INV and the output voltage Vout is output from the voltage output terminal;

[0066] The first auxiliary adjustment circuit and the second auxiliary adjustment circuit are used to limit the current and divide the voltage of the bit cell circuit.

[0067] After the power supply is stable, the first switch and the second switch of the double-pole single-throw switch are turned on simultaneously, the input terminal and the output terminal of the bit cell circuit are connected, and under the adjustment of the first auxiliary adjustment circuit and the second auxiliary adjustment circuit, both the PMOS transistor and the NMOS transistor in the inverter circuit operate in the subthreshold region; the output voltage T≈VDD / 2.

[0068] At the same time, the first auxiliary adjustment circuit and the second auxiliary adjustment circuit have the functions of current limiting and voltage dividing, making the PUF core of this architecture have advantages such as low power consumption and small leakage.

[0069] In actual design, the first auxiliary adjustment circuit and the second auxiliary adjustment circuit can be implemented by electronic devices or circuits with the above functions. For example, resistors, MOS diodes, etc.

[0070] Specifically, as Figure 3 shown, an example of a bit cell circuit given in this embodiment includes diodes D1, D2, a PMOS transistor MP1, and an NMOS transistor MN1;

[0071] Among them, the voltage input terminal VIN is respectively connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1; the drains of the PMOS transistor MP1 and the NMOS transistor MN1 are connected as the voltage output terminal VOUT; the power supply VDD is connected to the source of the PMOS transistor MP1 after passing through the anode and cathode of the diode D1; the source of the NMOS transistor MN1 is connected to GND after passing through the anode and cathode of the diode D2.

[0072] When a high voltage is input at the voltage input terminal VIN to turn off the PMOS transistor MP1 and turn on the NMOS transistor MN1, the input high voltage passes through the conducting diode D2 to GND; the output of the output terminal VOUT is a low voltage equal to the sum of the conduction voltage drops of the diode D2 and the NMOS transistor MN1, approximately equal to GND.

[0073] When a low voltage is input at the voltage input terminal VIN to turn on the PMOS transistor MP1 and turn off the NMOS transistor MN1, the power supply VDD passes through the conducting diode D1 and the conducting PMOS transistor MP1, and the output of the output terminal VOUT is a high voltage equal to the power supply VDD minus the voltage drops of the conducting diode D1 and the PMOS transistor MP1, approximately equal to the power supply VDD.

[0074] When the input terminal VIN and the output terminal VOUT are connected, the output voltage of the output terminal VOUT is approximately VDD / 2.

[0075] Due to process variations, each bit cell circuit U m outputs a metastable state that is non-linearly distributed around VDD / 2.

[0076] Embodiment 2

[0077] An embodiment of the present invention discloses a PUF code generator, as Figure 4 shown, including:

[0078] N PUF cores arranged in parallel; each PUF core is used to generate a 1-bit PUF code; the N PUF cores generate a total of N-bit PUF codes [OUT_1,..., OUT_N];

[0079] Each PUF core includes: a monostable feedback module, a reinforcement verification module, and a digitization module; among them,

[0080] The monostable feedback module is used to generate the voltage value T from which the 1-bit PUF code of this PUF core is derived; the voltage values T in each PUF core are non-linearly distributed;

[0081] The reinforcement verification module is used to drive the voltage value T step by step and output the voltage Y;

[0082] A digitalization module is used to digitalize the output voltage Y and output the 1-bit PUF code of this PUF core.

[0083] Specifically, the monostable feedback module in each PUF core uses the monostable feedback device as described in Embodiment 1.

[0084] Specifically, as Figure 5 shown, the strengthening verification module in each PUF core includes a multi-stage cascaded bit unit circuit; the input end of the first-stage bit unit circuit in the cascade is connected to the output end T of the monostable feedback module, and the output voltage Y is output from the output end of the last-stage bit unit in the cascade.

[0085] Each stage of the bit unit circuit can act as a single-ended comparator to compare its input voltage with its own flip voltage V trip for comparison; the cascaded bit unit circuits amplify the deviation of its input voltage relative to its own flip voltage V trip step by step, and finally output the output voltage Y close to VDD or GND.

[0086] In a specific solution of this embodiment, the strengthening verification module includes at least 5 stages of bit unit circuits, so that the voltage values of the output voltages Y of the strengthening verification modules of almost all PUF cores satisfy: near VDD or GND, and the proportion of the Y values of different PUF cores distributed near VDD or GND is close to 50%.

[0087] Specifically, as Figure 6 shown, the digitalization module circuit includes a Buf module; the input end of the Buf module is connected to the output end Y of the strengthening verification module, and the output end outputs the 1-bit PUF code OUT.

[0088] When the voltage value of the output voltage Y is near VDD, the Buf module outputs "1".

[0089] When the voltage value of the output voltage Y is near GND, the Buf module outputs "0".

[0090] In a preferred solution, the PUF code generator of this embodiment further includes a digital logic circuit; as Figure 7 shown, the digital logic circuit is respectively connected to the monostable feedback modules in each PUF core to provide gating control for M double-open single-control switches in each monostable feedback module.

[0091] In a more preferred embodiment, different gating control logics are configured for the M double-pole single-throw switches in the monostable feedback module of each PUF core through digital logic circuits, and bit cell circuits at the same or different positions and in the same or different numbers are gated in the monostable feedback modules of different PUF cores; thereby, different voltage values T are output by the monostable feedback modules in each PUF core, and after passing through the enhanced verification module and the digitization module, a PUF code is finally obtained; by changing the gating control logic in the digital logic circuit, a strong PUF is realized.

[0092] In summary, in the embodiment of the present invention, through the gating control of the double-pole single-throw switches in the monostable feedback device, bit cell circuits at the same or different positions and in the same or different numbers in the monostable feedback devices of different PUF cores are combined to work, so that the output voltages of the monostable feedback devices of each PUF core are different, that is, PUF codes from different sources, and finally a unique PUF code is obtained. The response time of this PUF code generator is short, and the response value is not affected by the power-on initial value; by changing the gating control of the double-pole single-throw switches in the monostable feedback device multiple times, the sources of the PUF codes are made richer, so as to generate more types of PUF codes and obtain a strong PUF. Its excitation response grows exponentially relative to the PUF with a finite type of excitation response pair, and it has a small overhead and strong anti-attack ability.

[0093] Embodiment III

[0094] An embodiment of the present invention discloses a PUF generation method using the PUF code generator in the above embodiment; specifically, it includes the following steps:

[0095] Step S1: Initialize the PUF code generator, and set PUF working conditions including the supply voltage VDD and excitation gating control.

[0096] Step S2: After the power supply works stably, perform gating logic control on the M double-pole single-throw switches in the monostable feedback modules of the N PUF cores in the PUF code generator, and gate bit cell circuits at the same or different positions and in the same or different numbers in the monostable feedback modules of different PUF cores.

[0097] Step S3: After each PUF core works, output a PUF code of N bits.

[0098] Step S4: Extract the PUF code of N bits output in Step S3.

[0099] In addition, this embodiment also discloses another PUF code generation method using the PUF code generator in the above embodiment, including:

[0100] Step S1: Initialize the PUF code generator and set the PUF operating conditions including the supply voltage VDD and the excitation gating control;

[0101] Step S2: After the power supply operates stably, perform gating logic control on the M double-open single-control switches in the monostable feedback device of each PUF core in the PUF code generator, and gate the bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback devices of different PUF cores;

[0102] Step S3: After each PUF core operates, output the first group of N Bit PUF codes;

[0103] Step S4: Extract the N Bit PUF codes output in Step S3;

[0104] Step S5: Disconnect the power supply, power on again, and after the power supply is stable, change the positions and quantities of the gated bit cell circuits in the monostable feedback device of each PUF core;

[0105] Step S6: After each PUF core operates, output the second group of N Bit PUF codes;

[0106] Step S7: Extract the N Bit PUF codes output in Step S6;

[0107] Step S8: Repeat Steps S5, S6, and S7 multiple times to obtain multiple groups of PUF codes without changing the circuit scale, thereby implementing a strong PUF.

[0108] For the relevant technical details of the PUF code generator, please refer to Embodiment 2 and will not be elaborated here one by one.

[0109] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A monostable feedback device in a PUF code generator, characterized in that, The monostable feedback device includes M double-pole single-throw switches C1 to C M , and M bit cell circuits U1 to U M ; The bit unit circuit is used to reverse the voltage and output the reversed voltage from the input terminal at the output terminal. The double-pole single-control switch C m of the first switch C m-1 of the second terminal, the second switch C m-2 of the first terminal are respectively connected to the input terminal and the output terminal of the bit unit circuit U m ; The first node where the first connection terminals of the first switches of all double-pole single-throw switches are connected together is connected to the second node where the second connection terminals of the second switches of all double-pole single-throw switches are connected together, and the second node serves as the output terminal of the monostable feedback device; m = 1, …, M.

2. The monostable feedback device in the PUF code generator according to claim 1, wherein The bit unit circuit includes: an inverter circuit INV, a first auxiliary adjustment circuit, and a second auxiliary adjustment circuit; The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary adjustment circuit, and a node connected to the second auxiliary adjustment circuit; A first auxiliary adjustment circuit is connected between the node where the inverter circuit is connected to the first auxiliary adjustment circuit and the power supply VDD; a second auxiliary adjustment circuit is connected between the node connected to the second auxiliary adjustment circuit and the ground GND; The input voltage Vin applied to the voltage input terminal is inverted by the inverter circuit INV and the voltage Vout is output from the voltage output terminal; The first auxiliary adjustment circuit and the second auxiliary adjustment circuit are used to limit the current and divide the voltage of the bit unit circuit.

3. The monostable feedback device in the PUF code generator according to claim 2, wherein The first auxiliary adjustment circuit and the second auxiliary adjustment circuit are electronic devices or circuits with current-limiting and voltage-dividing functions including resistors and MOS diodes, and are used to limit the current and divide the voltage of the bit unit circuit.

4. A PUF code generator, characterized in that, It includes N PUF cores arranged in parallel; each PUF core is used to generate a 1-bit PUF code; the N PUF cores generate an N-bit PUF code in total; Each PUF core includes: a monostable feedback module, a strengthening verification module, and a digitization module; wherein, The monostable feedback module is used to generate the voltage value T that is the source of the 1-bit PUF code of this PUF core; the voltage values T in each PUF core are distributed in a non-linear pattern; The strengthening verification module is used to drive the voltage value T step by step and output the voltage Y; The digitization module is used to digitize the output voltage Y and output the 1-bit PUF code of this PUF core; The monostable feedback modules in the N PUF cores all adopt the monostable feedback device according to any one of claims 1-3.

5. The PUF code generator according to claim 4, wherein The PUF code generator further includes a digital logic circuit; the digital logic circuit is respectively connected to the monostable feedback modules in each PUF core to provide gating control for the M double-pole single-throw switches in each monostable feedback module.

6. The PUF code generator according to claim 5, wherein Configure different gating control logics for M double-pole single-throw switches in the monostable feedback module of each PUF core through digital logic circuits, and gate bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback modules of different PUF cores; the monostable feedback modules in each PUF core output different voltage values T, and after passing through the enhancement verification module and the digitization module, a PUF code is finally obtained; by changing the gating control logic in the digital logic circuit, a strong PUF is realized.

7. The PUF code generator according to claim 4, characterized in that the enhancement verification module includes cascaded bit cell circuits; the input end of the first-stage bit cell circuit in the cascade is connected to the output end T of the monostable feedback module, and the output end of the last-stage bit cell in the cascade outputs voltage Y; Each stage of the bit cell circuit acts as a single-ended comparator, comparing its input voltage with its own flip voltage Vtrip; the cascaded bit cell circuits gradually amplify the deviation of their input voltage from their own flip voltage Vtrip, and the outputs of the cascaded bit cell circuits gradually approach VDD or GND, and finally output an output voltage Y approximately equal to VDD or GND.

8. The PUF code generator according to claim 4, characterized in that the digitization module circuit includes a Buf module; the input end of the Buf module is connected to the output end Y of the enhancement verification module, and the output end outputs a 1Bit PUF code OUT; When the voltage value of the output voltage Y is near VDD, the Buf module outputs "1"; When the voltage value of the output voltage Y is near GND, the Buf module outputs "0".

9. A PUF code generation method using the PUF code generator according to any one of claims 4-8, characterized in that, Including: Step S1: Initialize the PUF code generator, and set PUF working conditions including the supply voltage VDD and the excitation gating control; Step S2: After the power supply works stably, perform gating logic control on the M double-pole single-throw switches in the monostable feedback modules of the N PUF cores in the PUF code generator, and gate bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback modules of different PUF cores; Step S3: After each PUF core works, output an N Bit PUF code; Step S4: Extract the N Bit PUF code output in Step S3.

10. A PUF code generation method using the PUF code generator according to any one of claims 4-8, characterized in that, Including: Step S1: Initialize the PUF code generator, and set PUF working conditions including the supply voltage VDD and the excitation gating control; Step S2: After the power supply works stably, perform gating logic control on the M double-pole single-throw switches in the monostable feedback devices of each PUF core in the PUF code generator respectively, and gate bit cell circuits at the same or different positions and in the same or different quantities in the monostable feedback devices of different PUF cores; Step S3: After each PUF core works, output a first group of N Bit PUF codes; Step S4: Extract the N Bit PUF code output in Step S3; Step S5: Disconnect the power supply, power on again, and after the power supply is stable, change the positions and quantities of the gated bit cell circuits in the monostable feedback devices of each PUF core; Step S6: After each PUF core works, output a second set of N-bit PUF codes; Step S7: Extract the N-bit PUF codes output in Step S6; Step S8: Repeat Steps S5, S6, and S7 multiple times. Without changing the circuit scale, obtain multiple sets of PUF codes, thereby implementing a strong PUF.

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