Integrated circuit device and manufacturing method thereof

Abstract

An integrated circuit device and a method of manufacturing the same are provided. The integrated circuit device includes: a first semiconductor substrate having a front surface and a back surface opposite to each other; a FEOL structure on the front surface of the first semiconductor substrate; a first BEOL structure on the FEOL structure; a second BEOL structure on a back surface of the first semiconductor substrate; and a second semiconductor substrate spaced apart from the first semiconductor substrate in the vertical direction across the FEOL structure and the first BEOL structure. The second semiconductor substrate is partially bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and a local bonding region bonded to the first BEOL structure.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0001553, filed with the Korean Intellectual Property Office on January 4, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The inventive concept relates to an integrated circuit (IC) device and / or a method of manufacturing the same, and more particularly, to an IC device including a back - side power delivery network (BSPDN) structure and / or a method of manufacturing the IC device, the BSPDN structure including a wiring structure formed on the back side of a substrate. Background art

[0004] With the development of electronic technology, the miniaturization of IC devices has advanced rapidly. Accordingly, research has been conducted on more efficiently designing a wiring structure to achieve high integration while ensuring or helping to ensure the functions and operating speeds required for IC devices. Alternatively or additionally, in IC devices manufactured using a semiconductor substrate, as the semiconductor substrate gradually becomes thinner and the size of the patterns to be formed on the semiconductor substrate decreases, it becomes more necessary to develop an IC device and / or a method of manufacturing the IC device having a new structure in which patterns formed at different vertical levels have good or excellent overlay accuracy.

[0005] or in which the overlay error in patterns formed at different vertical levels on the semiconductor substrate is minimized. Summary of the invention

[0006] Various example embodiments may provide an integrated circuit (IC) device having a structure capable of improving overlay accuracy by minimizing or reducing the bending deformation of a semiconductor device and the overlay error in patterns formed at different vertical levels on a semiconductor substrate even when the semiconductor substrate gradually becomes thinner and / or the size of the patterns to be formed on the semiconductor substrate decreases.

[0007] Alternatively or additionally, various example embodiments may provide a method of manufacturing an IC device that improves overlay accuracy by reducing or minimizing process defects caused by the bending deformation of a semiconductor device and / or the overlay error in patterns formed at different vertical levels on a semiconductor substrate even when the semiconductor substrate gradually becomes thinner and / or the size of the patterns to be formed on the semiconductor substrate decreases. Accordingly, the method may improve the critical dimension (CD) uniformity of the patterns required for manufacturing the IC device and allow for the manufacture of reliable IC devices.

[0008] According to various example embodiments, an IC device is provided, including: a first semiconductor substrate having a front surface and a back surface opposite to each other; a front-end-of-line (FEOL) structure on the front surface of the first semiconductor substrate, the FEOL structure including a plurality of fin-shaped active regions; a first back-end-of-line (BEOL) structure on the FEOL structure, the first BEOL structure being vertically spaced apart from the first semiconductor substrate, with the FEOL structure between the first BEOL structure and the first semiconductor substrate; a second BEOL structure on the back surface of the first semiconductor substrate, the second BEOL structure being vertically spaced apart from the FEOL structure, with the first semiconductor substrate between the second BEOL structure and the FEOL structure; and a second semiconductor substrate vertically spaced apart from the first semiconductor substrate, with the FEOL structure and the first BEOL structure between the second semiconductor substrate and the first semiconductor substrate. The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure. The main surface of the second semiconductor substrate defines a local trench region in which a plurality of trenches are arranged in a regular pattern and a plurality of local bonding regions bonded to the first BEOL structure.

[0009] Alternatively or additionally, according to various example embodiments, an IC device is provided, including: a first semiconductor substrate having a front surface and a back surface opposite to each other; a front-end-of-line (FEOL) structure on the front surface of the first semiconductor substrate, the FEOL structure including a plurality of fin-shaped active regions; a first back-end-of-line (BEOL) structure on the FEOL structure, the first BEOL structure being vertically spaced apart from the first semiconductor substrate, with the FEOL structure between the first BEOL structure and the first semiconductor substrate; a second BEOL structure on the back surface of the first semiconductor substrate, the second BEOL structure being vertically spaced apart from the FEOL structure, with the first semiconductor substrate between the second BEOL structure and the FEOL structure; and a second semiconductor substrate vertically spaced apart from the first semiconductor substrate, with the FEOL structure and the first BEOL structure between the second semiconductor substrate and the first semiconductor substrate, the second semiconductor substrate having a main surface locally bonded to the first BEOL structure. The main surface of the second semiconductor substrate and the first BEOL structure together define a plurality of air gaps, and define a plurality of local trench regions in which a plurality of trenches are arranged in a regular pattern and a plurality of local bonding regions bonded to the first BEOL structure.

[0010] Alternatively or additionally, according to various example embodiments, there is provided an integrated circuit (IC) device including: a first semiconductor substrate having a front surface and a back surface opposite to each other; a front-end-of-line (FEOL) structure including fin-type active regions integrally connected to the first semiconductor substrate, gate lines located on the fin-type active regions, and at least one nanosheet between the fin-type active regions and the gate lines, the at least one nanosheet being surrounded by the gate lines; a first back-end-of-line (BEOL) structure on the FEOL structure, the first BEOL structure being vertically spaced apart from the first semiconductor substrate, the FEOL structure being between the first BEOL structure and the first semiconductor substrate, and the first BEOL structure including a front wiring structure; a second BEOL structure on the back surface of the first semiconductor substrate, the second BEOL structure being vertically spaced apart from the FEOL structure, the first semiconductor substrate being between the second BEOL structure and the FEOL structure, the second BEOL structure including a back wiring structure; and a second semiconductor substrate vertically spaced apart from the first semiconductor substrate, the FEOL structure and the first BEOL structure being between the second semiconductor substrate and the first semiconductor substrate. The second semiconductor substrate faces a main surface that faces the first BEOL structure, the main surface defining a first local trench region and a second local trench region that extend longitudinally in directions intersecting each other and a plurality of local bonding regions bonded to the first BEOL structure. A plurality of trenches are arranged in a regular pattern in each of the first local trench region and the second local trench region, and an area occupied by the plurality of trenches in a unit area of the main surface is 20% or less.

[0011] Alternatively or additionally, according to various example embodiments, there is provided a method of manufacturing an IC device. The method includes: forming a front-end-of-line (FEOL) structure on a front surface of a first semiconductor substrate having a front surface and a back surface opposite to the front surface; forming a first back-end-of-line (BEOL) structure on the FEOL structure; forming a second semiconductor substrate having a main surface in which a plurality of trenches are arranged in a regular pattern; bonding a surface other than the plurality of trenches of the main surface of the second semiconductor substrate to the first BEOL structure at a position where the main surface of the second semiconductor substrate faces the first BEOL structure in a vertical direction, and thus, the first BEOL structure is bonded to the second semiconductor substrate; polishing the first semiconductor substrate from the back surface of the first semiconductor substrate at least partially when the first BEOL structure is bonded to the second semiconductor substrate to reduce the thickness of the first semiconductor substrate; and forming a second BEOL structure on the polished back surface of the first semiconductor substrate at least partially when the first BEOL structure is bonded to the second semiconductor substrate. Description of the Drawings

[0012] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] In the figures:

[0014] Figure 1 is a plan view of a cell block of an integrated circuit (IC) device according to various exemplary embodiments;

[0015] Figure 2 is a cross-sectional view of an IC device according to various exemplary embodiments;

[0016] Figure 3A is a plan view of a first wafer that can be used to form a first semiconductor substrate to be included in an IC device according to various exemplary embodiments;

[0017] Figure 3B is a plan view of a second wafer that can be used to form a second semiconductor substrate to be included in an IC device according to various exemplary embodiments;

[0018] FIG. 4A to FIG. 4C is Figure 3B a detailed view of the second wafer shown, in which: Figure 4A is Figure 3B an enlarged plan view of the region "EX3" of; Figure 4B is along Figure 4A the line DX - DX' of

[0019] a cross-sectional view taken, and Figure 4C is along Figure 4A the line DY - DY' of a cross-sectional view taken;

[0020] Figure 5 is Figure 2 an enlarged cross-sectional view of a partial region "EX1" of;

[0021] Figure 6 is a cross-sectional view of an IC device according to various exemplary embodiments;

[0022] Fig. 7A is a cross-sectional view of an IC device according to various exemplary embodiments;

[0023] Figure 7B is for forming a second semiconductor substrate to be included in the Fig. 7A plan view of a second wafer of the IC device shown;

[0024] Figure 7C is Figure 7B an enlarged plan view of the region "EX4" of;

[0025] Fig. 8A is a planar layout view of a partial region of an IC device according to various exemplary embodiments;

[0026] Figure 8B is a cross-sectional view taken along line X1-X1' of Fig. 8A ;

[0027] Figure 8C is a cross-sectional view taken along line Y1-Y1' of Fig. 8A ;

[0028] Fig.8D is a cross-sectional view taken along line Y2-Y2' of Fig. 8A ;

[0029] Fig. 9A is a plan view of a partial area of an IC device according to various exemplary embodiments;

[0030] Fig. 9B is a cross-sectional view taken along line X4-X4' of Fig. 9A ;

[0031] Fig. 9C is a cross-sectional view taken along line Y4-Y4' of Fig. 9A ;

[0032] Fig.10 is a flowchart of a method of manufacturing an IC device according to various exemplary embodiments;

[0033] FIG. 11A to FIG. 11E is a cross-sectional view showing a process sequence of a method of manufacturing an IC device according to various exemplary embodiments;

[0034] Fig. 12A and Fig. 12B are cross-sectional views showing a process sequence of a method of bonding a first back-end-of-line (BEOL) structure to a second semiconductor substrate 104 in a method of manufacturing an IC device according to various exemplary embodiments, wherein

[0035] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D are diagrams for explaining a superposition key according to various exemplary embodiments, which can be used to measure the overlap between a pattern included in a front-end-of-line (FEOL) structure and a pattern included in a second BEOL structure in a method of manufacturing an IC device, wherein Fig.13A is a plan view of a partial area of an FEOL structure according to an embodiment, Fig. 13B is a plan view of a partial area of a second BEOL structure according to an embodiment, Fig. 13C is a plan view of a superposition key obtained from a resulting structure in which at least a part of a second BEOL structure is formed, Fig.13D is a cross-sectional view taken along lines X1-X1' and X2-X2' of Fig. 13C ;

[0036] Fig.14A and Fig. 14B each shows a superimposed simulation diagram showing the measurement results of the overlap between the patterns included in the FEOL structure and the patterns included in the second BEOL structure in an IC device according to various exemplary embodiments;

[0037] Fig. 14C shows a superimposed simulation diagram showing the measurement results of the overlap between the patterns included in the FEOL structure and the patterns included in the second BEOL structure in an IC device according to a comparative example. DETAILED DESCRIPTION

[0038] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used in the drawings to denote the same elements, and their repeated description is omitted.

[0039] Figure 1 is a plan view of a unit block 12 of an integrated circuit (IC) device 10 according to various exemplary embodiments.

[0040] Referring to Figure 1 , the unit block 12 of the IC device 10 may include a plurality of unit LCs, each unit LC including circuit patterns configured to constitute various circuits or included in various circuits. The plurality of unit LCs may be arranged in a matrix form in the unit block 12 in the width direction (or Figure 1 the X direction in Figure 1 the Y direction in).

[0041] Each of the plurality of unit LCs may constitute a logic unit. Each of the plurality of unit LCs may include circuit patterns having a layout designed according to placement and routing (PnR) technology to perform at least one logic function. The plurality of unit LCs may perform various logic functions. In some exemplary embodiments, the plurality of unit LCs may include a plurality of standard cells. In some exemplary embodiments, at least some of the plurality of unit LCs may perform the same logic function. In some exemplary embodiments, at least some of the plurality of unit LCs may perform different logic functions.

[0042] The multiple units LC may include various types of logic units, which include multiple circuit elements. For example, each of the multiple units LC may include one or more of AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MXT / MXIT, OAI, AO, AOI, D flip-flop, reset flip-flop, master-slave flip-flop, latch, or a combination thereof, or be included in one or more of AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MXT / MXIT, OAI, AO, AOI, D flip-flop, reset flip-flop, master-slave flip-flop, latch, or a combination thereof, without limitation thereto.

[0043] In the unit block 12, at least some of the multiple units LC forming a row R11, R12, R13, R14, R15, or R16 in the width direction (or Figure 1 the X direction in ) may have the same width as each other. Alternatively or additionally, at least some of the multiple units LC forming a row R11, R12, R13, R14, R15, or R16 may have the same height as each other. However, the exemplary embodiments are not limited to Figure 1 those shown. At least some of the multiple units LC forming a row R11, R12, R13, R14, R15, or R16 may have different widths and / or heights from each other.

[0044] The area of each of the multiple units LC included in the unit block 12 of the IC device 10 may be defined by the unit boundary CBD. A unit boundary contact portion CBC where the respective unit boundaries CBD of two adjacent units LC adjacent to each other in the width direction (or Figure 1 the X direction in ) or the height direction (or Figure 1 the Y direction in ) intersect each other may be between the two adjacent units LC.

[0045] In various exemplary embodiments, among a plurality of unit LCs forming a row R11, R12, R13, R14, R15, or R16, two unit LCs adjacent to each other in the width direction may contact each other at a unit boundary contact portion CBC without a distance therebetween. In some exemplary embodiments, among a plurality of unit LCs forming a row R11, R12, R13, R14, R15, or R16, two unit LCs adjacent to each other in the width direction may be separated from each other by a predetermined distance.

[0046] In various exemplary embodiments, among a plurality of unit LCs forming a row R11, R12, R13, R14, R15, or R16, two adjacent unit LCs may perform the same function as each other. In this case, the two adjacent unit LCs may have the same structure as each other. In some exemplary embodiments, among a plurality of unit LCs forming a row R11, R12, R13, R14, R15, or R16, two adjacent units may perform different functions from each other.

[0047] In various exemplary embodiments, a unit LC selected from among a plurality of unit LCs included in a unit block 12 of an IC device 10 may have a structure symmetric to that of another unit LC adjacent to the selected unit LC in the height direction (or Figure 1 the Y direction in ) with respect to a unit boundary contact portion CBC, where the unit boundary contact portion CBC is located between the selected unit LC and the other unit LC. For example, a reference logic unit LC_R in the third row R13 may have a structure symmetric to that of a lower logic unit LC_L in the second row R12 with respect to a unit boundary contact portion CBC located between the reference logic unit LC_R and the lower logic unit LC_L in the second row R12. Additionally, the reference logic unit LC_R in the third row R13 may have a structure symmetric to that of an upper logic unit LC_H in the fourth row R14 with respect to a unit boundary contact portion CBC located between the reference logic unit LC_R and the upper logic unit LC_H in the fourth row R14.

[0048] Although Figure 1 an example showing that the unit block 12 includes six rows R11, R12, R13, R14, R15, and R16 is illustrated, the exemplary embodiments are not limited thereto. The unit block 12 may include various numbers of rows selected as needed or desired, and one row may include various numbers of logic units selected as needed or desired.

[0049] A selected one of a plurality of ground lines VSS and a plurality of power supply lines VDD may be between a plurality of rows (e.g., R11, R12, R13, R14, R15, and R16), and each of the plurality of rows includes in the width direction (or Figure 1A plurality of unit LCs arranged in a line in the X direction (in the X direction) therein. A plurality of ground lines VSS and a plurality of power supply lines VDD may each extend in a first lateral direction (X direction) and may be alternately arranged spaced apart from each other in a second lateral direction (Y direction). Accordingly, the plurality of ground lines VSS and the plurality of power supply lines VDD may each overlap with the unit boundary CBD of the unit LCs in the second lateral direction (Y direction).

[0050] Figure 2 is a cross-sectional view of an IC device 100 according to various exemplary embodiments. Referring to Figure 2 The components of the IC device 100 described may constitute Figure 1 a part of the plurality of unit LCs shown or be included in Figure 1 a part of the plurality of unit LCs shown.

[0051] Referring to Figure 2 , the IC device 100 may include a first semiconductor substrate 102 and a second semiconductor substrate 104 that overlap each other in a vertical direction (Z direction). The first semiconductor substrate 102 may have a front surface 102F and a back surface 102B that face each other. The second semiconductor substrate 104 may have a main surface 104S facing the front surface 102F of the first semiconductor substrate 102. Each of the first semiconductor substrate 102 and the second semiconductor substrate 104 may include a silicon substrate; however, the exemplary embodiments are not limited thereto, and either or both of the first semiconductor substrate 102 and the second semiconductor substrate 104 may be or may include other materials such as III-V materials.

[0052] A front-end-of-line (FEOL) structure FS may be on the front surface 102F of the first semiconductor substrate 102. The FEOL structure FS may include a plurality of fin-shaped active regions integrally connected to the first semiconductor substrate 102 (e.g., FIG. 8A to FIG. 8D the fin-shaped active region F1 shown). The FEOL structure FS may include components required or used to constitute a logic unit or included in a logic unit. For example, the FEOL structure FS may include a plurality of active regions, a plurality of source / drain regions, a plurality of gate lines, and a plurality of wiring structures configured to selectively connect the plurality of active regions, the plurality of source / drain regions, and the plurality of gate lines to each other and / or to the outside.

[0053] A first back-end-of-line (BEOL) structure BS1 may be on the FEOL structure FS. The first BEOL structure BS1 may be spaced apart from the first semiconductor substrate 102 in a vertical direction (Z direction), with the FEOL structure FS between the first BEOL structure BS1 and the first semiconductor substrate 102.

[0054] The second BEOL structure BS2 can be on the back surface 102B of the first semiconductor substrate 102. The second BEOL structure BS2 can be separated from the FEOL structure FS in the vertical direction (Z direction), with the first semiconductor substrate 102 between the second BEOL structure BS2 and the FEOL structure FS. The second semiconductor substrate 104 can be separated from the first semiconductor substrate 102 in the vertical direction (Z direction), with the FEOL structure FS and the first BEOL structure BS1 between the second semiconductor substrate 104 and the first semiconductor substrate 102.

[0055] In various example embodiments, Figure 2 the illustrated IC device 100 can form part of (or be included in) one or more of the following: a logic chip, such as an analog-to-digital converter (ADC) and / or an application-specific IC (ASIC); a memory chip, such as a volatile memory (e.g., dynamic random access memory (DRAM)), a non-volatile memory (e.g., read-only memory (ROM)), and a flash memory; an application processor chip, such as a central processor (e.g., central processing unit (CPU)), a graphics processor (e.g., graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller; and / or a power management chip, such as a power management IC (PMIC).

[0056] Figure 3A is available for forming Figure 2 a plan view of the first wafer 102W of the illustrated first semiconductor substrate 102, Figure 3B is available for forming Figure 2 a plan view of the second wafer 104W of the illustrated second semiconductor substrate 104. The size (or diameter) of either or both of the first wafer 102W or the second wafer 104W can be 300 mm; however, example embodiments are not limited thereto, and the size (or diameter) of either or both of the first wafer 102W can be greater than or less than 300 mm (e.g., 200 mm or 450 mm). In various example embodiments, the first wafer 102W can have the same diameter as the second wafer 104W; however, example embodiments are not limited thereto.

[0057] In various example embodiments, Figure 2 the illustrated first semiconductor substrate 102 can correspond to Figure 3A at least a portion of the illustrated first wafer 102W, and Figure 2 the illustrated second semiconductor substrate 104 can correspond to Figure 3BAt least a portion of the second wafer 104W shown. As used herein, the first wafer 102W may be referred to as the first semiconductor substrate 102, and the second wafer 104W may be referred to as the second semiconductor substrate 104. As used herein, the features of the first wafer 102W described below may equally apply to the first semiconductor substrate 102. As used herein, the features of the second wafer 104W described below may equally apply to the second semiconductor substrate 104.

[0058] Referring Figure 2 、 Figure 3A and Figure 3B , each of the first wafer 102W and the second wafer 104W may include a plurality of irradiation regions SA each including a quadrilateral region. Each of the plurality of irradiation regions SA may refer to a region exposed by a single exposure process. The plurality of irradiation regions SA in the first wafer 102W and the plurality of irradiation regions SA in the second wafer 104W may have the same size and be located at the same positions (e.g., relative to the edges and / or notches, such as flats and / or notches 102N and / or flats and / or notches 104N). Although several irradiation regions SA are shown as extending to the edges of both the first wafer 102W and the second wafer 104W, the exemplary embodiments are not limited thereto.

[0059] In various exemplary embodiments, each of the front surface 102F of the first wafer 102W and the main surface of the second wafer 104W may include or be arranged as a (100) crystal plane, but is not limited thereto. The first wafer 102W may include a notch 102N formed on the edge of the first wafer 102W in a radial direction starting from the center 102C of the first wafer 102W. The second wafer 104W may include a notch 104N formed on the edge (of the second wafer 104W) in a radial direction starting from the center 104C of the second wafer 104W.

[0060] In various exemplary embodiments, the first semiconductor substrate 102 shown may be obtained from the first wafer 102W, Figure 2 and the second semiconductor substrate 104 shown may be obtained from the second wafer 104W. In some exemplary embodiments, in the Figure 2 IC device 100 shown, when the center 102C of the first wafer 102W and the center 104C of the second wafer 104W are on a vertical line in the vertical direction (or Figure 2 the Z direction in Figure 2 ), the notch 102N of the first wafer 102W and the notch 104N of the second wafer 104W are in the vertical direction (or Figure 2When they overlap with each other in the Z direction, and the first wafer 102W is aligned with the second wafer 104W such that the first radial direction RA1 and the second radial direction RA1 are in the same direction, a structure in which the first semiconductor substrate 102 and the second semiconductor substrate 104 are aligned can be obtained.

[0061] The second wafer 104W may include a main surface 104S facing the first BEOL structure BS1, and the main surface 104S of the second wafer 104W may be locally bonded to the first BEOL structure BS1. As Figure 3B shown, the main surface 104S of the second wafer 104W may include a plurality of local trench regions LT1 and LT2 and a plurality of local bonding regions BA bonded to the first BEOL structure BS1. In the plurality of local trench regions LT1 and LT2, a plurality of trenches (e.g., FIG. 4A to FIG. 4C the plurality of first trenches T1 and the plurality of second trenches T2 in ) are formed, for example, in a regular pattern. In the plurality of local trench regions LT1 and LT2 of the main surface 104S of the second wafer 104W, the remaining regions other than the plurality of trenches may be bonded to the first BEOL structure BS1.

[0062] FIG. 4A to FIG. 4C is Figure 3B a detailed view of the second wafer 104W shown. Figure 4A is Figure 3B an enlarged plan view of the region "EX3" of. Figure 4B is along Figure 4A the cross-sectional view taken along the line DX-DX' of, Figure 4C is along Figure 4A the cross-sectional view taken along the line DY-DY' of.

[0063] Referring to FIG. 4A to FIG. 4C , in the main surface 104S of the second wafer 104W, the plurality of local trench regions LT1 and LT2 may include a plurality of first local trench regions LT1 and a plurality of second local trench regions LT2 that extend longitudinally in different directions intersecting each other. Each of the plurality of first local trench regions LT1 may include a plurality of first trenches T1 that extend longer in the first direction (or FIG. 4A to FIG. 4C the D1 direction in ) Each of the plurality of second local trench regions LT2 may include a plurality of second trenches that extend in a second transverse direction (or FIG. 4A to FIG. 4CA plurality of second grooves T2 extending longitudinally in a second direction (the D2 direction in ). The first direction (the D1 direction) and the second direction (the D2 direction) may be perpendicular to each other; the exemplary embodiments are not limited thereto. In various exemplary embodiments, the first direction (the D1 direction) may be a direction parallel to a first radial direction from the center 104C of the second wafer 104W toward the notch 104N. The second direction (the D2 direction) may correspond to a direction parallel to a second radial direction that rotates 90° about the center 104C of the second wafer 104W from the first radial direction. The number of the first grooves T1 may be equal to, greater than, or less than the number of the second grooves T2.

[0064] As Figure 3B and Figure 4A shown, in the main surface 104S of the second wafer 104W, each of a plurality of first local groove regions LT1 and a plurality of second local groove regions LT2 may extend longer in a direction parallel to at least one side of at least one irradiation region SA.

[0065] In the main surface 104S of the second wafer 104W, a plurality of local bonding regions BA may include surfaces other than the plurality of first grooves T1 and the plurality of second grooves T2. The area occupied by the plurality of first grooves T1 and the plurality of second grooves T2 may be 20% or less of the area of the main surface 104S of the second wafer 104W. Similarly, the area occupied by the plurality of first grooves T1 and the plurality of second grooves T2 may be 20% or less of each of the plurality of irradiation regions SA included in the main surface 104S of the second wafer 104W. In various exemplary embodiments, the area occupied by the plurality of first grooves T1 and the plurality of second grooves T2 may be about 5% to about 20% of the area of the main surface 104S of the second wafer 104W, without being limited thereto. Similarly, the area occupied by the plurality of first grooves T1 and the plurality of second grooves T2 may be about 5% to about 20% of each of the plurality of irradiation regions SA included in the main surface 104S of the second wafer 104W, without being limited thereto.

[0066] As Figure 4B and Figure 4CAs shown, in the main surface 104S of the second wafer 104W, the first width TW1 of each of the plurality of first trenches T1 and the second width TW2 of each of the plurality of second trenches T2 can each be independently selected within a range of about 300 nm to about 500 nm. The first pitch P1 of the plurality of first trenches T1 disposed in each of the plurality of first local trench regions LT1 and the second pitch P2 of the plurality of second trenches T2 disposed in each of the plurality of second local trench regions LT2 can each be independently selected within a range of about 600 nm to about 1 μm. The plurality of first trenches T1 disposed in each of the plurality of first local trench regions LT1 can have a first length DL1 selected within a range of about 100 nm to about 150 nm in the vertical direction (Z direction). The plurality of second trenches T2 disposed in each of the plurality of second local trench regions LT2 can have a second length DL2 selected within a range of about 100 nm to about 150 nm in the vertical direction (Z direction).

[0067] Figure 5 is Figure 2 an enlarged cross-sectional view of a partial region “EX1”.

[0068] Referring to Figure 5 , the IC device 100 can include or define a plurality of first trenches T1 and a plurality of second trenches T2 and a plurality of air gaps AG defined by a first BEOL structure BS1. The plurality of first trenches T1 and the plurality of second trenches T2 are formed in the second semiconductor substrate 104 between the second semiconductor substrate 104 and the first BEOL structure BS1. As used herein, the term “air” can refer to a space including air and / or other gases that may be present during the manufacturing process. The air gap can be or can not be in a vacuum.

[0069] The length DA of each of the plurality of air gaps AG in the vertical direction (Z direction) can be selected within a range of about 100 nm to about 150 nm. The width TWA of each of the plurality of air gaps AG can be selected within a range of about 300 nm to about 500 nm. The pitch PA of each of the plurality of air gaps AG can be selected within a range of about 600 nm to about 1 μm. Although Figure 5 shows the plurality of air gaps AG defined by the plurality of first trenches T1, in the IC device 100, the plurality of air gaps AG defined by the plurality of second trenches T2 in regions not shown in Figure 5 can be located between the second semiconductor substrate 104 and the first BEOL structure BS1. The details of the plurality of air gaps AG defined by the plurality of second trenches T2 are substantially the same as the details of the plurality of air gaps AG defined by the plurality of first trenches T1 described with reference to Figure 5 .

[0070] Although Figure 5An example is shown in which each of the plurality of first trenches T1 and / or the plurality of air gaps AG substantially has a rectangular cross-sectional shape, but the exemplary embodiments are not limited thereto. For example, the cross-sectional shape of each or at least one of the plurality of first trenches T1 and / or the plurality of air gaps AG may have various cross-sectional shapes, such as trapezoidal, inverted trapezoidal, triangular, inverted triangular, and elliptical.

[0071] In the second semiconductor substrate 104 included in the IC device 100 described with reference to Figure 2 and the second wafer 104W described with reference to Figure 3B and FIG. 4A to FIG. 4C in each of the plurality of first trenches T1 arranged in each of the plurality of first local trench regions LT1 may be equal to or different from the second width TW2 of each of the plurality of second trenches T2 arranged in each of the plurality of second local trench regions LT2. The first pitch P1 of the plurality of first trenches T1 arranged in each of the plurality of first local trench regions LT1 may be equal to or different from the second pitch P2 of the plurality of second trenches T2 arranged in each of the plurality of second local trench regions LT2. Additionally, the first length DL1 in the vertical direction (Z direction) of the plurality of first trenches T1 arranged in each of the plurality of first local trench regions LT1 may be equal to or different from the second length DL2 in the vertical direction (Z direction) of the plurality of second trenches T2 arranged in each of the plurality of second local trench regions LT2. In the structure in which the main surface 104S of the second semiconductor substrate 104 of the IC device described with reference to Figure 2 is locally bonded to the first BEOL structure BS1, the first width TW1, the second width TW2, the first pitch P1, the second pitch P2, the first length DL1, and the second length DL2 may each be selected differently according to the required bonding energy between the second semiconductor substrate 104 and the first BEOL structure BS1.

[0072] Generally, the bonding energy between two bonded wafers can be estimated based on the Maszara model according to Equation 1. In the method of estimating the bonding energy based on the Maszara model, a sharp blade may be inserted a certain distance (e.g., dynamically determined, or alternatively, a predetermined distance) between the bonding surfaces of the two bonded wafers. In this case, the bonding strength can be calculated based on the peeling length L from the front end of the blade.

[0073] [Equation 1]

[0074] γ = 3 / 8×(Et 3 y 2 / L 4 )[J / m 2

[0075] ​Among them, γ represents the bonding strength per unit area, E represents the Young's modulus of the wafer, t represents the thickness of the wafer or the substrate, y represents 1 / 2 of the blade thickness, and L is the peeling length.

[0076] As can be seen from Equation 1, the bonding strength between the wafers can increase as the value of y in Equation 1 increases. It can be estimated that the greater the average distance between the bonded wafers, the greater the bonding strength between the wafers.

[0077] In the IC device 100 according to the inventive concept, as described above with reference to Figure 5 the main surface 104S of the second semiconductor substrate 104 can be locally bonded to the first BEOL structure BS1, and a plurality of first trenches T1 and a plurality of second trenches T2 formed in the second semiconductor substrate 104 between the second semiconductor substrate 104 and the first BEOL structure BS1 and the first BEOL structure BS1 can define a plurality of air gaps AG. Therefore, in the IC device 100, due to the plurality of air gaps AG, the average distance between the second semiconductor substrate 104 and the first BEOL structure BS1 can become greater than when the main surface 104S of the second semiconductor substrate 104 is fully bonded to the first BEOL structure BS1. Therefore, in the IC device 100, the bonding strength between the second semiconductor substrate 104 and the first BEOL structure BS1 can become greater than when the main surface 104S of the second semiconductor substrate 104 is fully bonded to the first BEOL structure BS1.

[0078] Figure 6 is a cross-sectional view of an IC device 200A according to various exemplary embodiments. In Figure 6 the same reference numerals are used to denote the same elements as in Figures 2 to 5 and thus, the repeated description thereof is omitted.

[0079] Referring to Figure 6 the IC device 200A can have substantially the same configuration as the IC device 100 described with reference to Figures 2 to 5 . However, in the IC device 200A, a plurality of first trenches T21A can be formed in the first local trench region LT1 of the second semiconductor substrate 104, and a plurality of air gaps AG2 defined by the plurality of first trenches T21A and the first BEOL structure BS1 can be disposed between the second semiconductor substrate 104 and the first BEOL structure BS1. The details of the plurality of first trenches T21A and the plurality of air gaps AG2 are substantially the same as the details of the plurality of first trenches T1 and the plurality of air gaps AG described with reference to Figure 4A and Figure 5 respectively. However, each of the plurality of first trenches T21A and the plurality of air gaps AG2 can have a trapezoidal cross-sectional shape with a lateral width increasing towards the first BEOL structure BS1.

[0080] Fig. 7A , Figure 7B and Figure 7C are diagrams of an IC device 200B according to various exemplary embodiments. Fig. 7A is a cross-sectional view of the IC device 200B. Figure 7B is a plan view of a second wafer 204W that can be used to form a second semiconductor substrate 204 to be included in the IC device 200B.

[0081] Figure 7C is Figure 7B an enlarged plan view of the region "EX4" of. In Fig. 7A , Figure 7B and Figure 7C the same reference numerals are used to denote the same elements as in Figures 2 to 5 and thus, their repeated description is omitted.

[0082] Referring to Fig. 7A , Figure 7B and Figure 7C , the IC device 200B can have a construction substantially the same as that of the IC device 100 described with reference to Figures 2 to 5 . However, the IC device 200B can include a second semiconductor substrate 204 instead of the second semiconductor substrate 104.

[0083] Fig. 7A The second semiconductor substrate 204 shown in can correspond to Figure 7B at least a portion of the second wafer 204W shown in. As used herein, the second wafer 204W can be referred to as the second semiconductor substrate 204. As used herein, the features of the second wafer 204W described below can equally apply to the second semiconductor substrate 204.

[0084] The second wafer 204W can include a notch 204N formed on the edge of the second wafer 204W in a radial direction starting from the center 204C of the second wafer 204W. The second wafer 204W can include a plurality of irradiation regions SA.

[0085] The second wafer 204W can include a main surface 204S, and the main surface 204S of the second semiconductor substrate 204 obtained from the second wafer 204W can face the first BEOL structure BS1. The main surface 204S of the second semiconductor substrate 204 can be locally bonded to the first BEOL structure BS1.

[0086] As Figure 7B and Figure 7C shown, the main surface 204S of the second wafer 204W can include a plurality of trenches formed in a regular pattern therein (e.g., Figure 7CMultiple local trench regions LT21 and LT22 of the multiple first trenches T21B and multiple second trenches T22B shown, and multiple local bonding regions BA2 bonded to the first BEOL structure BS1. The remaining regions of the multiple local trench regions LT21 and LT22 of the main surface 204S of the second wafer 204W, other than the multiple trenches, may be bonded to the first BEOL structure BS1.

[0087] In the main surface 204S of the second wafer 204W, the multiple local trench regions LT21 and LT22 may include multiple first local trench regions LT21 and multiple second local trench regions LT22 that extend longer in different directions crossing each other. Each of the multiple first local trench regions LT21 may extend longer in a direction parallel to a diagonal of at least one irradiation region SA. In various example embodiments, the multiple first local trench regions LT21 may include multiple first trenches T21B that extend longer in a direction parallel to a first diagonal of at least one irradiation region SA. The multiple second local trench regions LT22 may include multiple second trenches T22B that extend longer in a direction parallel to a second diagonal crossing the first diagonal of at least one irradiation region.

[0088] Details of the respective dimensions and / or respective cross-sectional shapes of the multiple first trenches T21B included in the multiple first local trench regions LT21 and the multiple second trenches T22B included in the multiple second local trench regions LT22 are substantially the same as the details of the respective dimensions and / or respective cross-sectional shapes of the multiple first trenches T1 and multiple second trenches T2 described with reference to Figure 4B and Figure 4C In some cases, in the IC device 200B, the cross-sectional shape of each of the multiple first trenches T21B included in the multiple first local trench regions LT21 and the multiple second trenches T22B included in the multiple second local trench regions LT22 may be a trapezoidal shape similar to the cross-sectional shape of the multiple first trenches T21A formed in the second semiconductor substrate 104 of the IC device 200A described with reference to Figure 6 Description.

[0089] In the main surface 204S of the second wafer 204W, a plurality of local bonding regions BA2 may include surfaces other than the plurality of first trenches T21B and the plurality of second trenches T22B. The area occupied by the plurality of first trenches T21B and the plurality of second trenches T22B may be 20% or less of the area of the main surface 204S of the second wafer 204W. Similarly, the area occupied by the plurality of first trenches T21B and the plurality of second trenches T22B may be 20% or less in each of the plurality of irradiation regions SA included in the main surface 204S of the second wafer 204W. In various example embodiments, the area occupied by the plurality of first trenches T21B and the plurality of second trenches T22B may be about 5% to about 20% of the area of the main surface 204S of the second wafer 204W, without being limited thereto. Alternatively or additionally, the area occupied by the plurality of first trenches T21B and the plurality of second trenches T22B may be about 5% to about 20% in each of the plurality of irradiation regions SA included in the main surface 204S of the second wafer 204W, without being limited thereto.

[0090] FIG. 8A to FIG. 8D is a diagram of an IC device 100A according to various example embodiments, showing Figure 2 a specific configuration of an example of a portion "EX2". More specifically, Fig. 8A is a plan layout diagram of a partial region of an IC device 100A according to various example embodiments. Figure 8B is Fig. 8A a cross-sectional view taken along line X1-X1' of Figure 8C is Fig. 8A a cross-sectional view taken along line Y1-Y1' of Fig.8D is Fig. 8A a cross-sectional view taken along line Y2-Y2' of. Now refer to FIG. 8A to FIG. 8D to describe an IC device 100A including a field effect transistor (FET) having a gate-all-around (GAA) structure including an active region of a nanowire and / or nanosheet type and a gate surrounding the active region. In FIG. 8A to FIG. 8D , the same reference numerals are used to denote the same elements as in Figure 2 , and thus, their repeated descriptions are omitted. In the IC device 100A, FIG. 8A to FIG. 8D the components shown may constitute Figure 1 a part of the plurality of unit LCs shown.

[0091] Refer to FIG. 8A to FIG. 8D , the first semiconductor substrate 102 may include a conductive region, such as a doped well or a doped structure.

[0092] A plurality of fin-shaped active regions F1 may protrude from the front surface 102F of the first semiconductor substrate 102 in the vertical direction (Z direction). The plurality of fin-shaped active regions F1 may extend relatively long in the first lateral direction (X direction) on the front surface 102F of the first semiconductor substrate 102 and be spaced apart from each other in a second lateral direction (Y direction) perpendicular to the first lateral direction (X direction). A plurality of trench regions 102T may be defined by the plurality of fin-shaped active regions F1 on the front surface 102F of the first semiconductor substrate 102.

[0093] As Fig. 8A shown, the IC device 100A may include a power rail region PRR. The power rail region PRR may be spaced apart from the plurality of fin-shaped active regions F1 in the second lateral direction (Y direction) and extend relatively long in the first lateral direction (X direction). In the power rail region PRR, a power rail wiring MPR may be adjacent to the back surface 102B of the first semiconductor substrate 102. In various exemplary embodiments, the power rail wiring MPR may constitute Figure 1 the ground wire VSS as shown. The power rail wiring MPR may pass through a portion of the first semiconductor substrate 102 from the back surface 102B of the first semiconductor substrate 102 in the vertical direction (Z direction). The power rail region PRR and the power rail wiring MPR may constitute Figure 2 the second BEOL structure BS2 as shown (or be included in the second BEOL structure BS2).

[0094] In various exemplary embodiments, the power rail wiring MPR may include a metal wiring layer. In some cases, the power rail wiring MPR may include a metal wiring layer and a conductive barrier film surrounding the metal wiring layer. The metal wiring layer may include ruthenium (Ru), cobalt (Co), tungsten (W), or a combination thereof. The conductive barrier film may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0095] As Figure 8C and Fig.8D shown, a device isolation film 112 may be between two adjacent fin-shaped active regions among the plurality of fin-shaped active regions F1. The device isolation film 112 may fill the plurality of trench regions 102T and cover the sidewalls of each of the plurality of fin-shaped active regions F1. The device isolation film 112 may include a silicon oxide film, but is not limited thereto.

[0096] As Figure 8B and Fig.8DAs shown, multiple gate lines 160 may be on multiple fin-type active regions F1 and device isolation films 112. The multiple gate lines 160 may extend relatively long in a second lateral direction (Y direction) to cross the multiple fin-type active regions F1 respectively. Multiple nanosheet stacks NSS may be on the fin top surfaces FF of the multiple fin-type active regions F1 in regions where the multiple fin-type active regions F1 cross the multiple gate lines 160. Each of the multiple nanosheet stacks NSS may include at least one nanosheet that is spaced apart from the fin top surface FF of the fin-type active region F1 in a vertical direction (Z direction) and faces the fin top surface FF of the fin-type active region F1. As used herein, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. The nanosheet may be interpreted to include nanowires.

[0097] Each of the multiple nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that overlap each other in a vertical direction (Z direction) on the fin-type active region F1. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may be located at different vertical distances (Z-direction distances) from the fin top surface FF of the fin-type active region F1. Each of the multiple gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 that overlap each other in a vertical direction (Z direction). Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may be used as a channel region. In various example embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may independently or jointly include a silicon (Si) layer, a silicon germanium (SiGe) layer, or a combination thereof.

[0098] As Figure 8B and Fig.8D As shown, each of the multiple gate lines 160 may include a main gate portion 160M and multiple sub-gate portions 160S. The main gate portion 160M may cover the top surface of the nanosheet stack NSS and extend relatively long in the second lateral direction (Y direction). The multiple sub-gate portions 160S may be integrally connected to the main gate portion 160M and are respectively arranged between the first to third nanosheets N1, N2, and N3 and between the first nanosheet N1 and the fin top surface FF of the fin-type active region F1.

[0099] As Figure 8B and Figure 8CAs shown, a plurality of recesses R1 may be formed in the fin-type active region F1. The lowermost surface of each of the plurality of recesses R1 may be at a vertical level lower than the fin top surface FF of the fin-type active region F1. As used herein, the term "vertical height" refers to the distance from the front surface 102F of the first semiconductor substrate 102 in the vertical direction (Z direction or -Z direction).

[0100] A plurality of source / drain regions 130 may be respectively within the plurality of recesses R1. Each of the plurality of source / drain regions 130 may be on the fin-type active region F1 and spaced apart from the front surface 102F of the first semiconductor substrate 102 in the vertical direction (Z direction), with the fin-type active region F1 between the plurality of source / drain regions 130 and the front surface 102F of the first semiconductor substrate 102. Each of the plurality of source / drain regions 130 may be adjacent to at least one gate line 160 selected from the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface in contact with the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0101] Each of the plurality of source / drain regions 130 may include an epitaxially grown semiconductor layer. In various example embodiments, each of the plurality of source / drain regions 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or an embedded SiGe structure including a plurality of epitaxially grown SiGe layers. When the source / drain region 130 constitutes an NMOS transistor, the source / drain region 130 may include a SiC layer doped with an n-type dopant. The n-type dopant may be selected from at least one of phosphorus (P), arsenic (As), and antimony (Sb); the example embodiments are not limited thereto. When the source / drain region 130 constitutes a PMOS transistor, the source / drain region 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and / or gallium (Ga); the example embodiments are not limited thereto.

[0102] Each of the plurality of gate lines 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from one or more of titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and / or tantalum nitride (TaN). The metal carbide may include titanium aluminum carbide (TiAlC). However, the materials included in the plurality of gate lines 160 are not limited to the above examples.

[0103] The gate dielectric film 152 may be between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may include a stacked structure of an interfacial dielectric film and a high-k dielectric film. The interfacial dielectric film may include a low-k dielectric material film having a dielectric constant of about 9 or less (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof). In various exemplary embodiments, the interfacial dielectric film may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to 25. The high-k dielectric film may include hafnium oxide, but is not limited thereto.

[0104] Two sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be spaced apart from the source / drain regions 130, and the gate dielectric film 152 is between the two sidewalls and the source / drain regions 130. The gate dielectric film 152 may be between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portion 160S included in the gate line 160 and the source / drain regions 130.

[0105] The plurality of nanosheet stacks NSS may be respectively located on the fin top surfaces FF of the plurality of fin-type active regions F1 in the region where the plurality of fin-type active regions F1 intersect with the plurality of gate lines 160. Each of the plurality of nanosheet stacks NSS may be spaced apart from the fin-type active region F1 and face the fin top surface FF of the fin-type active region F1. A plurality of nanosheet transistors may be formed in the portion where the plurality of fin-type active regions F1 intersect with the plurality of gate lines 160. The plurality of nanosheet transistors may include NMOS transistors, PMOS transistors, or a combination thereof.

[0106] As Figure 8B shown, two sidewalls of the gate line 160 may be covered by a plurality of insulating spacers 118. Each of the plurality of insulating spacers 118 may cover the sidewalls of the main gate portion 160M on the top surface of the nanosheet stack NSS. Each of the plurality of insulating spacers 118 may be spaced apart from the gate line 160, and the gate dielectric film 152 is between each of the plurality of insulating spacers 118 and the gate line 160. As Figure 8CAs shown, a plurality of recess side insulating spacers 119 may be on the device isolation film 112. At least some of the plurality of recess side insulating spacers 119 may cover sidewalls of the source / drain regions 130. In various example embodiments, the plurality of recess side insulating spacers 119 may be separately and integrally connected to adjacent insulating spacers 118. The plurality of insulating spacers 118 and the plurality of recess side insulating spacers 119 may each independently or simultaneously include silicon nitride, silicon oxide, silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), or a combination thereof. As used herein, each of the terms SiCN, SiBN, SiON, SiOCN, SiBCN, and SiOC refers to a material including the elements included therein, without referring to a chemical formula indicating a stoichiometric relationship.

[0107] The top surfaces of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may include a silicon nitride film.

[0108] The plurality of source / drain regions 130, the device isolation film 112, the plurality of insulating spacers 118, and the plurality of recess side insulating spacers 119 may be covered by an insulating liner 142. The inter-gate dielectric film 144 may be on the insulating liner 142. The inter-gate dielectric film 144 may be between a pair of adjacent source / drain regions 130 and between a pair of gate lines 160 adjacent to each other in a first lateral direction (X direction). In various example embodiments, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, without limitation. The inter-gate dielectric film 144 may include a silicon oxide film, without limitation. The device isolation film 112, the insulating liner 142, and the inter-gate dielectric film 144 may constitute an insulating structure.

[0109] As Figure 8B and Figure 8C shown, a plurality of source / drain contacts CA may be on the plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may be spaced apart from the front surface 102F of the first semiconductor substrate 102 in a vertical direction (Z direction), with the fin-type active region F1 and the source / drain region 130 between each of the plurality of source / drain contacts CA and the first semiconductor substrate 102.

[0110] Each of the plurality of source / drain contacts CA may be electrically connected to at least one source / drain region 130 selected from the plurality of source / drain regions 130. For example, as Figure 8CAs shown, a source / drain contact CA can be connected to two source / drain regions 130 adjacent to each other, but not limited thereto. As Fig. 8A shown, the source / drain contact CA can extend relatively long in a second lateral direction (Y direction) between a pair of gate lines 160 adjacent to each other in a first lateral direction (X direction). As Figure 8B shown, the source / drain contact CA can be separated from a main gate portion 160M of an adjacent gate line 160 in the first lateral direction (X direction), and an insulating spacer 118 is between the source / drain contact CA and the main gate portion 160M.

[0111] In various exemplary embodiments, the source / drain regions 130 and the source / drain contact CA connected to each other can be in contact with each other. In other embodiments, a metal silicide film (not shown) can be between the source / drain regions 130 and the source / drain contact CA connected to each other. The metal silicide film can include a metal, and the metal includes Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film can include titanium silicide, but not limited thereto.

[0112] In various exemplary embodiments, the source / drain contact CA can include only a metal plug containing a single metal. In other embodiments, the source / drain contact CA can include a metal plug and a conductive barrier film surrounding the metal plug. The metal plug can include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, but not limited thereto. The conductive barrier film can include a metal or a conductive metal nitride. For example, the conductive barrier film can include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbon nitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), or a combination thereof, but not limited thereto.

[0113] As Figure 8C shown, the IC device 100A can include a via power rail VPR that extends relatively long in a vertical direction (Z direction) between a power rail wiring MPR and the source / drain contact CA. The via power rail VPR can include a portion that vertically penetrates an insulating structure including a device isolation film 112, an insulating liner 142, and an inter-gate dielectric film 144, and a portion that vertically penetrates a part of a front surface 102F of the first semiconductor substrate 102. The portion of the via power rail VPR that vertically penetrates the insulating structure can include a conductive barrier film BM and a metal plug MP surrounded by the conductive barrier film BM. The via power rail VPR can constitute Figure 2 The second BEOL structure BS2 shown. The metal plug MP may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), combinations thereof, or alloys thereof, without limitation. The conductive barrier film BM may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or combinations thereof, without limitation.

[0114] The power rail wiring MPR and the via power rail VPR may form a contact structure. In the contact structure, the power rail wiring MPR may form a first plug portion passing through the first semiconductor substrate 102 in the vertical direction (Z direction), and the via power rail VPR may form a second plug portion passing through the insulating structure in the vertical direction (Z direction). Insulating spacers including inorganic materials (e.g., silicon oxide film and silicon nitride film) may be between the power rail wiring MPR and the first semiconductor substrate 102 and / or between the via power rail VPR and the insulating structure.

[0115] The top surfaces of each of the source / drain contact CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144 may be covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an upper insulating film 184 sequentially stacked on each of the source / drain contact CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144. The etch stop film 182 may include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), silicon oxycarbide (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum oxycarbide (AlOC), or combinations thereof. The upper insulating film 184 may include an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, the upper insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a silicon oxynitride (SiON) film, a silicon nitride (SiN) film, a silicon oxycarbide (SiOC) film, a SiCOH film, or combinations thereof, without limitation.

[0116] As Figure 8B and Figure 8CAs shown, the source / drain via contact VA can be on the source / drain contact CA. The source / drain via contact VA can pass through the upper insulating structure 180 and contact the source / drain contact CA. Each of the plurality of source / drain regions 130 can be electrically connected to the source / drain via contact VA through the source / drain contact CA. The bottom surface of the source / drain via contact VA can contact the top surface of the source / drain contact CA.

[0117] As Fig.8D shown, the gate contact CB can be on the gate line 160. The gate contact CB can be connected to the gate line 160 by passing through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction). The bottom surface of the gate contact CB can contact the top surface of the gate line 160.

[0118] Each of the source / drain via contact VA and the gate contact CB can include a contact plug, which includes molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof, but the constituent material of the contact plug is not limited thereto. In various exemplary embodiments, the source / drain via contact VA and the gate contact CB can further include a conductive barrier pattern surrounding a part of the contact plug. The conductive barrier pattern included in the source / drain via contact VA and the gate contact CB can include a metal or a metal nitride. For example, the conductive barrier pattern can include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, without limitation.

[0119] The top surface of each of the upper insulating structure 180, the source / drain via contact VA, and the gate contact CB can be covered by the interlayer insulating film 186. The constituent material of the interlayer insulating film 186 is substantially the same as that of the above-mentioned upper insulating film 184. A plurality of upper wiring layers M1 can pass through the interlayer insulating film 186. Each of the plurality of upper wiring layers M1 can be connected to the source / drain via contact VA or the gate contact CB located therebelow. Each of the plurality of upper wiring layers M1 can include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, without limitation.

[0120] The front wiring structure FWS can be on multiple upper wiring layers M1 and the interlayer insulating film 186. The front wiring structure FWS can include multiple wiring layers MN1, multiple via contacts CT1, and an interlayer insulating film 194 covering the multiple wiring layers MN1 and the multiple via contacts CT1. The via power rail VPR can be connected to a selected one of the multiple wiring layers MN1 through the source / drain contact CA, the source / drain via contact VA, the upper wiring layer M1, and the via contact CT1. The constituent materials of the multiple wiring layers MN1 and the constituent materials of the multiple via contacts CT1 are substantially the same as the constituent materials of the above-mentioned multiple upper wiring layers M1. The constituent material of the interlayer insulating film 194 is substantially the same as the constituent material of the above-mentioned upper insulating film 184.

[0121] The back surface 102B of the first semiconductor substrate 102 can be covered by the back insulating film 109. The back insulating film 109 can include a silicon oxide film, a silicon nitride film, a silicon carbide film, a low-k dielectric film, or a combination thereof. The low-k dielectric film can include fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon oxide, porous organosilicate glass, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof, without limitation.

[0122] The back wiring structure BWS can be on the back insulating film 109. The back wiring structure BWS can include multiple wiring layers MN2, multiple via contacts CT2, and an interlayer insulating film 196 covering the multiple wiring layers MN2 and the multiple via contacts CT2. A selected one of the multiple via contacts CT2 can have one end that contacts through the back insulating film 109, and the other end that contacts a selected one of the multiple wiring layers MN2. The power rail wiring MPR can be connected to a selected one of the multiple wiring layers MN2 through one via contact CT2. The constituent materials of the multiple wiring layers MN2 and the multiple via contacts CT2 are substantially the same as the constituent materials of the above-mentioned multiple upper wiring layers M1. The constituent material of the interlayer insulating film 196 is substantially the same as the constituent material of the above-mentioned upper insulating film 184.

[0123] 9A to 9C is a diagram of the IC device 100B according to various exemplary embodiments, showing Figure 2 a specific configuration of another example of the part "EX2". More specifically, Fig. 9A is a layout plan of a partial area of the IC device 100B. Fig. 9B is along Fig. 9A the cross-sectional view taken along the line X4-X4'. Fig. 9C is along Fig. 9A the cross-sectional view taken along the line Y4-Y4'. In 9A to 9C it, the same reference numerals are used to denote the same as Figure 2 as well as FIG. 8A to FIG. 8DSame components as those in [reference], so repeated descriptions thereof are omitted.

[0124] Referring to 9A to 9C , the IC device 100B can form Figure 1 Some of the multiple unit LCs shown. The IC device 100B can have a configuration substantially the same as that of the IC device 100A described with reference to Fig.8D . However, the IC device 100B can include a contact structure that includes a power rail wiring MPR4 and a back source / drain contact DBC.

[0125] A selected one of the multiple fin-shaped active regions F1 can include a first fin portion F1A and a second fin portion F1B. The first fin portion F1A and the second fin portion F1B are separated from each other in a first lateral direction (X direction) across the back source / drain contact DBC included in the contact structure and extend longer in a straight line in the first lateral direction (X direction). Each of the first fin portion F1A and the second fin portion F1B can have sidewalls covered by a device isolation film 112. The device isolation film 112 can form an insulating structure.

[0126] Multiple gate lines 160 can be on the multiple fin-shaped active regions F1. Each of the multiple gate lines 160 can extend longer in a second lateral direction (Y direction) that intersects the first lateral direction (X direction). Multiple nanosheet stacks NSS can be respectively above the multiple fin-shaped active regions F1 in regions where the multiple fin-shaped active regions F1 intersect with the multiple gate lines 160.

[0127] Multiple source / drain regions 130 can be on the multiple fin-shaped active regions F1. Each of the multiple source / drain regions 130 can be adjacent to at least one gate line 160 selected from the multiple gate lines 160. Each of the multiple source / drain regions 130 can be in contact with a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0128] As Fig. 9C shown, multiple recessed side insulating spacers 119 can be on the top surface of the device isolation film 112. At least some of the multiple recessed side insulating spacers 119 can cover the sidewalls of the source / drain regions 130. In various example embodiments, each of the multiple recessed side insulating spacers 119 can be integrally connected to an adjacent insulating spacer 118.

[0129] A metal silicide film 172 may be formed on the top surfaces of some selected source / drain regions among the plurality of source / drain regions 130 toward the upper insulating structure 180, and the metal silicide film 172 may be formed on the bottom surfaces of some other selected source / drain regions among the plurality of source / drain regions 130 toward the first semiconductor substrate 102. The plurality of source / drain regions 130 and the device isolation film 112 may be covered by an insulating liner 142. The inter-gate dielectric film 144 may be on the insulating liner 142.

[0130] As Fig. 9C shown, a plurality of front source / drain contacts CA4 may be on the fin-type active region F1. Each of the plurality of front source / drain contacts CA4 may be electrically connected to some of the source / drain regions 130 selected from the plurality of source / drain regions 130. Each of the plurality of front source / drain contacts CA4 may be spaced apart from the fin-type active region F1 in the vertical direction (Z direction), with the source / drain regions 130 between each of the plurality of front source / drain contacts CA4 and the fin-type active region F1.

[0131] Each of the plurality of front source / drain contacts CA4 may pass through the inter-gate dielectric film 144 and the insulating liner 142 in the vertical direction (Z direction) and contact the metal silicide film 172. As Fig. 9B shown, the front source / drain contact CA4 may be spaced apart from the main gate portion 160M of the gate line 160 in the first lateral direction (X direction), with the insulating spacer 118 between the front source / drain contact CA4 and the main gate portion 160M. The details of the front source / drain contact CA4 are substantially the same as the details of the source / drain contact CA described with reference to Figure 2 、 Figure 3A and Figure 3B described.

[0132] A plurality of back source / drain contacts DBC may be on the back surface, which is opposite to the front surface where the front source / drain contacts CA4 are located, with the plurality of source / drain regions 130 between the plurality of back source / drain contacts DBC and the front source / drain contacts CA4. Each of the plurality of back source / drain contacts DBC may be electrically connected to some other source / drain regions 130 selected from the plurality of source / drain regions 130 and not connected to the front source / drain contacts CA4.

[0133] Each of the plurality of back source / drain contacts DBC may pass through a selected one of the plurality of fin active regions F1 in the vertical direction (Z direction). As described above, the selected fin active region F1 may include a first fin portion F1A and a second fin portion F1B, which are separated from each other in the first lateral direction (X direction) across the back source / drain contact DBC and extend linearly in the first lateral direction (X direction) for a longer distance.

[0134] Among the plurality of source / drain regions 130, the source / drain region 130 connected to the front source / drain contact CA4 may be separated from the source / drain region 130 connected to the back source / drain contact DBC in the lateral direction (e.g., the first lateral direction (X direction) or the second lateral direction (Y direction)).

[0135] Each of the plurality of back source / drain contacts DBC may have sidewalls facing each of the adjacent fin active region F1 and the device isolation film 112, and each of the fin active region F1 and the device isolation film 112 is penetrated by the back source / drain contact DBC in the vertical direction (Z direction).

[0136] As Fig. 9B shown, the plurality of gate lines 160 may include a gate line 160 on the first fin portion F1A and a gate line 160 on the second fin portion F1B. Each of the plurality of front source / drain contacts CA4 may be connected to a source / drain region 130 located on the first fin portion F1A or the second fin portion F1B.

[0137] As Fig. 9C shown, the device isolation film 112 may cover two sidewalls of each of the first fin portion F1A and the second fin portion F1B in the second lateral direction (Y direction) and define the width of the contact space DBH in the second lateral direction (Y direction). The back source / drain contact DBC may overlap with the source / drain region 130 in the vertical direction (Z direction) in the contact space DBH and extend linearly in the vertical direction (Z direction) for a longer distance in the contact space DBH.

[0138] The back source / drain contact DBC may have a width that gradually increases in the vertical direction (Z direction) toward the first semiconductor substrate 102 in each of the first lateral direction (X direction) and the second lateral direction (Y direction). As Fig. 9B and Fig. 9C shown, the front source / drain contact CA4 may have a width that gradually increases in the vertical direction (Z direction) away from the first semiconductor substrate 102 in the first lateral direction (X direction) and the second lateral direction (Y direction).

[0139] The metal silicide film 192 can be between the back source / drain contact DBC and the source / drain region 130. The details of the metal silicide film 192 are substantially the same as the details of the metal silicide film 172 described above.

[0140] As Fig. 9C shown, in the contact space DBH, the sidewall of the back source / drain contact DBC facing the device isolation film 112 can be in contact with the device isolation film 112.

[0141] As Fig. 9B shown, in the contact space DBH, the insulating film 406 can be between the first fin portion F1A and the back source / drain contact DBC, and the insulating film 406 can be between the second fin portion F1B and the back source / drain contact DBC. Additionally, the insulating film 406 can be between the first semiconductor substrate 102 and the power rail wiring MPR4. The insulating film 406 can include a silicon oxide film.

[0142] In the IC device 100B, the power rail wiring MPR4 can pass through the first semiconductor substrate 102 in the vertical direction (Z direction) from the back surface 102B of the first semiconductor substrate 102 to the front surface 102F of the first semiconductor substrate 102 and be connected to the back source / drain contact DBC. The back source / drain contact DBC can include a first end connected to the power rail wiring MPR4 and a second end connected to the source / drain region 130 through the metal silicide film 192. In various example embodiments, the power rail wiring MPR4 can be integrally connected to the back source / drain contact DBC. In various example embodiments, the power rail wiring MPR4 and the back source / drain contact DBC can include the same metal. In various example embodiments, each of the power rail wiring MPR4 and the back source / drain contact DBC can include a metal plug that includes molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), a combination thereof, or an alloy thereof.

[0143] The power rail wiring MPR4 and the back source / drain contact DBC can form a contact structure. The power rail wiring MPR4 passing through the first semiconductor substrate 102 in the vertical direction (Z direction) can form a first plug portion of the contact structure, and the back source / drain contact DBC can form a second plug portion of the contact structure.

[0144] As Fig. 9B and Fig. 9CAs shown, the top surfaces of each of the plurality of front source / drain contact members CA4, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144 may be covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an upper insulating film 184. The plurality of source / drain via contact members VA may be on the plurality of front source / drain contact members CA4. Each of the plurality of source / drain via contact members VA may pass through the upper insulating structure 180 and contact the front source / drain contact member CA4. Among the plurality of source / drain regions 130, the source / drain region 130 connected to the front source / drain contact member CA4 may be electrically connected to the source / drain via contact member VA through the metal silicide film 172 and the front source / drain contact member CA4. The top surface of the upper insulating structure 180 may be covered by the interlayer insulating film 186. The plurality of upper wiring layers M1 may pass through the interlayer insulating film 186. Each of the plurality of upper wiring layers M1 may be connected to a selected one or more of the plurality of source / drain via contact members VA located therebelow and a selected one of the gate contact members (refer to Fig. 9A CB in

[0145] The front wiring structure FWS may be on the plurality of upper wiring layers M1 and the interlayer insulating film 186. The back surface 102B of the first semiconductor substrate 102 may be covered by the back insulating film 109. The back wiring structure BWS may be on the back insulating film 109.

[0146] Refer to Figures 2 to 9C Each of the IC devices 100, 100A, 100B, 200A, and 200B described may include a first semiconductor substrate 102 and a second semiconductor substrate 104, the first semiconductor substrate 102 and the second semiconductor substrate 104 being separated from each other in the vertical direction (Z direction) by the FEOL structure FS and the first BEOL structure BS1 and overlapping each other in the vertical direction (Z direction). The main surface 104S or 204S of the second semiconductor substrate 104 or 204 facing the first BEOL structure BS1 may include a plurality of trenches therein (e.g., FIG. 4A to FIG. 4C the plurality of first trenches T1 and the plurality of second trenches T2 shown, Figure 6 the plurality of first trenches T21A shown, or Figure 7CThe multiple first trenches T21B and multiple second trenches T22B shown) are multiple local trench regions LT1 and LT2 or LT21 and LT22 formed in a regular pattern, and multiple local bonding regions BA or BA2 bonded to the first BEOL structure BS1. The main surfaces 104S or 204S of the second semiconductor substrates 104 or 204 may be locally bonded to the first BEOL structure BS1 in regions other than the multiple trenches. In the IC devices 100, 100A, 100B, 200A, and 200B having the above-described configuration according to the inventive concept, even when the first semiconductor substrate 102 is gradually thinned and the pattern size to be formed on the first semiconductor substrate 102 is reduced, the bending deformation of the first semiconductor substrate 102, the overlay error between patterns formed at different levels on the first semiconductor substrate 102, or the overlay error between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 can be minimized or reduced. Therefore, the overlay accuracy can be improved. Accordingly, according to the inventive concept, the pattern critical dimension (CD) uniformity required or used for manufacturing the IC devices 100, 100A, 100B, 200A, and 200B can be improved, and / or the reliability of the IC devices 100, 100A, 100B, 200A, and 200B can be improved.

[0147] Alternatively or additionally, the IC devices 100, 100A, 100B, 200A, and 200B according to the inventive concept may include multiple air gaps AG or AG2 between the second semiconductor substrates 104 or 204 and the first BEOL structure BS1, and the multiple air gaps AG or AG2 are defined by multiple trenches formed in the second semiconductor substrates 104 or 204 and the first BEOL structure BS1. Accordingly, the bonding strength between the second semiconductor substrates 104 or 204 and the first BEOL structure BS1 can be improved, and thus, a stable bonding structure can be provided. As a result, the reliability of the IC devices 100, 100A, 100B, 200A, and 200B can be further enhanced.

[0148] Fig.10 is a flowchart of a method of manufacturing an IC device according to various example embodiments. FIG. 11A to FIG. 11E is a cross-sectional view showing a process sequence of a method of manufacturing an IC device according to various example embodiments. Refer to Fig.10 and FIG. 11A to FIG. 11E to describe the method of manufacturing the IC device 100 described with reference to Figure 2 In FIG. 11A to FIG. 11E , the same reference numerals are used to denote the same elements as in Figure 2 , and thus, their repeated description is omitted.

[0149] Refer to Fig.10 and Fig.11AIn process P302, a first semiconductor substrate 102 may be provided, and a FEOL structure FS may be formed on a front surface 102F of the first semiconductor substrate 102. The first semiconductor substrate 102 may include reference Figure 3A A first wafer 102W is described.

[0150] In various example embodiments, the FEOL structure FS may be formed to include reference FIG. 8A to FIG. 8D The components of the IC device 100A described and / or referenced 9A to 9C Components of IC device 100B are described.

[0151] Reference Fig.10 and Fig. 11B In process P304, a first BEOL structure BS1 may be formed on the FEOL structure FS. In various example embodiments, the first BEOL structure BS1 may be formed to include reference FIG. 8A to FIG. 8D and 9A to 9C The front wiring structure FWS described herein. Fig. 11B As shown, a structure in which the FEOL structure FS and the first BEOL structure BS1 are sequentially formed on the first semiconductor substrate 102 may be referred to as a first wafer structure WF1 .

[0152] exist Fig.10 In process P306, a second semiconductor substrate 104 having a main surface 104S, a plurality of trenches (eg, FIG. 4A to FIG. 4C A plurality of first trenches T1 and a plurality of second trenches T2 as shown are formed on the main surface 104S in a regular pattern. In various example embodiments, the second semiconductor substrate 104 may include reference Figure 3B and FIG. 4A to FIG. 4C A second wafer 104W is described.

[0153] In the main surface 104S of the second semiconductor substrate 104, FIG. 4A to FIG. 4C The plurality of first trenches T1 and the plurality of second trenches T2 shown may include: forming a bottom anti-reflective coating (BARC) layer on a bare wafer including silicon (Si); forming a photoresist pattern on the BARC layer; and etching a partial area of ​​the bare wafer using the photoresist pattern as an etching mask. In various example embodiments, in order to form the photoresist pattern, an exposure process using a krypton fluoride (KrF) excimer laser (248 nm) may be performed, without limitation thereto.

[0154] In some example embodiments, it may be provided Figure 6 The second semiconductor substrate 104 shown in FIG. Figure 2 The second semiconductor substrate 104 is shown. In some example embodiments, a reference 7A to 7CThe described second semiconductor substrate 204 or second wafer 204W, rather than Figure 2 the second semiconductor substrate 104 shown.

[0155] Referring to Fig.10 and Fig. 11C , in process P308, after the main surface 104S of the second semiconductor substrate 104 is aligned to face the first BEOL structure BS1, the surface of the main surface 104S of the second semiconductor substrate 104 except for a plurality of trenches (e.g., FIG. 4A to FIG. 4C the plurality of first trenches T1 and the plurality of second trenches T2 shown) can be bonded to the first BEOL structure BS1.

[0156] In various exemplary embodiments, to bond the first BEOL structure BS1 to the second semiconductor substrate 104, first, each of the bonding target surface of the first BEOL structure BS1 and the main surface 104S of the second semiconductor substrate 104 can be cleaned using plasma, and the second semiconductor substrate 104 can be bonded to the first BEOL structure BS1 under pressure such that the main surface 104A of the second semiconductor substrate 104 contacts the first BEOL structure BS1. Thereafter, an annealing process can be performed.

[0157] To perform the plasma cleaning process on the bonding target surface of the first BEOL structure BS1 and the main surface 104S of the second semiconductor substrate 104, first, plasma and deionized water can be supplied to the bonding target surface of the first BEOL structure BS1 and the main surface 104S of the second semiconductor substrate 104 in a surface treatment chamber. The process gas for forming plasma can include nitrogen, oxygen, argon, helium, or a combination thereof. The deionized water can be supplied to the surface treatment chamber simultaneously with the plasma, or the deionized water and the plasma can be supplied to the surface treatment chamber sequentially or alternately. The plasma can remove contaminants from the bonding target surface of the first BEOL structure BS1 and the main surface 104S of the second semiconductor substrate 104, and the deionized water can be used as a medium for chemical bonding. More specifically, in a vacuum state, the plasma can break the Si - O bonds in the silicon oxide film exposed to the bonding target surface of the first BEOL structure BS1 and the bonding target surface of the second semiconductor substrate 104, and thus, - Si groups can be exposed to the bonding target surface. The deionized water can supply moisture (H2O) to the bonding target surface to form - OH groups on the bonding target surface. Therefore, the - Si groups present in the bonding target surface can remain bonded to the - OH groups.

[0158] As described above, by drying the plasma - cleaned first BEOL structure BS1 and second semiconductor substrate 104, the excess moisture can be removed from the bonding target surface of each of the first BEOL structure BS1 and the second semiconductor substrate 104.

[0159] Fig. 12A and Fig. 12B is a cross-sectional view showing a process sequence of a method of bonding a first BEOL structure BS1 to be plasma-cleaned and a second semiconductor substrate 104 according to process P308 as described above according to an embodiment. Fig.10 The process sequence of the method of bonding a first BEOL structure BS1 to be plasma-cleaned and a second semiconductor substrate 104 according to process P308 as described above according to an embodiment.

[0160] Referring to Fig. 12A , in a bonding chamber maintained in a vacuum state, the second wafer 104W can be held adsorbed on the bottom surface of the upper chuck 410 included in the bonding apparatus 400, and the first wafer structure WF1 can be held adsorbed on the top surface of the lower chuck 420 included in the bonding apparatus 400. Fig. 11C The second semiconductor substrate 104 shown can be Fig. 12A at least a part of the second wafer 104W shown.

[0161] Referring to Fig. 12B , in Fig. 12A the resulting structure, the center portion of the second wafer 104W can be pushed downward in the direction of arrow AR using the pusher pin 430 included in the bonding apparatus 400 and brought into contact with the center portion of the first wafer structure WF1. As a result, due to the intermolecular force between the mutually contacting surfaces of the center portion of the second wafer 104W and the center portion of the first wafer structure WF1, the center portion of the second wafer 104W can be bonded to the center portion of the first wafer structure WF1.

[0162] When the bonding of the center portion of the second wafer 104W to the center portion of the first wafer structure WF1 starts, a bonding wave between the second wafer 104W and the first wafer structure WF1 can propagate in the radial direction from the center portions of the second wafer 104W and the first wafer structure WF1 to beyond the portion between their bonding target surfaces, and thus, the main surface 104S of the second wafer 104W can be bonded to the first BEOL structure BS1 of the first wafer structure WF1. In this case, the —Si—OH groups present on the main surface 104S of the second wafer 104W can be bonded to the —Si—OH groups present on the bonding target surface of the first BEOL structure BS1. Although van der Waals bonds occur between the —OH groups present on the respective bonding target surfaces of the second wafer 104W and the first BEOL structure BS1, moisture (H2O) may be separated between the respective bonding target surfaces of the second wafer 104W and the first BEOL structure BS1. As a result, due to the Si—O—Si bond, a plurality of local bonding regions included in the main surface 104S of the second wafer 104W (refer to FIG. 4A to FIG. 4CThe BA) in can be completely bonded to the first BEOL structure BS1. After the bonding process is completed, an annealing process can be performed in an atmosphere at a relatively high temperature. In this case, moisture (H2O) separated between the corresponding bonding target surfaces of the second wafer 104W and the first BEOL structure BS1 can be removed.

[0163] for reference Fig. 12A and Fig. 12B In the same manner as described, the process of bonding the main surface 104S of the second semiconductor substrate 104 to the first BEOL structure BS1 can be performed by using a pusher pin 430 to push down the central portion of the second wafer 104W. As a comparative example, instead of the second wafer 104W having a main surface 104S in which a plurality of trenches are formed in the method of manufacturing an IC device according to the inventive concept, when using a comparative second wafer having a planar main surface without trenches, when pushing the central portion of the comparative second wafer by using the pusher pin 430, while the bonding region between the comparative second wafer and the first wafer structure WF1 propagates from the central portion of the comparative second wafer toward its outer peripheral portion, the bonding process may be unstable, or the speed at which the bonding wave propagates outward from the central portion of the comparative second wafer may vary according to position. Therefore, the comparative second wafer may be unevenly bonded to the first wafer structure WF1 according to position. In some cases, the comparative second wafer may be deformed. Specifically, when there is anisotropy in the Young's modulus of the comparative second wafer, the degree of deformation of the comparative second wafer may be different in the direction with a high Young's modulus and the direction with a low Young's modulus. When the comparative second wafer is unevenly bonded to the first wafer structure WF1 as described above, the comparative second wafer may be locally deformed after the bonding process. When performing subsequent processes for manufacturing the IC device 100 while the comparative second wafer is unevenly bonded to the first wafer structure WF1, deterioration of the overlay between the patterns included in the first wafer structure WF1 formed after the bonding process and the patterns included in the second BEOL structure BS2 may occur.

[0164] In the method of manufacturing an IC device, according to the inventive concept, the main surface 104S of the second semiconductor substrate 104 bonded to the first BEOL structure BS1 may include a plurality of first local trench regions LT1 in which a plurality of first trenches T1 are formed in a regular pattern and a plurality of second local trench regions LT2 in which a plurality of second trenches T2 are formed. Thus, when the main surface 104S of the second semiconductor substrate 104 is according to Fig.10When the process P308 is bonded to the first BEOL structure BS1, after the bonding between the central portion of the second wafer 104W and the central portion of the first wafer structure WF1 starts, the bonding wave between the second wafer 104W and the first wafer structure WF1 can propagate outward in the radial direction at a uniform speed from the central portions of the second wafer 104W and the first wafer structure WF1 to beyond the portion between their bonding target surfaces. Therefore, the bonding process can be stably performed, and thus, the bonding state between the main surface 104S of the second semiconductor substrate 104 and the first BEOL structure BS1 can be uniform according to the position.

[0165] Referring to Fig.10 and Fig.11D , in process P310, in the resulting structure in which the first BEOL structure BS1 of Fig.11E is bonded to the second semiconductor substrate 104, the first semiconductor substrate 102 can be polished from the back surface 102B of the first semiconductor substrate 102 to reduce the thickness of the first semiconductor substrate 102. As a result, the back surface 102B of the first semiconductor substrate 102 can become relatively closer to the front surface 102F of the first semiconductor substrate 102.

[0166] In various example embodiments, at least one selected from a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, and combinations thereof can be used to polish the first semiconductor substrate 102 from the back surface 102B.

[0167] Referring to Fig.10 and Fig.11E , in process P312, in the resulting structure of Fig.11D , a second BEOL structure BS2 can be formed on the polished back surface 102B of the first semiconductor substrate 102.

[0168] In various example embodiments, the second BEOL structure BS2 can be formed to include a backside wiring structure BWS described with reference to FIG. 8A to FIG. 8D and 9A to 9C .

[0169] In various example embodiments, after polishing the first semiconductor substrate 102 according to Fig.10 process P310 and before forming the second BEOL structure BS2 according to process P312 of FIG. 12, a process of forming a contact structure including a plug portion can also be performed. The plug portion can pass through the first semiconductor substrate 102 from the polished back surface of the first semiconductor substrate 102 in the vertical direction (Z direction). For example, the process of forming the contact structure can also include: forming a contact structure including a via power rail VPR and a power rail wiring MPR described with reference to FIG. 8A to FIG. 8D , including a contact structure described with reference to 9A to 9CThe described backside source / drain contact DBC and the contact structure of the power rail routing MPR4, or contact structures of various changes and modifications thereof.

[0170] In a method of manufacturing an IC device, according to the inventive concept, even when the first semiconductor substrate 102 is gradually thinned and the pattern size to be formed on the first semiconductor substrate 102 is reduced, during the manufacturing of the IC devices 100, 100A, 100B, 200A, and 200B, process defects caused by the bending deformation of the first semiconductor substrate 102, the overlay error between patterns formed at different levels on the first semiconductor substrate 102, or the overlay error between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 can be minimized, and thus, the overlay accuracy can be improved. Therefore, in a method of manufacturing an IC device, according to the present inventive concept, by improving the CD uniformity of the patterns required for manufacturing the IC device, a reliable IC device can be provided, and / or the manufacturing yield of the IC device can be improved.

[0171] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D are diagrams for explaining an overlay key that can be used to measure the overlap between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 in the method of manufacturing an IC device described with reference to Figures 10 to 12B . More specifically, Fig.13A is a plan view of a partial region of the FEOL structure FS formed in the process P302 of Fig.10 . Fig. 13B is a plan view of a partial region of the second BEOL structure BS2 formed in the process P312 of Fig.10 . Fig. 13C is a plan view of the overlay key OVK obtained from the resulting structure in which at least a part of the second BEOL structure BS2 is formed in the process P312 of Fig.10 . Fig.13D is a cross-sectional view taken along the lines X1-X1' and X2-X2' of Fig. 13C .

[0172] As Fig.13A shown, the FEOL structure FS may include a plurality of chip regions A1. A scribe region SL may be between two adjacent regions among the plurality of chip regions A1. The plurality of chip regions A1 may include a plurality of circuit regions. The plurality of circuit regions may include, but are not limited to, a logic circuit region, a memory region, and an input / output circuit region. A plurality of first overlay patterns OVK1 may be in the scribe region SL of the FEOL structure FS. As Fig. 13BAs shown, multiple second overlay patterns OVK2 can be in a partial region of the second BEOL structure BS2. The corresponding positions of the multiple second overlay patterns OVK2 included in the second BEOL structure BS2 can correspond to the corresponding positions of the multiple first overlay patterns OVK1 included in the FEOL structure FS. The corresponding positions and numbers of the multiple second overlay patterns OVK2 included in the second BEOL structure BS2 and the multiple first overlay patterns OVK1 included in the FEOL structure FS are not limited to Fig.13A and Fig. 13B those shown, and various modifications and changes can be made as needed.

[0173] As Fig. 13C shown, after forming at least a part of the second BEOL structure BS2 according to Fig.10 process P312, an overlay key OVK can be obtained. The overlay key OVK can include a combination of the first overlay pattern OVK1 included in the FEOL structure FS and the second overlay pattern OVK2 included in the second BEOL structure BS2.

[0174] Referring to Fig. 13C and Figure 13D , the overlay key OVK can include a first overlay group to a fourth overlay group GR1, GR2, GR3, and GR4 that are adjacent to and spaced apart from each other. The first overlay group to the fourth overlay group GR1, GR2, GR3, and GR4 can each include multiple overlay patterns KX and KY including a conductive material. The multiple overlay patterns KX and KY can be spaced apart from each other by an insulating layer. The first overlay group GR1 and the third overlay group GR3 can include multiple overlay patterns KY that extend longer in the Y direction in Figure 13C , and the second overlay group GR2 and the fourth overlay group GR4 can include multiple overlay patterns KX that extend longer in the X direction in Figure 13C .

[0175] As Figure 13D (A) of shows, the first overlay group GR1 of the overlay key OVK can include a first insulating film IL1 included in the FEOL structure FS, an overlay sub-pattern KY1 surrounded by the first insulating film IL1, a second insulating film IL2 included in the second BEOL structure BS2, and an overlay sub-pattern KY2 surrounded by the second insulating film IL2. In the first overlay group GR1, the overlay sub-pattern KY1 included in the FEOL structure FS and the overlay sub-pattern KY2 included in the second BEOL structure BS2 can constitute Figure 13C the overlay pattern KY of the overlay key OVK shown. Figure 13C The third overlay group GR3 of the overlay key OVK shown can have substantially the same structure as the above first overlay group GR1.

[0176] As Figure 13DAs shown in (B) of FIG. 0, the second overlay group GR2 of the overlay key OVK may include a first insulating film IL1 included in the FEOL structure, an overlay sub-pattern KX1 surrounded by the first insulating film IL1, a second insulating film IL2 included in the second BEOL structure BS2, and an overlay sub-pattern KX2 surrounded by the second insulating film IL2. In the second overlay group GR2, the overlay sub-pattern KX1 included in the FEOL structure FS and the overlay sub-pattern KX2 included in the second BEOL structure BS2 may constitute Figure 13C the overlay pattern KX of the overlay key OVK shown in FIG. Figure 13C The fourth overlay group GR4 of the overlay key OVK shown in FIG. may have substantially the same configuration as the second overlay group GR2.

[0177] The Figure 13C overlay key OVK shown in FIG. may be used to measure the overlap between the pattern included in the FEOL structure FS and the pattern included in the second BEOL structure BS2.

[0178] Figure 14A and Figure 14B each show an overlay simulation diagram showing the measurement results of the overlap between the pattern included in the FEOL structure FS and the pattern included in the second BEOL structure BS2 in an IC device according to various exemplary embodiments.

[0179] More specifically, Figure 14A shows an overlay simulation diagram showing the measurement results of the overlap between the pattern included in the FEOL structure FS and the pattern included in the second BEOL structure BS2 in an IC device (hereinafter, "Example 1") manufactured using the second wafer 104W described with reference to Figures 10 to 11E and using the second wafer described with reference to Figure 3B and Figures 4A to 4C in an IC device (hereinafter, "Example 1") manufactured using the second wafer 104W described with reference to Figure 14B shows an overlay simulation diagram showing the measurement results of the overlap between the pattern included in the FEOL structure FS and the pattern included in the second BEOL structure BS2 in an IC device (hereinafter, "Example 2"), except that the second wafer 204W described with reference to Figure 7B and Figure 7C is used instead of the second wafer 104W, and the IC device (hereinafter, "Example 2") is manufactured by using a process similar to the process described with reference to Figures 10 to 11E in an IC device (hereinafter, "Example 2") manufactured by using a process similar to the process described with reference to

[0180] In the second wafer 104W used in Example 1, each of the plurality of first trenches T1 and the plurality of second trenches T2 has a width of 300 nm, the pitch of the plurality of first trenches T1 arranged in each of the plurality of first local trench regions LT1 is 600 nm, and the pitch of the plurality of second trenches T2 arranged in each of the plurality of second local trench regions LT2 is 600 nm. That is, each of the plurality of first trenches T1 and the plurality of second trenches T2 has a width of 300 nm, and each of the local bonding regions BA2 between the plurality of first trenches T1 and the plurality of second trenches T2 has a width of 300 nm. The depth of each of the plurality of first trenches T1 and the plurality of second trenches T2 (i.e., Figure 4A and Figure 7A the dimension in the vertical direction (Z direction) of

[0181] Figure 14C shows a superposition simulation diagram showing the measurement results of the overlap between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 in the IC device according to the comparative example. Figure 14C shows a superposition simulation diagram showing the measurement results of the overlap between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 in an IC device (hereinafter, "comparative example"). Except for using a bare wafer having a planar main surface without trenches instead of the second wafer 104W, the IC device (hereinafter, "comparative example") is manufactured by using a process similar to the process Figures 10 to 11E described.

[0182] In Figure 14A the evaluation result of Example 1 shown, the sum (M + 3σ) of the average value M of the superposition offset measured in the Figure 14A X direction of Figure 14A is about 42.4, and the sum (M + 3σ) of the average value M of the superposition offset measured in the

[0183] Y direction of Figure 14B is about 42.5. Figure 14B In Figure 14B the evaluation result of Example 2 shown, the sum (M + 3σ) of the average value M of the superposition offset measured in the

[0184] In Figure 14C the evaluation results of the comparative example shown, in Figure 14C the sum (M + 3σ) of the average value M and the standard deviation 3σ of the overlay shift measured in the X direction is about 46.2, and in Figure 14C the sum (M + 3σ) of the average value M and the standard deviation 3σ of the overlay shift measured in the Y direction is about 46.3.

[0185] From Figures 14A to 14C the results, it can be seen that compared with the comparative example, in Example 1 and Example 2, the overlap between the patterns included in the FEOL structure FS and the patterns included in the second BEOL structure BS2 is improved by about 2 nm to about 4 nm.

[0186] When the terms "about" or "substantially" are used in conjunction with numerical values in this specification, the associated numerical values are intended to include manufacturing or operating tolerances around the stated numerical values (e.g., ±10%). In addition, when the words "substantially" and "about" are used in conjunction with geometries, it is intended that the precision of the geometry is not required, but rather the magnitude of the shape is within the scope of the present disclosure. In addition, when the words "substantially" and "about" are used in conjunction with material compositions, it is intended that the accuracy of the material is not required, but rather the magnitude of the material is within the scope of the present disclosure.

[0187] Furthermore, regardless of whether numerical values or shapes are modified as "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances around the stated numerical values or shapes (e.g., ±10%). Therefore, while the terms "same" or "equal" are used in the description of the exemplary embodiments, it should be understood that there may be some imprecision. Thus, when an element or a numerical value is referred to as being the same as or equal to another element or another numerical value, it should be understood that the element or numerical value is the same as the other element or the other numerical value within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0188] Although the inventive concept has been specifically shown and described with reference to various exemplary embodiments thereof, it will be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims. In addition, the exemplary embodiments are not necessarily mutually exclusive. For example, some exemplary embodiments may include one or more features described with reference to one or more of the drawings and may also include one or more other features described with reference to one or more other drawings.

Claims

1. An integrated circuit device, comprising: a first semiconductor substrate having a front surface and a back surface opposite to each other; a front-end process structure on the front surface of the first semiconductor substrate, the front-end process structure including a plurality of fin-shaped active regions; a first back-end process structure on the front-end process structure, the first back-end process structure being separated from the first semiconductor substrate in a vertical direction with the front-end process structure interposed therebetween; a second back-end process structure on the back surface of the first semiconductor substrate, the second back-end process structure being separated from the front-end process structure in the vertical direction with the first semiconductor substrate interposed therebetween; and a second semiconductor substrate separated from the first semiconductor substrate in the vertical direction with the front-end process structure and the first back-end process structure interposed therebetween, the second semiconductor substrate being partially bonded to the first back-end process structure, wherein the second semiconductor substrate includes a main surface facing the first back-end process structure, and the main surface of the second semiconductor substrate defines a local trench region in which a plurality of trenches are arranged in a regular pattern and a plurality of local bonding regions bonded to the first back-end process structure.

2. The integrated circuit device according to claim 1, wherein in the main surface of the second semiconductor substrate, the plurality of local trench regions include a plurality of first local trench regions and a plurality of second local trench regions, the plurality of first local trench regions include a plurality of first trenches longitudinally extending in a first direction, the plurality of second local trench regions include a plurality of second trenches longitudinally extending in a second direction, wherein the second direction intersects the first direction, and the plurality of local trench regions have a grid shape in which the plurality of first local trench regions and the plurality of second local trench regions cross each other.

3. The integrated circuit device according to claim 2, wherein the main surface of the second semiconductor substrate has at least one irradiation region including a square region, and in the main surface of the second semiconductor substrate, each of the plurality of first local trench regions and the plurality of second local trench regions extends along a direction parallel to at least one side of the at least one irradiation region.

4. The integrated circuit device according to claim 2, wherein the main surface of the second semiconductor substrate has at least one irradiation region including a square region, and in the main surface of the second semiconductor substrate, each of the plurality of first local trench regions and the plurality of second local trench regions extends along a direction parallel to a diagonal direction in which the at least one irradiation region intersects itself.

5. The integrated circuit device according to claim 1, wherein, The integrated circuit device defines a plurality of air gaps defined by the plurality of trenches of the second semiconductor substrate and the first back-end process structure.

6. The integrated circuit device according to claim 1, wherein, The second semiconductor substrate has at least one irradiation region, and an area occupied by the plurality of trenches in the at least one irradiation region is 20% or less.

7. The integrated circuit device according to claim 1, further comprising: A power rail wiring that passes through the first semiconductor substrate in the vertical direction. Wherein, the second back-end process structure includes a wiring layer on the back surface of the first semiconductor substrate, and the wiring layer is connected to the power rail wiring.

8. The integrated circuit device according to claim 1, further comprising: A contact structure that passes through the first semiconductor substrate in the vertical direction. Wherein, the front-end process structure further includes: A source / drain region on a first fin active region among the plurality of fin active regions, the source / drain region being separated from the first semiconductor substrate by the first fin active region in the vertical direction; and A source / drain contact separated from the first semiconductor substrate by the first fin active region and the source / drain region in the vertical direction, the source / drain contact being connected to the source / drain region. Wherein, the contact structure is connected to one of the source / drain region and the source / drain contact.

9. The integrated circuit device according to claim 1, wherein The front-end process structure further includes: A gate line on a first fin active region among the plurality of fin active regions; At least one nanosheet between the first fin active region and the gate line, the at least one nanosheet being surrounded by the gate line; A source / drain region on the first fin active region, the source / drain region contacting the at least one nanosheet; A source / drain contact between the source / drain region and the first back-end process structure, the source / drain contact being connected to the source / drain region; An insulating structure including a device isolation film covering first sidewalls and second sidewalls of the first fin active region; and A contact structure that passes through the first semiconductor substrate and the insulating structure in the vertical direction, the contact structure being connected to at least one of the source / drain region and the source / drain contact.

10. An integrated circuit device, comprising: A first semiconductor substrate having a front surface and a back surface opposite to each other; A front-end process structure on the front surface of the first semiconductor substrate, the front-end process structure including a plurality of fin active regions; A first back-end process structure on the front-end process structure, the first back-end process structure being separated from the first semiconductor substrate by the front-end process structure in the vertical direction; A second back-end process structure on the back surface of the first semiconductor substrate, the second back-end process structure being separated from the front-end process structure by the first semiconductor substrate in the vertical direction; And A second semiconductor substrate separated from the first semiconductor substrate by the front-end process structure and the first back-end process structure in the vertical direction, the second semiconductor substrate having a main surface partially bonded to the first back-end process structure. Wherein, the main surface of the second semiconductor substrate and the first back-end process structure define a plurality of air gaps together, and define a plurality of local trench regions in which a plurality of trenches are arranged in a regular pattern, and a plurality of local bonding regions are bonded to the first back-end process structure.

11. The integrated circuit device according to claim 10, wherein, the main surface of the second semiconductor substrate has at least one irradiation region including a quadrangular region, and the plurality of local trench regions include a plurality of first local trench regions and a plurality of second local trench regions. The plurality of first local trench regions include a plurality of first trenches longitudinally extending in a direction parallel to a first side of the at least one irradiation region in a first direction. The plurality of second local trench regions include a plurality of second trenches longitudinally extending in a direction parallel to a second side of the at least one irradiation region in a second direction, wherein the second direction intersects the first direction of the at least one irradiation region.

12. The integrated circuit device according to claim 10, wherein, the main surface of the second semiconductor substrate has at least one irradiation region including a quadrangular region, and the plurality of local trench regions include a plurality of first local trench regions and a plurality of second local trench regions. The plurality of first local trench regions include a plurality of first trenches longitudinally extending in a direction parallel to a first diagonal of the at least one irradiation region. The plurality of second local trench regions include a plurality of second trenches longitudinally extending in a direction parallel to a second diagonal intersecting the first diagonal of the at least one irradiation region.

13. The integrated circuit device according to claim 10, wherein, The second semiconductor substrate has at least one irradiation region, and an area occupied by the plurality of trenches in the area of the at least one irradiation region is 20% or less.

14. An integrated circuit device, comprising: a first semiconductor substrate having a front surface and a back surface opposite to each other; a front-end process structure including a fin-type active region integrally connected to the first semiconductor substrate, a gate line on the fin-type active region, and at least one nanosheet between the fin-type active region and the gate line, the at least one nanosheet being surrounded by the gate line; a first back-end process structure on the front-end process structure, the first back-end process structure being separated from the first semiconductor substrate by the front-end process structure in a vertical direction, and the first back-end process structure including a front wiring structure; a second back-end process structure on the back surface of the first semiconductor substrate, the second back-end process structure being separated from the front-end process structure by the first semiconductor substrate in the vertical direction, the second back-end process structure including a back wiring structure; and a second semiconductor substrate separated from the first semiconductor substrate by the front-end process structure and the first back-end process structure in the vertical direction Wherein, the second semiconductor substrate includes a main surface facing the first back-end process structure, the main surface defining a first local trench region and a second local trench region extending along directions crossing each other, and a plurality of local bonding regions bonded to the first back-end process structure, wherein a plurality of trenches are arranged in a regular pattern in each of the first local trench region and the second local trench region, and an area occupied by the plurality of trenches in a unit area of the main surface is 20% or less.

15. The integrated circuit device according to claim 14, wherein, the integrated circuit device defines a plurality of air gaps defined by the plurality of trenches of the second semiconductor substrate and the first back-end process structure, each of the plurality of air gaps has a length in the range of 100 nm to 150 nm in the vertical direction, each of the plurality of air gaps has a width in the range of 300 nm to 500 nm, and each of the plurality of air gaps has a pitch in the range of 600 nm to 1 μm.

16. A method of manufacturing an integrated circuit device, the method comprising: forming a front-end process structure on the front surface of a first semiconductor substrate having a front surface and a back surface opposite to the front surface; forming a first back-end process structure on the front-end process structure; providing a second semiconductor substrate having a main surface, a plurality of trenches being formed in the main surface in a regular pattern; bonding the first back-end process structure to the second semiconductor substrate by bonding the main surface of the second semiconductor substrate except for the plurality of trenches to the first back-end process structure at a position where the main surface of the second semiconductor substrate faces the first back-end process structure in the vertical direction; when the first back-end process structure is bonded to the second semiconductor substrate, polishing the first semiconductor substrate from the back surface of the first semiconductor substrate to reduce the thickness of the first semiconductor substrate; and when the first back-end process structure is bonded to the second semiconductor substrate, forming a second back-end process structure on the polished back surface of the first semiconductor substrate.

17. The method according to claim 16, wherein, during the provision of the second semiconductor substrate, the main surface of the second semiconductor substrate defines a plurality of first local trench regions and a plurality of second local trench regions, the plurality of first local trench regions including a plurality of first trenches longitudinally extending in a first direction among the plurality of trenches, and the plurality of second local trench regions including a plurality of second trenches longitudinally extending in a second direction among the plurality of trenches, wherein the second direction crosses the first direction, and in the main surface of the second semiconductor substrate, the plurality of first local trench regions and the plurality of second local trench regions cross each other to have a grid shape.

18. The method according to claim 16, wherein During the provision of the second semiconductor substrate, the second semiconductor substrate has a notch at an edge of the second semiconductor substrate, and The main surface of the second semiconductor substrate defines a plurality of first local trench regions and a plurality of second local trench regions. The plurality of first local trench regions include a plurality of first trenches that extend longitudinally in a first direction among the plurality of trenches, and the plurality of second local trench regions include a plurality of second trenches that extend longitudinally in a second direction among the plurality of trenches. Herein, the first direction is parallel to a first radial direction from the center of the second semiconductor substrate toward the notch, and the second direction intersects the first direction.

19. The method according to claim 16, wherein During the provision of the second semiconductor substrate, the second semiconductor substrate includes a notch formed on an edge of the second semiconductor substrate, and the main surface of the second semiconductor substrate includes a plurality of first local trench regions and a plurality of second local trench regions. The plurality of first local trench regions include a plurality of first trenches that extend longitudinally in a third direction among the plurality of trenches, and the plurality of second local trench regions include a plurality of second trenches that extend longitudinally in a fourth direction among the plurality of trenches. Herein, the third direction is an inclined direction with respect to a first radial direction from the center of the second semiconductor substrate toward the notch, and the fourth direction is an inclined direction with respect to the first radial direction and intersects the third direction.

20. The method according to claim 16, wherein, Bonding the first back-end process structure to the second semiconductor substrate includes: forming a plurality of air gaps defined by the plurality of trenches and the first back-end process structure.

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