Micro-LED epitaxial wafer and Micro-LED

Abstract

The present invention discloses a Micro-LED epitaxial wafer and a Micro-LED, which relate to the field of semiconductor optoelectronic devices. The epitaxial wafer comprises a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type GaN layer in sequence; the N-type semiconductor layer comprises a first superlattice layer and a second superlattice layer in sequence; the first superlattice layer comprises a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer; the InN annihilation layer is provided with a plurality of holes; the second superlattice layer comprises a third Si-doped GaN layer and an AlInGaN layer; the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are less than the Si doping concentration of the third Si-doped GaN layer; the Si doping concentration of the third Si-doped GaN layer is ≥1×10 19 cm ‑3 The implementation of the present invention can improve light efficiency and wavelength uniformity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a Micro-LED epitaxial wafer and a Micro-LED. Background Art

[0002] Micro-LED generally refers to chips with a size of less than 100μm. It has excellent performance and low power consumption. It is the latest and best application technology in the foreseeable multi-display scenario at the current stage. However, the operating current density of Micro-LED is generally 0.1A / cm 2 ~2A / cm 2 Under such low current density, how to achieve uniform current distribution and how to improve luminous efficiency become extremely important issues. The epitaxial structure of Micro-LED generally includes a substrate, an AlN buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, and a P-type GaN layer. Currently, a common method to improve the uniformity of current distribution is to increase the Si doping concentration in the N-type GaN layer to reduce its resistivity and reduce current congestion. However, increasing the Si doping concentration can easily cause a significant decrease in the crystal quality of the layer, causing the dislocations in the lower layer to easily spread upward, forming leakage channels, resulting in poor reliability; and after the dislocations extending upward enter the multi-quantum well layer, they will increase the compressive strain in the multi-quantum well layer, resulting in an increase in non-radiative recombination and reduced luminous efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a Micro-LED epitaxial wafer with high luminous efficiency and good luminous uniformity.

[0004] Another technical problem to be solved by the present invention is to provide a Micro-LED.

[0005] In order to solve the above technical problems, the present invention provides a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type GaN layer stacked on the substrate in sequence;

[0006] The N-type semiconductor layer includes a first superlattice layer and a second superlattice layer sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure, and each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer and an InN annihilation layer stacked in sequence; the InN annihilation layer is provided with a plurality of holes;

[0007] The second superlattice layer has a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence; the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer is less than the Si doping concentration of the third Si-doped GaN layer; the Si doping concentration of the third Si-doped GaN layer is ≥1×10 19 cm -3 .

[0008] As an improvement to the above technical solution, in the first superlattice layer, the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period is respectively greater than the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer in the N-1th period; wherein N is a positive integer and N≥2; and / or

[0009] In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is greater than the Si doping concentration of the third Si-doped GaN layer in the M-1th period; wherein M is a positive integer and M≥2.

[0010] As an improvement to the above technical solution, in the first superlattice layer, the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period is 2% to 20% greater than the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer in the N-1th period, respectively; wherein N is a positive integer and N ≥ 2; and / or

[0011] In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is 10% to 50% greater than the Si doping concentration of the third Si-doped GaN layer in the M-1th period; wherein M is a positive integer and M≥2.

[0012] As an improvement of the above technical solution, the method for preparing the InN annihilation layer includes: growing an InN layer, and then heat-treating it in an atmosphere containing H2 to form holes, thereby obtaining the InN annihilation layer;

[0013] The growth temperature of the InN layer is 700° C. to 800° C., and the heat treatment temperature is 1000° C. to 1100° C.

[0014] As an improvement to the above technical solution, the number of periods of the first superlattice layer is 2 to 20; and / or

[0015] The thickness of the first Si-doped GaN layer is 10 nm to 60 nm, and the Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3and / or

[0016] The thickness of the Si3N4 layer is 1nm~10nm; and / or

[0017] The thickness of the second Si-doped GaN layer is 10 nm to 60 nm, and the Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 and / or

[0018] The thickness of the InN annihilation layer is 0.5 nm to 5 nm; and / or

[0019] The number of periods of the second superlattice layer is 2 to 15; and / or

[0020] The thickness of the third Si-doped GaN layer is 5 nm to 30 nm, and the Si doping concentration is 1×10 19 cm -3 ~5×10 20 cm -3 ;

[0021] The thickness of the AlInGaN layer is 5 nm to 50 nm, the In component ratio is 0.01 to 0.1, and the Al component ratio is 0.01 to 0.1.

[0022] As an improvement of the above technical solution, the N-type semiconductor layer further includes a third superlattice layer provided between the first superlattice layer and the second superlattice layer;

[0023] The third superlattice layer is a periodic structure, and each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer stacked in sequence; a plurality of holes are formed in the porous InGaN layer and filled with the intrinsic GaN layer;

[0024] The doping concentration of the fourth Si-doped GaN layer is lower than the Si doping concentration of the third Si-doped GaN layer, and the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are lower than the Si doping concentration of the fourth Si-doped GaN layer.

[0025] As an improvement to the above technical solution, the number of periods of the third superlattice layer is 2 to 20; and / or

[0026] The thickness of the AlN layer is 1 nm to 10 nm; and / or

[0027] The thickness of the fourth Si-doped GaN layer is 10 nm to 50 nm, and the Si doping concentration is 5×10 18 cm -3 ~5×1019 cm -3 and / or

[0028] The thickness of the porous InGaN layer is 0.5 nm to 5 nm, and the proportion of In component thereof is 0.01 to 0.1; and / or

[0029] The thickness of the intrinsic GaN layer is 10 nm to 50 nm.

[0030] As an improvement of the above technical solution, in the third superlattice layer, the Si doping concentration of the fourth Si-doped GaN layer in the Oth period is greater than the Si doping concentration of the fourth Si-doped GaN layer in the O-1th period; wherein O is a positive integer and O≥2.

[0031] As an improvement of the above technical solution, the method for preparing the porous InGaN layer includes: growing an InGaN layer, and then heat-treating it in an atmosphere containing H2 to form pores, thereby obtaining a porous InGaN layer;

[0032] The growth temperature of the InGaN layer is 800°C to 900°C, and the heat treatment temperature is 1000°C to 1100°C.

[0033] Correspondingly, the present invention also discloses a Micro-LED, which includes the above-mentioned Micro-LED epitaxial wafer.

[0034] The implementation of the present invention has the following beneficial effects:

[0035] In one embodiment of the present invention, the micro-LED epitaxial wafer comprises an N-type semiconductor layer comprising a first superlattice layer and a second superlattice layer stacked sequentially on an undoped GaN layer. The first superlattice layer has a periodic structure, with each period comprising a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer stacked sequentially. The InN annihilation layer is provided with multiple holes. The Si3N4 layer blocks dislocations from extending upward, reducing dislocation density. The holes in the InN annihilation layer annihilate various types of defects (such as point defects and line defects), improving the crystal quality of the entire layer. Furthermore, the periodic, repetitive structure of first Si-doped GaN layer, Si3N4 layer, second Si-doped GaN layer, and InN annihilation layer allows for multiple changes in the dislocation propagation path, further reducing dislocation density, optimizing crystal quality, and enhancing reliability. The second superlattice layer is a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence. The crystal quality is greatly optimized by the first superlattice layer, which can effectively increase the Si doping concentration in the third Si-doped GaN layer to be greater than 1×10 19 cm -3, and a doping method can be adopted in which the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer is less than the Si doping concentration of the third Si-doped GaN layer. This doping method reduces the resistivity of the N-type semiconductor layer as a whole, optimizes the current expansion, and improves the uniformity of luminescence. In addition, the potential barrier of the AlInGaN layer introduced in the second superlattice layer is relatively high, which can promote electrons to enter the multi-quantum well layer more uniformly. In addition, it can further reduce the lattice mismatch between the N-type semiconductor layer and the multi-quantum well layer, reduce the compressive stress in the multi-quantum well layer, and improve the luminescence efficiency. Therefore, based on the technical solution of this embodiment, not only the current distribution is effectively improved and the luminescence uniformity is optimized, but also the luminescence efficiency is improved, leakage is effectively prevented, and reliability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 1 is a schematic structural diagram of a Micro-LED epitaxial wafer according to an embodiment of the present invention;

[0037] Figure 2 Schematic diagram of the structure of a Micro-LED epitaxial wafer in another embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0039] See also Figure 1 The present invention discloses a Micro-LED epitaxial wafer, which includes a substrate 100, a buffer layer 200, an undoped GaN layer 300, an N-type semiconductor layer 400, a multi-quantum well layer 500 and a P-type GaN layer 600 stacked in sequence on the substrate 100.

[0040] The N-type semiconductor layer 400 includes a first superlattice layer 410 and a second superlattice layer 420 sequentially stacked on the undoped GaN layer 300. The first superlattice layer 410 has a periodic structure, with each period comprising a first Si-doped GaN layer 411, a Si3N4 layer 412, a second Si-doped GaN layer 413, and an InN annihilation layer 414 stacked in sequence. The InN annihilation layer 414 is provided with multiple holes. The Si3N4 layer 412 blocks dislocations from extending upward, reducing dislocation density. The holes in the InN annihilation layer 414 annihilate various types of defects (such as point defects and line defects), improving the crystal quality of the entire layer. Furthermore, the periodic, repetitive structure of first Si-doped GaN layer 411 - Si3N4 layer 412 - second Si-doped GaN layer 413 - InN annihilation layer 414 allows for multiple changes in the dislocation propagation path, further reducing dislocation density, optimizing crystal quality, and enhancing reliability.

[0041] The second superlattice layer 420 is a periodic structure, and each period includes a third Si-doped GaN layer 421 and an AlInGaN layer 422 stacked in sequence. By significantly optimizing the crystal quality through the first superlattice layer 410, the Si doping concentration in the third Si-doped GaN layer 421 can be effectively increased to be greater than 1×10 19 cm -3 , and a doping method can be adopted in which the Si doping concentration of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 is less than the Si doping concentration of the third Si-doped GaN layer 421. This doping method reduces the resistivity of the N-type semiconductor layer 400 as a whole, optimizes current spreading, and improves luminescence uniformity. In addition, the AlInGaN layer 422 introduced in the second superlattice layer 420 has a high potential barrier, which can promote more uniform electron entry into the multi-quantum well layer 500. In addition, it can further reduce the lattice mismatch between the N-type semiconductor layer 400 and the multi-quantum well layer 500, reduce the compressive stress in the multi-quantum well layer 500, and improve luminescence efficiency. Therefore, based on the technical solution of this embodiment, not only the current distribution and luminescence uniformity are effectively optimized, but also the luminescence efficiency is improved, leakage is effectively prevented, and reliability is improved.

[0042] Specifically, in some embodiments, the period number of the first superlattice layer 410 is 2 to 20, preferably 5 to 15. The thickness of the first Si-doped GaN layer 411 is 10 nm to 60 nm, preferably 20 nm to 50 nm. The Si doping concentration of the first Si-doped GaN layer 411 is 1×10 18 cm -3 ~1×10 19 cm -3 , preferably 1×10 18 cm -3 ~5×10 18 cm -3 The thickness of the Si3N4 layer 412 is 1 nm to 10 nm, preferably 1 nm to 5 nm. The thickness of the second Si-doped GaN layer 413 is 10 nm to 60 nm, preferably 20 nm to 50 nm. The Si doping concentration of the second Si-doped GaN layer 413 is 1×10 18 cm -3 ~1×10 19 cm -3 , preferably 1×10 18 cm -3 ~5×10 18 cm -3 The thickness of the InN annihilation layer 414 is 0.5 nm to 5 nm, preferably 2 nm to 5 nm.

[0043] Specifically, the Si doping concentration of the first Si-doped GaN layer 411 is the same as or different from the Si doping concentration of the second Si-doped GaN layer 413. Preferably, the Si doping concentration of the first Si-doped GaN layer 411 is less than the Si doping concentration of the second Si-doped GaN layer 413. Based on this configuration, current spreading can be further optimized and light uniformity can be improved.

[0044] Specifically, in some embodiments, the period number of the second superlattice layer 420 is 2 to 15, preferably 5 to 12. The thickness of the third Si-doped GaN layer 421 is 5 nm to 30 nm, preferably 10 nm to 20 nm. The Si doping concentration of the third Si-doped GaN layer 421 is 1×10 19 cm -3 ~5×10 20 cm -3 , preferably 2×10 19 cm -3 ~5×10 19 cm -3 The thickness of the AlInGaN layer 422 is 5 nm to 50 nm, preferably 10 nm to 20 nm. The ratio of the In component in the AlInGaN layer 422 is 0.01 to 0.1, preferably 0.01 to 0.05. The ratio of the Al component in the AlInGaN layer 422 is 0.01 to 0.1, preferably 0.05 to 0.1.

[0045] Specifically, in some embodiments, the substrate 100 is a sapphire substrate or a silicon substrate, but is not limited thereto.

[0046] Specifically, in some embodiments, the buffer layer 200 is an AlN layer or an AlGaN layer, but is not limited thereto. The buffer layer 200 has a thickness of 30 nm to 80 nm.

[0047] Specifically, in some embodiments, the thickness of the undoped GaN layer 300 is 1 μm to 3 μm.

[0048] Specifically, in some embodiments, the multi-quantum well layer 500 includes alternating InGaN quantum well layers and GaN quantum barrier layers, with a period number of 3 to 15. The thickness of a single InGaN quantum well layer is 3 nm to 5 nm, with an In component ratio of 0.1 to 0.4; the thickness of a single GaN quantum barrier layer is 5 nm to 15 nm.

[0049] Specifically, the doping element of the P-type GaN layer 600 is Mg, but not limited thereto. The Mg doping concentration in the P-type GaN layer 600 is 1×10 19 cm -3 ~5×10 20 cm -3, its thickness is 20nm~200nm.

[0050] Preferably, in some embodiments, in the first superlattice layer 410, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the Nth period are respectively greater than the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the N-1th period; wherein N is a positive integer and N ≥ 2. That is, as the number of periods in the first superlattice layer 410 increases, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in different periods increase. Based on this embodiment, the overall crystal quality of the N-type semiconductor layer 400 can be prevented from being degraded due to excessive doping concentration, thereby improving reliability. At the same time, this incremental doping method further improves the uniformity of current distribution and enhances luminescence uniformity.

[0051] More preferably, in the first superlattice layer 410, the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the Nth period are 2% to 20% greater than the Si doping concentrations of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413 in the N-1th period, respectively. It should be noted that within any period, the Si doping concentration of the first Si-doped GaN layer 411 may increase, decrease, or remain unchanged as its thickness increases. The Si doping concentration of the second Si-doped GaN layer 413 may increase, decrease, or remain unchanged as its thickness increases.

[0052] Preferably, in some embodiments, in the second superlattice layer 420, the Si doping concentration of the third Si-doped GaN layer 421 in the Mth period is greater than the Si doping concentration of the third Si-doped GaN layer 421 in the M-1th period; wherein M is a positive integer, and M ≥ 2. That is, as the number of periods of the second superlattice layer 420 increases, the Si doping concentration of the third Si-doped GaN layer 421 in different periods increases. Based on this embodiment, the overall crystal quality of the N-type semiconductor layer 400 can be avoided from being reduced due to excessive doping concentration, thereby improving reliability. At the same time, this incremental doping method also further improves the uniformity of current distribution and improves the uniformity of luminescence.

[0053] More preferably, in the second superlattice layer 420, the Si doping concentration of the third Si-doped GaN layer 421 in the Mth period is 10% to 50% greater than the Si doping concentration of the third Si-doped GaN layer 421 in the M-1th period. It should be noted that within any period, the Si doping concentration of the third Si-doped GaN layer 421 may increase, decrease, or remain unchanged as its thickness increases.

[0054] Specifically, the InN annihilation layer 414 can form a plurality of holes through a photolithography-etching process, but is not limited thereto. Preferably, in some embodiments, the preparation method of the InN annihilation layer 414 is: growing an InN layer, and then heat-treating it in an atmosphere containing H2 to form holes, that is, obtaining the InN annihilation layer 414. The growth temperature of the InN layer is 700°C to 800°C, and the heat treatment temperature is 1000°C to 1100°C. Based on this embodiment, on the one hand, the growth temperature of the InN layer is relatively low, which is conducive to the release of thermal stress accumulated in the N-type semiconductor layer 400. Secondly, by forming holes through heat treatment in an atmosphere containing H2, the defects gathered in the InN layer can be annihilated by holes obtained by high-temperature thermal decomposition, which greatly reduces the density of dislocations extending upward.

[0055] Preferably, see Figure 2 In some embodiments, the N-type semiconductor layer 400 further includes a third superlattice layer 430 disposed between the first superlattice layer 410 and the second superlattice layer 420. The third superlattice layer 430 has a periodic structure, with each period comprising a sequentially stacked AlN layer 431, a fourth Si-doped GaN layer 432, a porous InGaN layer 433, and an intrinsic GaN layer 434. The porous InGaN layer 433 has multiple pores formed therein, which are filled by the intrinsic GaN layer 434. The AlN layer 431 has a high density, facilitating dislocation kinking and reducing dislocation density. The porous InGaN layer 433 further annihilates dislocations through the pores, thereby improving the overall crystal quality of the N-type semiconductor layer 400. The pores are filled by the intrinsic GaN layer 434, providing a good growth foundation for the subsequent growth of the third superlattice layer 430, further reducing stress accumulation and improving luminous efficiency. In addition, the Si doping concentration of the fourth Si-doped layer is lower than that of the third Si-doped layer, but higher than that of the first Si-doped GaN layer 411 and the second Si-doped GaN layer 413. This step-by-step doping method further improves the crystal quality and optimizes the current expansion.

[0056] Specifically, in some embodiments, the period number of the third superlattice layer 430 is 2 to 20, preferably 5 to 15. The thickness of the AlN layer 431 is 1 nm to 10 nm, preferably 2 nm to 8 nm. The thickness of the fourth Si-doped GaN layer 432 is 10 nm to 50 nm, preferably 30 nm to 50 nm. The Si doping concentration of the fourth Si-doped GaN layer 432 is 5×10 18 cm -3 ~5×10 19 cm -3 , preferably 5×10 18 cm -3 ~1×10 19 cm -3The thickness of the porous InGaN layer 433 is 0.5 nm to 5 nm, preferably 2 nm to 5 nm. The ratio of the In component in the porous InGaN layer 433 is 0.01 to 0.1, preferably 0.03 to 0.08. The thickness of the intrinsic GaN layer 434 is 10 nm to 50 nm, preferably 30 nm to 50 nm.

[0057] Preferably, in some embodiments, in the third superlattice layer 430, the Si doping concentration of the fourth Si-doped GaN layer 432 in the Oth period is greater than the Si doping concentration of the fourth Si-doped GaN layer 432 in the O-1th period; where O is a positive integer and O ≥ 2. That is, as the number of periods in the third superlattice layer 430 increases, the Si doping concentration of the fourth Si-doped GaN layer 432 in different periods increases. Based on this embodiment, the overall crystal quality of the N-type semiconductor layer 400 can be prevented from being degraded due to excessive doping concentration, thereby improving reliability. At the same time, this incremental doping method further improves the uniformity of current distribution and the uniformity of luminescence. It should be noted that within any period, the Si doping concentration of the fourth Si-doped GaN layer 432 can increase, decrease, or remain unchanged as its thickness increases.

[0058] Specifically, the holes in the porous InGaN layer 433 can be formed by a photolithography-etching process, but is not limited thereto. Preferably, in some embodiments, the porous InGaN layer 433 is prepared by growing an InGaN layer and then heat-treating it in an H2-containing atmosphere to form the holes, thereby obtaining the porous InGaN layer 433. The InGaN layer is grown at a temperature of 800°C to 900°C, and the heat-treated temperature is 1000°C to 1100°C.

[0059] Accordingly, the present invention also discloses a Micro-LED, which includes the aforementioned Micro-LED epitaxial wafer. Based on the Micro-LED epitaxial wafer, the reliability of the Micro-LED can be improved, while also improving the luminous efficiency and luminous uniformity.

[0060] The present invention will be further described below with specific embodiments:

[0061] Example 1

[0062] This embodiment provides a Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type semiconductor layer, a multi-quantum well layer, and a P-type GaN layer stacked in sequence on the substrate.

[0063] The substrate is a sapphire substrate, the buffer layer is an AlN layer with a thickness of 40 nm, and the thickness of the non-doped GaN layer is 2 μm.

[0064] The N-type semiconductor layer includes a first superlattice layer and a second superlattice layer stacked sequentially on an undoped GaN layer. The first superlattice layer has a periodic structure with 10 periods. Each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer, and an InN annihilation layer stacked sequentially. The thickness of the first Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 The thickness of the Si3N4 layer is 3.5nm. The thickness of the second Si-doped GaN layer is 40nm, and the Si doping concentration is 2.3×10 18 cm -3 The thickness of the InN annihilation layer is 2.8 nm, and multiple holes are formed by photolithography and etching.

[0065] The second superlattice layer is a periodic structure with 5 periods. Each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence. The thickness of the third Si-doped GaN layer is 25 nm, and its Si doping concentration is 2.2×10 19 cm -3 The thickness of the AlInGaN layer is 12 nm, with an In component ratio of 0.02 and an Al component ratio of 0.08.

[0066] The multi-quantum well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers, with a period of 10. The InGaN quantum well layer has an In component ratio of 0.18 and a thickness of 3 nm. The GaN quantum barrier layer has a thickness of 10 nm.

[0067] Among them, the Mg doping concentration in the P-type GaN layer is 8×10 19 cm -3 , and its thickness is 100nm.

[0068] Example 2

[0069] This embodiment provides a Micro-LED epitaxial wafer, which differs from the first embodiment in that:

[0070] In the first superlattice layer, as the number of periods increases, the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer increases by 20% from 1×10 18 cm -3 Increased to 2.8×10 18 cm -3 .

[0071] In the second superlattice layer, as the number of periods increases, the Si doping concentration of the third Si-doped GaN layer increases by 10% from 1.8×10 19 cm -3Increased to 2.52×10 19 cm -3 .

[0072] The rest are the same as in Example 1.

[0073] Example 3

[0074] This embodiment provides a Micro-LED epitaxial wafer, which differs from Embodiment 2 in that:

[0075] The InN annihilation layer is prepared by growing an InN layer and then heat-treating it in an H2 atmosphere to form holes, thereby obtaining the InN annihilation layer. The InN layer is grown at a temperature of 720°C, heat-treated at a temperature of 1050°C, and heat-treated for 20 seconds.

[0076] The rest are the same as in Example 2.

[0077] Example 4

[0078] This embodiment provides a Micro-LED epitaxial wafer, which differs from Embodiment 3 in that:

[0079] The N-type semiconductor layer further includes a third superlattice layer disposed between the first superlattice layer and the second superlattice layer;

[0080] The third superlattice layer is a periodic structure with 10 periods. Each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer stacked in sequence. The thickness of the AlN layer is 4.5 nm. The thickness of the fourth Si-doped GaN layer is 35 nm, and the Si doping concentration is 6.5×10 18 cm -3 The porous InGaN layer is 3.5nm thick, with an In component ratio of 0.05. Photolithography and etching processes have created multiple pores within it, which are then filled with the intrinsic GaN layer. The intrinsic GaN layer is 35nm thick.

[0081] The rest are the same as in Example 3.

[0082] Example 5

[0083] This embodiment provides a Micro-LED epitaxial wafer, which differs from Embodiment 4 in that:

[0084] In the third superlattice layer, as the number of periods increases, the Si doping concentration of the fourth Si-doped GaN layer increases by 10% from 5×10 18 cm -3 Increased to 9.5×10 18 cm -3 .

[0085] The rest are the same as in Example 4.

[0086] Example 6

[0087] This embodiment provides a Micro-LED epitaxial wafer, which differs from Embodiment 5 in that:

[0088] The porous InGaN layer is prepared by growing an InGaN layer and then heat treating it in a H2 atmosphere to form pores.

[0089] The growth temperature of the InGaN layer is 840° C., the heat treatment temperature is 1100° C., and the heat treatment time is 15 seconds.

[0090] The rest are the same as in Example 5.

[0091] Comparative Example 1

[0092] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0093] The N-type semiconductor layer is an N-type GaN layer with a doping concentration of 1.3×10 19 cm -3 .

[0094] The rest are the same as in Example 1.

[0095] Comparative Example 2

[0096] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0097] The N-type semiconductor layer does not include the first superlattice layer.

[0098] The rest are the same as in Example 1.

[0099] Comparative Example 3

[0100] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0101] The N-type semiconductor layer does not include the second superlattice layer.

[0102] The rest are the same as in Example 1.

[0103] Comparative Example 4

[0104] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0105] The first superlattice layer does not include a Si3N4 layer.

[0106] The rest are the same as in Example 1.

[0107] Comparative Example 5

[0108] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0109] The first superlattice layer does not include an InN annihilation layer.

[0110] The rest are the same as in Example 1.

[0111] Comparative Example 6

[0112] This comparative example provides a Micro-LED epitaxial wafer, which differs from Example 1 in that:

[0113] The first superlattice layer of each period consists of a Si3N4 layer, a first Si-doped GaN layer, a second Si-doped GaN layer, and an InN annihilation layer stacked in sequence. The thickness of the Si3N4 layer is 3.5 nm. The thickness of the first Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 The thickness of the second Si-doped GaN layer is 40 nm, and the Si doping concentration is 2.3×10 18 cm -3 The thickness of the InN annihilation layer is 2.8 nm, and multiple holes are formed by photolithography and etching.

[0114] The rest are the same as in Example 1.

[0115] The micro-LED epitaxial wafers obtained in Examples 1 to 6 and Comparative Examples 1 to 6 were prepared into micro-LEDs with a size of 3 mil × 5 mil and a horizontal structure, and then tested as follows;

[0116] (1) At 0.2A / cm 2 The luminous brightness was tested at a current density of , and the luminous brightness improvement rate was calculated based on the data of comparative example 1.

[0117] (2) Conduct electroluminescence test with a current density of 0.2A / cm 2 and 1A / cm 2 , the wavelength under different current densities is obtained, and the wavelength shift is calculated according to the following formula:

[0118] Wavelength shift = |Test wavelength 1 (0.2A / cm 2 )-Test wavelength 2 (1A / cm 2 )|.

[0119]

[0120] As can be seen from the above table, when the Micro-LED epitaxial wafer of the present invention is used, the luminous efficiency of the Micro-LED can be greatly improved and the wavelength uniformity can be optimized.

[0121] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A Micro-LED epitaxial wafer, characterized in that: The method comprises a substrate, a buffer layer, a non-doped GaN layer, an N-type semiconductor layer, a multi-quantum well layer and a P-type GaN layer sequentially stacked on the substrate; The N-type semiconductor layer includes a first superlattice layer and a second superlattice layer sequentially stacked on the undoped GaN layer; the first superlattice layer is a periodic structure, and each period includes a first Si-doped GaN layer, a Si3N4 layer, a second Si-doped GaN layer and an InN annihilation layer stacked in sequence; the InN annihilation layer is provided with a plurality of holes; The second superlattice layer has a periodic structure, and each period includes a third Si-doped GaN layer and an AlInGaN layer stacked in sequence; the Si doping concentration of the first Si-doped GaN layer and the second Si-doped GaN layer is less than the Si doping concentration of the third Si-doped GaN layer; the Si doping concentration of the third Si-doped GaN layer is ≥1×10 19 cm -3 .

2. The Micro-LED epitaxial wafer according to claim 1, wherein: In the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the N-1th period; wherein N is a positive integer and N≥2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is greater than the Si doping concentration of the third Si-doped GaN layer in the M-1th period; wherein M is a positive integer and M≥2.

3. The Micro-LED epitaxial wafer according to claim 1, wherein: In the first superlattice layer, the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the Nth period are respectively 2% to 20% greater than the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer in the N-1th period; wherein N is a positive integer and N ≥ 2; and / or In the second superlattice layer, the Si doping concentration of the third Si-doped GaN layer in the Mth period is 10% to 50% greater than the Si doping concentration of the third Si-doped GaN layer in the M-1th period; wherein M is a positive integer and M≥2.

4. The Micro-LED epitaxial wafer according to claim 1, wherein: The method for preparing the InN annihilation layer comprises: growing an InN layer, and then heat treating it in an atmosphere containing H2 to form holes, thereby obtaining the InN annihilation layer; The growth temperature of the InN layer is 700° C. to 800° C., and the heat treatment temperature is 1000° C. to 1100° C.

5. The Micro-LED epitaxial wafer according to any one of claims 1 to 4, wherein: The number of periods of the first superlattice layer is 2 to 20; and / or The thickness of the first Si-doped GaN layer is 10 nm to 60 nm, and the Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 and / or The thickness of the Si3N4 layer is 1nm~10nm; and / or The thickness of the second Si-doped GaN layer is 10 nm to 60 nm, and the Si doping concentration is 1×10 18 cm -3 ~1×10 19 cm -3 and / or The thickness of the InN annihilation layer is 0.5 nm to 5 nm; and / or The number of periods of the second superlattice layer is 2 to 15; and / or The thickness of the third Si-doped GaN layer is 5 nm to 30 nm, and the Si doping concentration is 1×10 19 cm -3 ~5×10 20 cm -3 ; The thickness of the AlInGaN layer is 5 nm to 50 nm, the In component ratio is 0.01 to 0.1, and the Al component ratio is 0.01 to 0.

1.

6. The Micro-LED epitaxial wafer according to any one of claims 1 to 4, wherein: The N-type semiconductor layer further includes a third superlattice layer disposed between the first superlattice layer and the second superlattice layer; The third superlattice layer is a periodic structure, and each period includes an AlN layer, a fourth Si-doped GaN layer, a porous InGaN layer, and an intrinsic GaN layer stacked in sequence; a plurality of holes are formed in the porous InGaN layer and filled with the intrinsic GaN layer; The doping concentration of the fourth Si-doped GaN layer is lower than the Si doping concentration of the third Si-doped GaN layer, and the Si doping concentrations of the first Si-doped GaN layer and the second Si-doped GaN layer are lower than the Si doping concentration of the fourth Si-doped GaN layer.

7. The Micro-LED epitaxial wafer according to claim 6, wherein: The number of periods of the third superlattice layer is 2 to 20; and / or The thickness of the AlN layer is 1 nm to 10 nm; and / or The thickness of the fourth Si-doped GaN layer is 10 nm to 50 nm, and the Si doping concentration is 5×10 18 cm -3 ~5×10 19 cm -3 and / or The thickness of the porous InGaN layer is 0.5 nm to 5 nm, and the proportion of In component thereof is 0.01 to 0.1; and / or The thickness of the intrinsic GaN layer is 10 nm to 50 nm.

8. The Micro-LED epitaxial wafer according to claim 6, wherein: In the third superlattice layer, the Si doping concentration of the fourth Si-doped GaN layer in the Oth period is greater than the Si doping concentration of the fourth Si-doped GaN layer in the O-1th period; wherein O is a positive integer and O≥2.

9. The Micro-LED epitaxial wafer according to claim 6, wherein: The method for preparing the porous InGaN layer comprises: growing an InGaN layer, and then heat-treating it in an atmosphere containing H2 to form pores, thereby obtaining the porous InGaN layer; The growth temperature of the InGaN layer is 800°C to 900°C, and the heat treatment temperature is 1000°C to 1100°C.

10. A Micro-LED, characterized in that: Comprising the Micro-LED epitaxial wafer as described in any one of claims 1 to 9.

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