Power semiconductor device chip active area temperature distribution simulation test method and system

Abstract

The invention discloses a power semiconductor device chip active area temperature distribution simulation test method and system, and the method comprises the steps: designing a metal pattern mask according to the cell information of a power semiconductor device chip active area; selecting a semiconductor wafer of which the growth of the semiconductor multilayer structure is completed and the surface semiconductor layer is not doped, and depositing a metal pattern; calibrating a Raman characteristic temperature curve of a semiconductor layer on the surface of the chip sample based on a confocal Raman spectrometer and a heating stage; the bottom face of the chip sample is connected with the device packaging heat dissipation structure, and the metal pattern on the surface of the chip sample is connected into a direct-current power supply loop; adjusting output of the direct-current power supply, simulating heat generation of a heat source in an active area of the chip sample and reaching target heat generation power; and measuring the temperature distribution of the active area of the chip sample according to the calibrated Raman characteristic temperature curve. According to the invention, the simulation test of the junction temperature and temperature distribution of the active area of the chip can be realized in the design and manufacturing process of the power semiconductor device, and the actual performance of thermal design of the power semiconductor device is experimentally evaluated.

Description

Technical Field

[0001] The present invention belongs to the field of design and manufacturing of power semiconductor devices, and particularly relates to a method and system for simulating and testing the temperature distribution in the active region of a power semiconductor device chip. Background Art

[0002] The trend of miniaturization and high performance of power semiconductor devices poses higher requirements for device thermal design. If the heat dissipation is insufficient during the high-power density operation of the device, it will lead to too high a junction temperature, accelerating device degradation and affecting the switching performance and efficiency of the device; at the same time, the uneven temperature distribution in the active region may cause local hot spots, further shortening the device life. Therefore, thermal design is one of the core challenges in the design and application of power semiconductor devices.

[0003] In the process of designing and manufacturing power semiconductor devices, currently only thermal simulation methods are used to preliminarily evaluate the thermal characteristics such as the junction temperature and temperature distribution in the active region of the chip, but the accuracy of the thermal simulation results is limited. The existing methods for measuring the junction temperature of power semiconductor devices mainly focus on the finished products of power semiconductor devices, and are basically divided into two categories: the contact temperature measurement method mainly realizes temperature measurement through thermocouples or thermosensitive parameters, and the non-contact temperature measurement method mainly realizes temperature measurement through optical signals. The temperatures measured by the above methods for measuring the junction temperature of power semiconductor devices are mainly the near-junction temperatures of the package structure, and it is difficult to measure the accurate junction temperature and temperature distribution in the active region inside the chip. Summary of the Invention

[0004] The object of the present invention is to propose a method and system for simulating and testing the temperature distribution in the active region of a power semiconductor device chip.

[0005] The technical solution for achieving the object of the present invention is: a method for simulating and testing the temperature distribution in the active region of a power semiconductor device chip, comprising the following steps:

[0006] Step 1, collect the size of the active region of the power semiconductor device chip, the size and layout of the cell pattern, and the gate size information of the cell unit, and correspondingly design a metal pattern mask plate;

[0007] Step 2, select a semiconductor wafer on which the growth of the semiconductor multi-layer structure is completed and the surface semiconductor layer is not doped, and deposit the metal pattern corresponding to the metal pattern mask plate on the surface of the semiconductor wafer;

[0008] Step 3, cut out a chip sample from the semiconductor wafer deposited with the metal pattern, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample by using a confocal Raman spectrometer and a hot stage;

[0009] Step 4, connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit;

[0010] Step 5: Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, adjust the output of the DC power supply, simulate the heat generation of the heat source in the active region of the chip sample, and reach the target heat generation power P;

[0011] Step 6: Measure the Raman spectral signals at different positions of the semiconductor layer on the surface of the chip sample at the target heat generation power P, calculate the temperature distribution of the active region of the chip sample according to the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device.

[0012] Further, in Step 1, collect the active region size of the power semiconductor device chip, the cell pattern size and layout, and the gate size information of the cell unit, and design the metal pattern mask accordingly. Specifically:

[0013] Collect the active region size of the power semiconductor device chip, the cell unit pattern size and layout in the active region, and the gate size information of the cell unit;

[0014] Design the metal pattern mask. For strip-shaped cells, the metal pattern mask includes metal wires and metal disks. The metal wires are used to simulate the heat sources in the cell units, the metal wires are parallel to each other, the width of the metal wire is set as the gate width, and the length of the metal wire is set as the cell unit length; the metal disks are arranged outside the active region at both ends of the metal wires, connect all the metal wires to realize the parallel connection of the metal wires, and the side length of the metal disk is greater than or equal to 1 mm for connecting the DC power supply circuit; for square cells, the metal pattern mask also includes strip-shaped metal bands, which are arranged in the cell interval area in the extending direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip-shaped metal bands interconnect all the metal wires to form a mesh metal pattern.

[0015] Further, in Step 2, select a semiconductor wafer on which the semiconductor multi-layer structure has been grown and the surface semiconductor layer has not been doped, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer. Specifically:

[0016] Select the metal silver with excellent conductivity as the metal pattern material, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer on which the semiconductor multi-layer structure has been completed and the surface semiconductor layer has not been doped by using the lithography process. The thickness range of the metal pattern is 100 nm to 1 um.

[0017] Further, in Step 3, cut out a chip sample from the semiconductor wafer deposited with the metal pattern, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample by using a confocal Raman spectrometer and a hot stage. Specifically:

[0018] A chip sample is cut from a semiconductor wafer with a deposited metal pattern. The metal pattern is placed upward on a hot stage, and the hot stage is installed on the confocal Raman spectrometer stage. The hot stage is controlled to rise from room temperature to 400 °C, and a temperature measurement point is set every 10 - 30 °C. The confocal Raman spectrometer is used to collect the Raman spectral signals of the semiconductor layer on the surface of the chip sample at each temperature measurement point. The laser wavelength of the confocal Raman spectrometer is selected as 532 nm, the laser power is controlled below 0.5 mW, and the longitudinal measurement depth is less than or equal to 4 μm;

[0019] Find the Raman spectral characteristic peaks corresponding to the surface semiconductor layer, obtain the displacement values of the characteristic peaks through baseline calibration and Gaussian model peak fitting, perform quadratic polynomial fitting on the displacement values of the characteristic peaks at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample. The specific expression is as follows:

[0020]

[0021] In the formula, f is the displacement value of the characteristic peak, with the unit of cm -1 ; T is the temperature, with the unit of K, and a, b, and c are the fitting coefficients of the quadratic term, linear term, and constant term respectively.

[0022] Furthermore, in step 4, the bottom surface of the chip sample is connected to the device package heat dissipation structure, and the metal pattern on the surface of the chip sample is connected to the DC power supply circuit. Specifically:

[0023] Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat of the active region heat source of the chip sample to dissipate downward;

[0024] The metal pattern on the surface of the chip sample is connected in series to the DC power supply circuit. The DC power supply circuit also includes a DC power supply and a precision resistor, where the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

[0025] Furthermore, in step 5, the chip sample connected to the DC power supply circuit and the device package heat dissipation structure are installed on the stage of the confocal Raman spectrometer, and the output of the DC power supply is adjusted to simulate the heat generation of the active region heat source of the chip sample and reach the target heat generation power P. Specifically:

[0026] Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, and adjust the output of the DC power supply to simulate the heat generation of the active region heat source of the chip sample and reach the target heat generation power P;

[0027] Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern, and calculate the target heat generation power P of the active region heat source of the chip sample. The specific formula is as follows:

[0028]

[0029] Wherein, P is the heat generation power with the unit of W; R is the resistance value of the precision resistor with the unit of Ω; U1 is the voltage across the precision resistor with the unit of V; U2 is the voltage across the metal pattern with the unit of V.

[0030] Further, in step 6, at the target heat generation power P, the Raman spectrum signals at different positions on the semiconductor layer surface of the chip sample are measured, and the temperature distribution in the active region of the chip sample is calculated based on the calibrated Raman characteristic temperature curve f(T) to evaluate the thermal design performance of the power semiconductor device, specifically as follows:

[0031] After reaching the target heat generation power P, the Raman spectrum signals at different positions on the semiconductor layer surface of the chip sample are sampled using the same confocal Raman spectrometer sampling parameters as in step 3, and the spatial resolution of the signal sampling is less than or equal to 1 μm;

[0032] Substitute the Raman characteristic temperature curve f(T) calibrated in step 3 to calculate the temperature distribution in the active region of the chip sample at the target heat generation power;

[0033] Evaluate the thermal design performance of the power semiconductor device. If the junction temperature and the temperature distribution uniformity in the active region of the chip sample both meet the design requirements, the thermal design of the power semiconductor device meets the standard; if the junction temperature and the temperature distribution uniformity in the active region of the chip sample do not meet the design requirements, the thermal design of the power semiconductor device needs to be optimized.

[0034] A simulation test system for the temperature distribution in the active region of a power semiconductor device chip implements the simulation test method for the temperature distribution in the active region of the power semiconductor device chip to realize the simulation test of the temperature distribution in the active region of the power semiconductor device chip, and six modules respectively execute steps 1 to 6.

[0035] Compared with the prior art, the remarkable advantages of the present invention are as follows: 1) According to the cell information in the active region of the power semiconductor device chip, a metal pattern mask is designed correspondingly, and the present invention can accurately simulate the heat source array in the active region of the power semiconductor device chip; 2) Based on the Raman spectroscopy temperature measurement method, the present invention can realize the temperature distribution measurement with high spatial resolution in the active region of the chip, and the spatial resolution of the temperature measurement is less than or equal to 1 μm; 3) The present invention conducts experimental tests based on the semiconductor wafer in the front-end process, and can realize the simulation test of the junction temperature and temperature distribution in the active region of the chip during the design and manufacturing process of the power semiconductor device, and experimentally evaluate the actual performance of the thermal design of the power semiconductor device. Description of the Drawings

[0036] Figure 1 It is a flowchart of the simulation test method for the temperature distribution in the active region of the power semiconductor device chip of the present invention.

[0037] Figure 2 Schematic diagram of the metal pattern mask design corresponding to the strip and square cells of the present invention.

[0038] Figure 3 Measurement results of the temperature distribution of the embodiment. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] As Figure 1 shown, a method for simulating and testing the temperature distribution in the active region of a power semiconductor device chip according to the present invention includes the following steps:

[0041] Step 1: Collect the size of the active region of the power semiconductor device chip, the size and layout of the cell pattern, and the gate size information of the cell unit, and design a metal pattern mask accordingly. Specifically:

[0042] Collect the size of the active region of the power semiconductor device chip, the size and layout of the cell unit pattern in the active region, and the gate size information of the cell unit;

[0043] Design a metal pattern mask. For strip cells, the metal pattern mask includes metal wires and metal disks. Among them, the metal wires are used to simulate the heat sources in the cell unit. The metal wires are parallel to each other. The width of the metal wire is set to the gate width, and the length of the metal wire is set to the length of the cell unit. The metal disks are arranged outside the active region at both ends of the metal wires and connect all the metal wires to achieve the parallel connection of the metal wires. The side length of the metal disk is greater than or equal to 1 mm and is used to connect the DC power supply circuit. For square cells, the metal pattern mask further includes strip-shaped metal strips. The strip-shaped metal strips are arranged in the cell interval area in the extending direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip-shaped metal strips interconnect all the metal wires to form a mesh metal pattern. To enhance the illustration effect, the schematic diagram of the metal pattern mask design corresponding to the strip and square cell layouts can be referred to Figure 2 .

[0044] Step 2: Select a semiconductor wafer on which the semiconductor multi-layer structure has been grown and the surface semiconductor layer has not been doped, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer. Specifically:

[0045] Select metal silver with excellent electrical conductivity as the metal pattern material, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer on which the semiconductor multi-layer structure has been completed and the surface semiconductor layer has not been doped by using a lithography process. The thickness range of the metal pattern is 100 nm to 1 um.

[0046] Step 3: Cut out a chip sample from the semiconductor wafer with the deposited metal pattern, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage. Specifically:

[0047] Cut out a chip sample from the semiconductor wafer with the deposited metal pattern, place it face-up in the hot stage, and install the hot stage on the stage of the confocal Raman spectrometer. Control the hot stage to rise from room temperature to 400 °C, set a temperature measurement point every 10 - 30 °C, and use the confocal Raman spectrometer to collect the Raman spectral signals of the surface semiconductor layer of the chip sample at each temperature measurement point. The laser wavelength of the confocal Raman spectrometer is selected as 532 nm, the laser power is controlled below 0.5 mW, and the longitudinal measurement depth is less than or equal to 4 μm.

[0048] Find the Raman spectral characteristic peak corresponding to the surface semiconductor layer, obtain the displacement value of the characteristic peak through baseline calibration and Gaussian model peak fitting, perform a quadratic polynomial fitting on the displacement values of the characteristic peaks at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample. The specific expression is:

[0049]

[0050] where f is the displacement value of the characteristic peak, with the unit of cm -1 ; T is the temperature, with the unit of K, and a, b, and c are the fitting coefficients of the quadratic term, linear term, and constant term respectively.

[0051] Step 4: Connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit. Specifically:

[0052] Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat of the active region heat source of the chip sample to dissipate downward.

[0053] Connect the metal pattern on the surface of the chip sample in series to the DC power supply circuit. The DC power supply circuit also includes a DC power supply and a precision resistor, where the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

[0054] Step 5: Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, and adjust the output of the DC power supply to simulate the heat generation of the active region heat source of the chip sample and reach the target heat generation power P. Specifically:

[0055] Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, and adjust the output of the DC power supply to simulate the heat generation of the active region heat source of the chip sample and reach the target heat generation power P;

[0056] Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern, and calculate the target heat generation power P of the heat source in the active region of the chip sample. The specific formula is as follows:

[0057]

[0058] In the formula, P is the heat generation power, with the unit of W; R is the resistance value of the precision resistor, with the unit of Ω; U1 is the voltage across the precision resistor, with the unit of V; U2 is the voltage across the metal pattern, with the unit of V.

[0059] Step 6: Measure the Raman spectrum signals at different positions on the semiconductor layer on the surface of the chip sample at the target heat generation power P, calculate the temperature distribution in the active region of the chip sample according to the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device, specifically:

[0060] After reaching the target heat generation power P, use the same confocal Raman spectrometer sampling parameters as in Step 3 to sample the Raman spectrum signals at different positions on the semiconductor layer on the surface of the chip sample. The spatial resolution of the signal sampling is less than or equal to 1 μm;

[0061] Substitute the Raman characteristic temperature curve f(T) calibrated in Step 3 to calculate the temperature distribution in the active region of the chip sample at the target heat generation power;

[0062] Evaluate the thermal design performance of the power semiconductor device. If the junction temperature (highest temperature) and the temperature distribution uniformity in the active region of the chip sample both meet the design requirements, the thermal design of the power semiconductor device meets the standard; if the junction temperature and the temperature distribution uniformity in the active region of the chip sample do not meet the design requirements, the thermal design of the power semiconductor device needs to be optimized.

[0063] The present invention also proposes a simulation test system for the temperature distribution in the active region of a power semiconductor device chip, implements the simulation test method for the temperature distribution in the active region of the power semiconductor device chip, and realizes the simulation test of the temperature distribution in the active region of the power semiconductor device chip. Six modules are respectively used to execute Steps 1 to 6.

[0064] In summary, the present invention can accurately simulate the heat source array in the active region of a power semiconductor device chip, realize the simulation test of the junction temperature and temperature distribution in the active region of the chip during the design and manufacturing process of the power semiconductor device, and experimentally evaluate the actual performance of the thermal design of the power semiconductor device.

[0065] Embodiment

[0066] In order to verify the effectiveness of the proposed solution of the present invention, the following experimental design is carried out.

[0067] In this embodiment, a sapphire-based gallium nitride (GaN) wafer is selected for the simulation test of the temperature distribution in the active region of a GaN power semiconductor device chip.

[0068] Assume that the size of the active region of the GaN power semiconductor device chip is 5 mm × 50 μm, and there is only one strip cell in the active region. The length of the cell is 5 mm, and the gate width of the cell unit is 10 μm. According to the above information, a metal pattern mask is designed with a metal line width of 10 μm and a length of 5 mm. The two ends of the metal line are connected to square metal disks with a side length of 2 mm.

[0069] A 2-inch sapphire-based GaN wafer is selected, where the thickness of the sapphire layer is 430 μm and the thickness of the undoped GaN layer is 4 μm. According to the designed metal pattern mask, a 1-μm-thick silver metal pattern is deposited on the surface of the GaN wafer by lithography.

[0070] A square chip sample with a side length of 15 mm is cut from the GaN wafer. With the metal pattern facing up, it is placed on a hot stage, and the hot stage is installed on the stage of a confocal Raman spectrometer. A temperature measurement point is set every 25 °C, and the Raman spectral signal of the GaN layer in the range from room temperature to 400 °C is measured using confocal Raman spectroscopy. The Raman characteristic temperature curve of the GaN layer is calibrated according to the E2 characteristic peak as:

[0071]

[0072] The bottom surface of the chip sample is connected to the package heat dissipation structure, and the metal pattern on the surface of the chip sample, a 1.0000 Ω precision resistor, and a DC power supply are connected in series to form a DC power supply loop.

[0073] The chip sample connected to the DC power supply loop and the device package heat dissipation structure are installed on the stage of the confocal Raman spectrometer. The output of the DC power supply is adjusted, and it is measured that U1 = 0.709 V and U1 = 7.80 V. The target heat generation power P of the heat source in the active region of the chip sample is simulated to be 5.530 W;

[0074] After reaching the target heat generation power P, the Raman spectral signals at different distance positions in the vertical direction of the center point of the metal line are collected using a confocal Raman spectrometer, and the temperature distribution is calculated by substituting into the calibrated Raman characteristic temperature curve f(T) as Figure 3 shown. It can be seen from the figure the temperature distribution at different distance positions from the metal line, where the junction temperature is 121.3 ± 3.8 °C, and the spatial resolution of the temperature measurement is less than or equal to 1 μm.

[0075] The above embodiments show that the method proposed by the present invention can effectively simulate the heat generation of the heat source in the active region of the power semiconductor device chip based on the semiconductor wafer, and at the same time can achieve the measurement of the temperature distribution with high spatial resolution in the active region of the chip. This means that this method can realize the simulation test of the temperature distribution in the active region of the chip during the design and manufacturing process of power semiconductor devices, and experimentally evaluate the actual performance of the thermal design of power semiconductor devices.

[0076] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0077] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for simulating and testing the temperature distribution in the active region of a power semiconductor device chip, characterized in that, It includes the following steps: Step 1: Collect the active region size of the power semiconductor device chip, the cell pattern size, layout, and the gate size information of the cell unit, and design the metal pattern mask accordingly; Step 2: Select a semiconductor wafer on which the semiconductor multi-layer structure growth is completed and the surface semiconductor layer is not doped, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer; Step 3: Cut out a chip sample from the semiconductor wafer deposited with the metal pattern, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage; Step 4: Connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit; Step 5: Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, adjust the output of the DC power supply, simulate the heat generation of the heat source in the active region of the chip sample and reach the target heat generation power P; Step 6: Measure the Raman spectrum signals at different positions on the surface semiconductor layer of the chip sample under the target heat generation power P, calculate the temperature distribution in the active region of the chip sample according to the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device.

2. The method for simulating and testing the temperature distribution of the active region of a power semiconductor device chip according to claim 1, wherein In Step 1, collecting the active region size of the power semiconductor device chip, the cell pattern size, layout, and the gate size information of the cell unit, and designing the metal pattern mask accordingly, specifically: Collect the active region size of the power semiconductor device chip, the cell unit pattern size, layout, and the gate size information within the active region; Design the metal pattern mask. For strip-shaped cells, the metal pattern mask includes metal wires and metal disks. Among them, the metal wires are used to simulate the heat source within the cell unit. The metal wires are parallel to each other, the width of the metal wire is set as the gate width, and the length of the metal wire is set as the cell unit length; the metal disks are arranged outside the active region at both ends of the metal wire, connecting all the metal wires to achieve the parallel connection of the metal wires. The side length of the metal disk is greater than or equal to 1 mm and is used to connect the DC power supply circuit; for square cells, the metal pattern mask further includes strip-shaped metal bands. The strip-shaped metal bands are arranged in the cell interval area in the extension direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip-shaped metal bands interconnect all the metal wires to form a mesh metal pattern.

3. A method for simulating and testing the temperature distribution of the active region of a power semiconductor device chip according to claim 1, characterized in that, In Step 2, selecting a semiconductor wafer on which the semiconductor multi-layer structure growth is completed and the surface semiconductor layer is not doped, and depositing the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer, specifically: Select metal silver with excellent electrical conductivity as the metal pattern material, and deposit the metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer on which the semiconductor multi-layer structure is completed and the surface semiconductor layer is not doped using a lithography process. The thickness range of the metal pattern is 100 nm to 1 μm.

4. A method for simulating and testing the temperature distribution in the active region of a power semiconductor device chip according to claim 1, characterized in that, In Step 3, cutting out a chip sample from the semiconductor wafer deposited with the metal pattern, and calibrating the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage, specifically: A chip sample is cut from a semiconductor wafer with a deposited metal pattern. The metal pattern facing upward, it is placed on a hot stage, and the hot stage is installed on the confocal Raman spectrometer stage. The hot stage is controlled to rise from room temperature to 400 °C, with a temperature measurement point set every 10 - 30 °C. The Raman spectral signal of the semiconductor layer on the surface of the chip sample is collected at each temperature measurement point using a confocal Raman spectrometer. The laser wavelength of the confocal Raman spectrometer is selected as 532 nm, the laser power is controlled below 0.5 mW, and the longitudinal measurement depth is less than or equal to 4 μm; Find the Raman spectral characteristic peak corresponding to the surface semiconductor layer, obtain the displacement value of the characteristic peak through baseline calibration and Gaussian model peak fitting, perform a quadratic polynomial fitting on the displacement values of the characteristic peaks at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample. The specific expression is: ； where f is the characteristic peak displacement value, with the unit of cm -1 ; T is the temperature, with the unit of K, and a, b, and c are the fitting coefficients of the quadratic term, linear term, and constant term, respectively.

5. A method for simulating and testing the temperature distribution of the active region of a power semiconductor device chip according to claim 1, characterized in that, In step 4, connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit. Specifically: Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat of the active region heat source of the chip sample to dissipate downward; Connect the metal pattern on the surface of the chip sample in series to the DC power supply circuit. The DC power supply circuit also includes a DC power supply and a precision resistor, where the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

6. The simulation test method for the temperature distribution of the active region of a power semiconductor device chip according to claim 1, wherein, In step 5, install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, adjust the output of the DC power supply, and simulate the heat generation of the active region heat source of the chip sample to reach the target heat generation power P. Specifically: Install the chip sample connected to the DC power supply circuit and the device package heat dissipation structure on the stage of the confocal Raman spectrometer, adjust the output of the DC power supply, and simulate the heat generation of the active region heat source of the chip sample to reach the target heat generation power P; Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern, and calculate the target heat generation power P of the active region heat source of the chip sample. The specific formula is as follows: ； In the formula, P is the heat generation power, with the unit of W; R is the resistance value of the precision resistor, with the unit of Ω; U1 is the voltage across the precision resistor, with the unit of V; U2 is the voltage across the metal pattern, with the unit of V.

7. A method for simulating and testing the temperature distribution in the active region of a power semiconductor device chip according to claim 1, characterized in that, In step 6, measure the Raman spectral signals at different positions on the surface semiconductor layer of the chip sample under the target heat generation power P, calculate the temperature distribution of the active region of the chip sample based on the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device. Specifically: After reaching the target heat generation power P, perform Raman spectral signal sampling on different positions of the surface semiconductor layer of the chip sample using the same confocal Raman spectrometer sampling parameters as in step 3. The spatial resolution of the signal sampling is less than or equal to 1 μm; Substitute the Raman characteristic temperature curve f(T) calibrated in step 3 to calculate the temperature distribution of the active region of the chip sample under the target heat generation power; Evaluate the thermal design performance of the power semiconductor device. If the junction temperature and temperature distribution uniformity of the active region of the chip sample both meet the design requirements, the thermal design of the power semiconductor device meets the standard; If the junction temperature and the temperature distribution uniformity of the active region of the chip sample do not meet the design requirements, it is necessary to optimize the thermal design of the power semiconductor device.

8. A simulation test system for the temperature distribution in the active region of a power semiconductor device chip, characterized in that, Implement the simulation test method for the temperature distribution of the active region of the power semiconductor device chip according to any one of claims 1-7, to achieve the simulation test of the temperature distribution of the active region of the power semiconductor device chip, and execute steps 1 to 6 in six modules respectively.

Images