Electronic package and fabrication method thereof

Abstract

An electronic package and a method of fabricating the same are provided, including providing a first carrier structure and a second carrier structure having a thickness smaller than that of the first carrier structure, disposing at least one first electronic component on the first carrier structure, and disposing at least one second electronic component on the second carrier structure. The first electronic component and the second electronic component are wrapped by a wrapping layer, so that the second electronic component can be arranged on the second bearing structure by adopting a packaging module, and the problem that the packaging module is too high is avoided.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an electronic package that can meet the thinning requirements and a manufacturing method thereof. Background Art

[0002] In order to ensure the continuous miniaturization and multi-functionality of electronic products and communication devices, semiconductor packages need to be developed towards smaller sizes to facilitate the connection of multiple pins and have high functionality. In addition, as the computing speed of chips is getting faster and the operating voltage is getting lower, the requirements for signal integrity and power integrity are also increasing. Therefore, the integration of system-on-chip with memory modules or passive modules has become a trend.

[0003] Figure 1 is a schematic cross-sectional view of a conventional semiconductor package 1. As Figure 1 shown, the semiconductor package 1 includes: a carrier structure 10, a system-on-chip 11 disposed on the carrier structure 10, a stacked chip group 12 disposed on the carrier structure 10, and a packaging colloid 18 that encapsulates the system-on-chip and the stacked chip group 12 (such as a memory module).

[0004] However, in the conventional semiconductor package 1, the system-on-chip 11 and the stacked chip group 12 are both disposed on the surface of the same carrier structure 10, so that the height of the packaging colloid 18 needs to match the height of the stacked chip group 12, resulting in difficulty in reducing the height of the semiconductor package 1 and thus unable to meet the thinning requirements. At the same time, the system-on-chip 11 cannot be exposed from the packaging colloid 18, which affects its heat dissipation efficiency.

[0005] Therefore, how to overcome the problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0006] In view of the above-mentioned various deficiencies of the prior art, the present invention provides an electronic package, including: a first carrier structure having a first circuit layer; a first electronic component disposed on the first carrier structure and electrically connected to the first circuit layer; a second carrier structure disposed at a distance from the first carrier structure and having a second circuit layer, wherein the thickness of the second carrier structure is different from the thickness of the first carrier structure; a second electronic component disposed on the second carrier structure and electrically connected to the second circuit layer; and a coating layer formed on the first carrier structure and the second carrier structure to encapsulate the first electronic component and the second electronic component, wherein the first electronic component is exposed from the coating layer.

[0007] The present invention also provides a method for manufacturing an electronic package, including: disposing a first carrier structure having a first circuit layer and a second carrier structure having a second circuit layer on a support member at intervals, wherein the thickness of the second carrier structure is different from that of the first carrier structure; disposing a first electronic component on the first carrier structure such that the first electronic component is electrically connected to the first circuit layer, and disposing a second electronic component on the second carrier structure such that the second electronic component is electrically connected to the second circuit layer; forming a coating layer on the first carrier structure and the second carrier structure such that the coating layer covers the first electronic component and the second electronic component, wherein the first electronic component is exposed from the coating layer; and removing the support member.

[0008] In the foregoing electronic package and its manufacturing method, the side surfaces of the first carrier structure and the second carrier structure are concave-convex. For example, the concave-convex side surfaces of the first carrier structure face the concave-convex side surfaces of the second carrier structure. Further, the protruding portions of the first carrier structure and the protruding portions of the second carrier structure are arranged in an interleaved manner. Alternatively, the side surfaces of the first carrier structure and the second carrier structure are flat and arranged adjacent to each other side by side.

[0009] In the foregoing electronic package and its manufacturing method, the first electronic component and / or the second sub-component are partially exposed from the coating layer.

[0010] In the foregoing electronic package and its manufacturing method, the side surface of the coating layer is flush with the side surface of the first carrier structure and / or the side surface of the second carrier structure.

[0011] In the foregoing electronic package and its manufacturing method, the coating layer covers the side surface of the first carrier structure and / or the side surface of the second carrier structure.

[0012] In the foregoing electronic package and its manufacturing method, the thickness of the second carrier structure is less than or greater than the thickness of the first carrier structure.

[0013] In the foregoing electronic package and its manufacturing method, there is also a conductive structure electrically connecting the first carrier structure and the second carrier structure. For example, the conductive structure includes at least one conductive wire body or at least one bridging element. Further, the bridging element is a bridging chip, a bridging substrate or an RDL structure.

[0014] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, different carrier structures are mainly provided in a single package. Through the design that the thickness of the second carrier structure is less than that of the first carrier structure, the second electronic component can be arranged on the second carrier structure by using a packaging module, so as to avoid the problem of excessive height of the packaging module. Therefore, compared with the prior art, the height of the coating layer of the electronic package of the present invention does not need to match the height of the second electronic component, and thus the coating layer can be thinned according to requirements, so as to effectively reduce the height of the electronic package, make the electronic package of the present invention meet the requirement of thinning, and at the same time expose the first electronic component from the coating layer to improve the heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. is a cross-sectional schematic view of a conventional semiconductor package.

[0016] Figures 2A to 2C FIG. is a cross-sectional schematic view of the manufacturing method of the electronic package of the present invention.

[0017] Figure 2B-1 is Figure 2B top view schematic diagram of

[0018] Figure 2B-2 is Figure 2B top view schematic diagram of another embodiment of

[0019] Figure 2C-1 is Figure 2C cross-sectional schematic view of another embodiment of

[0020] Figures 3A to 3C FIG. is a cross-sectional schematic view of another embodiment of the electronic package of the present invention.

[0021] Figures 4-1 to 4-3 FIG. is a cross-sectional schematic view of yet another embodiment of the electronic package of the present invention.

[0022] MAIN COMPONENT SYMBOL DESCRIPTION

[0023] 1 Semiconductor package

[0024] 10 Carrier structure

[0025] 11 System-on-chip

[0026] 12 Stacked chip group

[0027] 18 Encapsulation colloid

[0028] 2, 3, 4 Electronic package

[0029] 20 First carrier structure

[0030] 200 First insulating layer

[0031] 201 First circuit layer

[0032] 20c, 30c, 28c, 48c sides

[0033] 202, 302 protrusions

[0034] 21 First electronic component

[0035] 21a Active surface

[0036] 21b Non - active surface

[0037] 22 First passive component

[0038] 23 First conductive bump

[0039] 24, 34 Conductive structures

[0040] 25 Third electronic component

[0041] 28, 48 Coating layers

[0042] 28a First surface

[0043] 28b Second surface

[0044] 29 Conductive component

[0045] 30 Second carrier structure

[0046] 300 Second insulating layer

[0047] 301 Second circuit layer

[0048] 31 Second electronic component

[0049] 310 Encapsulation substrate

[0050] 311 Functional chip

[0051] 312 Encapsulation layer

[0052] 313 Conductive wire

[0053] 32 Second passive component

[0054] 33 Second conductive bump

[0055] 9 Support

[0056] T1, T2 Thicknesses Detailed implementation manners

[0057] The following describes the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0058] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have technical substantial significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration, and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present invention can be implemented.

[0059] Figures 2A to 2C It is a cross-sectional schematic view of the manufacturing method of the electronic package 2 of the present invention.

[0060] As Figure 2A shown, at least one first carrier structure 20 and at least one second carrier structure 30 are provided, and the first carrier structure 20 and the second carrier structure 30 are disposed on a support 9, wherein the thickness T2 of the second carrier structure 30 is less than the thickness T1 of the first carrier structure 20.

[0061] The first carrier structure 20 is in the form of a substrate, such as a packaging substrate having a core layer and a circuit structure or a circuit structure without a core layer (coreless), and it includes at least one first insulating layer 200 and at least one first circuit layer 201 combined with the first insulating layer 200, such as at least one fan-out type redistribution layer (RDL). It should be understood that the first carrier structure 20 can also be other plates for carrying chips, such as a leadframe, a wafer, or other carrier plates having metal routing, etc., and is not limited to the above.

[0062] In this embodiment, there are many manufacturing methods for the first carrier structure 20. For example, a wafer manufacturing process can be used to fabricate the circuit layer, and silicon nitride or silicon oxide can be formed by chemical vapor deposition (CVD) as the insulating layer; alternatively, a general non-wafer manufacturing process can be used to form the circuit layer, that is, a polymer dielectric material with a lower cost is used as the insulating layer, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer, or other materials, etc., which are formed by coating.

[0063] The second carrier structure 30 is in the form of a substrate, such as a packaging substrate having a core layer and a circuit structure or a circuit structure without a core layer (coreless), which includes at least one second insulating layer 300 and at least one second circuit layer 301 combined with the second insulating layer 300, such as at least one fan-out type redistribution layer (RDL). It should be understood that the second carrier structure 30 can also be other boards for carrying chips, such as a leadframe, a wafer, or other carrier boards with metal routing, etc., and is not limited to the above.

[0064] In this embodiment, there are many manufacturing methods for the second carrier structure 30. For example, a wafer manufacturing process can be used to fabricate the circuit layer, and silicon nitride or silicon oxide can be formed by chemical vapor deposition (CVD) as the insulating layer; alternatively, a general non-wafer manufacturing process can be used to form the circuit layer, that is, a polymer dielectric material with a lower cost is used as the insulating layer, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer, or other materials, etc., which are formed by coating.

[0065] Furthermore, the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30 are concave-convex. For example, the concave-convex side surface 20c of the first carrier structure 20 and the concave-convex side surface 30c of the second carrier structure 30 face each other, such as Figure 2B-1 shown, so that the protruding part 202 of the first carrier structure 20 and the protruding part 302 of the second carrier structure 30 are arranged in an interlaced manner to form a complementary structure. Additionally, in other embodiments, such as Figure 2B-2As shown, the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30 are straight and arranged adjacent to each other side by side, without forming unevenness.

[0066] The support member 9 is a glass plate, a wafer plate or other suitable plate body.

[0067] As Figure 2B As shown, at least one first electronic component 21 is disposed on the first carrier structure 20 to electrically connect the first electronic component 21 to the first circuit layer 201, and at least one second electronic component 31 is disposed on the second carrier structure 30, and the second electronic component 31 is electrically connected to the second circuit layer 301.

[0068] The first electronic component 21 is an active component, a passive component or a packaging module. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0069] In this embodiment, the first electronic component 21 is a semiconductor chip, which has opposite working surfaces 21a and non-working surfaces 21b. The working surface 21a has a plurality of electrode pads (not shown in the figure), and these electrode pads are disposed on the first carrier structure 20 in a flip-chip manner through a plurality of first conductive bumps 23 and electrically connected to the first circuit layer 201.

[0070] Furthermore, at least one first passive component 22 can be disposed on the first carrier structure 20.

[0071] The second electronic component 31 is an active component, a passive component or a packaging module. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor.

[0072] In this embodiment, the second electronic component 31 is a packaging module, which includes a packaging substrate 310, at least one or more functional chips 311 disposed on the packaging substrate 310, and a packaging layer 312 covering the functional chips 311. The packaging substrate 310 is disposed on the second carrier structure 30 through a plurality of second conductive bumps 33 and electrically connected to the second circuit layer 301. For example, a plurality of stacked functional chips 311 are disposed on the packaging substrate 310, and these functional chips 311 are electrically connected to the packaging substrate 310 in a wire bonding manner through a plurality of wires 313. It should be understood that the manner in which the functional chips 311 are electrically connected to the packaging substrate 310 is various and is not limited to the above.

[0073] Furthermore, the encapsulation layer 312 is an insulating material, such as polyimide (PI), dry film, encapsulation colloid such as epoxy resin, or molding compound, which can be formed on the encapsulation substrate 310 by lamination, coating, or molding.

[0074] In addition, at least one second passive component 32 can be disposed on the second carrier structure 30.

[0075] Such as Figure 2C As shown, the first carrier structure 20 and the second carrier structure 30 are electrically connected through the conductive structure 24, and then a coating layer 28 is formed on the support 9 so that the coating layer 28 covers the first carrier structure 20 and the second carrier structure 30, the first electronic component 21, the first passive component 22, the second electronic component 31, the second passive component 32, the first conductive bumps 23 and the second conductive bumps 33, and the conductive structure 24. Then, the support 9 is removed to expose the first carrier structure 20 and the second carrier structure 30 for bonding a plurality of conductive components 29 on the first carrier structure 20 and the second carrier structure 30, and a singulation process is performed to obtain the electronic package 2 of the present invention. Subsequently, the electronic package 2 can be placed on an electronic device (not shown) such as a circuit board through the conductive components 29.

[0076] The conductive structure 24 includes at least one conductive wire, such as a bonding wire, which electrically connects the first circuit layer 201 and the second circuit layer 301. In other embodiments, such as Figures 3A to 3C As shown in the electronic package 3, the conductive structure 34 can include at least one bridging element, such as a bridging chip, a bridging substrate, or a redistribution layer (RDL) structure, without particular limitation. Further, as Figure 3A and Figure 3B As shown, in one embodiment, the conductive structure 34 can straddle the upper surface or the lower surface of the first carrier structure 20 and the second carrier structure 30 to electrically connect the first circuit layer 201 and the second circuit layer 301. Or, as Figure 3C As shown, in another embodiment, a plurality of the conductive structures 34 can simultaneously straddle the upper surface and the lower surface of the first carrier structure 20 and the second carrier structure 30, thereby electrically connecting the first circuit layer 201 and the second circuit layer 301.

[0077] The coating layer 28 is an insulating layer having opposite first surface 28a and second surface 28b, so that its second surface 28b is bonded to the support 9 during fabrication.

[0078] In this embodiment, the material for forming the coating layer 28 can be, for example, polyimide (PI), dry film, encapsulation colloid such as epoxy resin (epoxy), or molding compound. For example, the coating layer 28 is formed on the support 9 by means of lamination, coating, or molding. It should be understood that the material for forming the coating layer 28 can be the same as or different from the material for forming the encapsulation layer 312.

[0079] Furthermore, the second electronic component 31 and the second passive component 32 are not exposed on the first surface 28a of the coating layer 28, but part of the material of the coating layer 28 can be removed as required to expose the non-functional surface 21b of the first electronic component 21. For example, part of the material of the coating layer 28 is removed through a planarization process such as grinding, so that the non-functional surface 21b of the first electronic component 21 is flush with the first surface 28a of the coating layer 28 (as Figure 2C shown). Additionally, in other embodiments, as Figure 2C-1 shown, the non-functional surface 21b of the first electronic component 21 can also be covered by the coating layer 28 and not exposed outside the coating layer 28.

[0080] Additionally, at least one third electronic component 25 for electrically connecting the first circuit layer 201 and the second circuit layer 301 can be arranged as required on the side of the first carrier structure 20 and the second carrier structure 30 where the coating layer 28 is exposed. For example, the third electronic component 25 is an active component, a passive component, or an encapsulation module. Among them, the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0081] The conductive element 29 is electrically connected to the first two circuit layers 201 and the second circuit layer 301.

[0082] In this embodiment, the conductive element 29 can be a metal column such as a copper pillar, a metal bump coated with an insulating block, a solder ball, a solder ball having a core copper ball (Cu core ball), or other suitable conductive structures, etc., and its shape is not particularly limited, such as a cylinder, an elliptical cylinder, or a polygonal cylinder is acceptable.

[0083] Furthermore, when performing the dicing process as required, the side surface 28c of the coating layer 28 of the electronic package 2 can be made flush with the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30 (as Figure 2C shown). Or, as Figure 4-1As shown in the electronic package 4, the coating layer 48 can cover the side surface 20c of the first carrier structure 20, but expose the side surface 30c of the second carrier structure 30, so that the side surface 30c of the second carrier structure 30 and the side surface 48c of the coating layer 48 are coplanar. Alternatively, as Figure 4-2 shown in the electronic package 4, the coating layer 48 can cover the side surface 30c of the second carrier structure 30, but expose the side surface 20c of the first carrier structure 20, so that the side surface 20c of the first carrier structure 20 and the side surface 48c of the coating layer 48 are coplanar. Or, as Figure 4-3 shown in the electronic package 4, the coating layer 48 can cover both the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30.

[0084] Therefore, in the manufacturing method of the electronic packages 2, 3, 4 of the present invention, different carrier structures are mainly provided in the same package to place different electronic components. For example, by providing a second carrier structure 30 with a thinner thickness T2, the second electronic component 31 as the packaging module is disposed on the second carrier structure 30. Therefore, compared with the prior art, the height of the coating layer 28 of the present invention does not need to match the height of the second electronic component 31, and thus the coating layer 28 can be thinned according to requirements (for example, exposing the non-functional surface 21b of the first electronic component 21), so as to effectively reduce the height of the electronic packages 2, 3, 4, and make the electronic packages 2, 3, 4 of the present invention effectively thinned, thereby meeting the development trend of being thin, light, short, and small.

[0085] The present invention also provides an electronic package 2, 3, 4, including: a first carrier structure 20 having a first circuit layer 201, a first electronic component 21, a second carrier structure 30 having a second circuit layer 301, a second electronic component 31, and a coating layer 28.

[0086] The first electronic component 21 is disposed on the first carrier structure 20 and electrically connected to the first circuit layer 201.

[0087] The second carrier structure 30 is arranged at a distance from the first carrier structure 20, wherein the thickness T2 of the second carrier structure 30 is less than the thickness T1 of the first carrier structure 20.

[0088] The second electronic component 31 is disposed on the second carrier structure 30 and electrically connected to the second circuit layer 301.

[0089] The coating layer 28 is formed on the first carrier structure 20 and the second carrier structure 30 to cover the first electronic component 21 and the second electronic component 31.

[0090] In one embodiment, the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30 are concave-convex. For example, the concave-convex side surface 20c of the first carrier structure 20 and the concave-convex side surface 30c of the second carrier structure 30 face each other. Further, the protruding portions 202 of the first carrier structure 20 and the protruding portions 302 of the second carrier structure 30 are arranged in an interleaved manner. In another embodiment, the side surface 20c of the first carrier structure 20 and the side surface 30c of the second carrier structure 30 are flat.

[0091] In one embodiment, the first surface 28a of the encapsulation layer 28 is flush with the surface (non-functional surface 21b) of the first electronic component 21. In another embodiment, the first surface 28a of the encapsulation layer 28 covers the first electronic component 21 and the second electronic component 31.

[0092] In one embodiment, the side surface 28c of the encapsulation layer 28 is flush with the side surface 20c of the first carrier structure 20 and / or the side surface 30c of the second carrier structure 30.

[0093] In one embodiment, the encapsulation layer 48 covers the side surface 20c of the first carrier structure 20 and / or the side surface 30c of the second carrier structure 30.

[0094] In one embodiment, the electronic packages 2, 3, 4 further include conductive structures 24, 34 electrically connecting the first carrier structure 20 and the second carrier structure 30. For example, the conductive structures 24, 34 include at least one conductive wire or at least one bridging element. Further, the bridging element is a bridging chip, a bridging substrate or a redistribution layer (RDL) structure.

[0095] In summary, for the electronic package and its manufacturing method of the present invention, by providing different carrier structures in a single package, and the design that the thickness of the second carrier structure is less than the thickness of the first carrier structure, the second electronic component can be disposed on the second carrier structure by using a packaging module to avoid the problem of excessive height of the packaging module. Therefore, compared with the prior art, the height of the encapsulation layer of the electronic package of the present invention does not need to match the height of the second electronic component, and thus the encapsulation layer can be thinned as required to effectively reduce the height of the electronic package, making the electronic package of the present invention meet the thinning requirement. At the same time, the first electronic component can be exposed from the encapsulation layer to improve the heat dissipation efficiency.

[0096] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, and are not used to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the rights protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A first carrier structure having a first circuit layer; A first electronic component disposed on the first carrier structure and electrically connected to the first circuit layer; A second carrier structure disposed at a distance from the first carrier structure and having a second circuit layer, wherein the thickness of the second carrier structure is different from the thickness of the first carrier structure; A second electronic component disposed on the second carrier structure and electrically connected to the second circuit layer; and A coating layer formed on the first carrier structure and the second carrier structure to coat the first electronic component and the second electronic component.

2. The electronic package according to claim 1, wherein, The side surfaces of the first carrier structure and the second carrier structure are concave-convex.

3. The electronic package according to claim 2, wherein The concave-convex side surfaces of the first carrier structure and the second carrier structure face each other and are arranged in an interleaved manner.

4. The electronic package according to claim 1, wherein, The side surfaces of the first carrier structure and the second carrier structure are flat and arranged adjacent to each other side by side.

5. The electronic package according to claim 1, wherein, The side surface of the coating layer is flush with the side surface of the first carrier structure and / or the side surface of the second carrier structure.

6. The electronic package according to claim 1, wherein The coating layer covers the side surface of the first carrier structure and / or the side surface of the second carrier structure.

7. The electronic package according to claim 1, wherein The electronic package further includes a conductive structure electrically connecting the first carrier structure and the second carrier structure.

8. The electronic package according to claim 7, wherein, The conductive structure includes at least one conductive wire or at least one bridging element.

9. The electronic package according to claim 8, wherein The bridging element is a bridging chip, a bridging substrate or a redistribution layer structure.

10. The electronic package according to claim 1, wherein, The thickness of the second carrier structure is less than or greater than the thickness of the first carrier structure.

11. The electronic package according to claim 1, wherein The first electronic component and / or the second sub-component are partially exposed from the coating layer.

12. A manufacturing method of an electronic package, comprising: Disposing a first carrier structure having a first circuit layer and a second carrier structure having a second circuit layer at a distance on a support, wherein the thickness of the second carrier structure is different from the thickness of the first carrier structure; Disposing a first electronic component on the first carrier structure to electrically connect the first electronic component to the first circuit layer, and disposing a second electronic component on the second carrier structure to electrically connect the second electronic component to the second circuit layer; Forming a coating layer on the first carrier structure and the second carrier structure to coat the first electronic component and the second electronic component; and Removing the support.

13. The manufacturing method of the electronic package as described in claim 12, wherein, The side surfaces of the first carrier structure and the second carrier structure are concave-convex.

14. The method for manufacturing the electronic package as described in claim 13, wherein, The concave-convex side surfaces of the first carrier structure and the second carrier structure face each other and are arranged in an interleaved manner.

15. The method for manufacturing an electronic package as claimed in claim 12, wherein, The side surfaces of the first carrier structure and the second carrier structure are flat and arranged adjacent to each other side by side.

16. The method for manufacturing an electronic package according to claim 12, wherein, The side surface of the coating layer is flush with the side surface of the first carrier structure and / or the side surface of the second carrier structure.

17. The method for manufacturing an electronic package as described in claim 12, wherein, The coating layer covers the side surface of the first carrier structure and / or the side surface of the second carrier structure.

18. The method for manufacturing an electronic package according to claim 12, wherein, The manufacturing method further includes providing a conductive structure electrically connecting the first carrier structure and the second carrier structure.

19. The method for manufacturing an electronic package as described in claim 18, wherein, The conductive structure includes at least one conductive wire or at least one bridging element.

20. The method for manufacturing an electronic package according to claim 19, wherein, The bridging element is a bridging chip, a bridging substrate or a redistribution layer structure.

21. The method for manufacturing an electronic package according to claim 12, wherein, The thickness of the second carrier structure is less than or greater than the thickness of the first carrier structure.

22. The method for manufacturing an electronic package as described in claim 12, wherein, The first electronic component and / or the second sub-component are partially exposed from the coating layer.

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