Semiconductor power device and preparation method thereof

Abstract

The present application relates to the field of semiconductor technology and discloses a semiconductor power device and a method for fabricating the same. The method comprises: providing a substrate, forming a plurality of gate trenches on the substrate; providing a composite functional layer, the composite functional layer comprising a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on the bottom and sidewalls of the gate trenches; depositing a first polysilicon layer in the gate trenches; depositing an isolation oxide layer in the gate trenches covering the first polysilicon layer and the composite functional layer; forming a third oxide layer on the gate trenches, the third oxide layer covering the sidewalls of the gate trenches and connecting adjacent gate trenches on the top surface of the substrate; depositing a second polysilicon layer in the gate trenches covering the isolation oxide layer; forming a body region and a source region located above the body region on the substrate; forming a source metal layer on the substrate, and forming a drain region by back-metallization of the substrate. The present application optimizes the performance of semiconductor power devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for preparing the same. Background Art

[0002] In semiconductor manufacturing, the SGT (Shield Gate Trench) MOSFET is a new type of semiconductor power device. As a switching device, it is used in motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances. It is a core power control component. The on-resistance (RSP) of the SGT MOSFET is a key parameter. The SGT MOSFET used in related technologies uses a shielded gate structure with thick insulation, which is not conducive to further optimizing the RSP parameter and affects the device's high-density structure requirements. Therefore, optimizing the design to achieve a smaller RSP and higher device integration has become a pressing technical issue. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor power device and a method for manufacturing the same to solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to the first aspect, the technical solution adopted is:

[0005] A method for preparing a semiconductor power device, comprising:

[0006] providing a substrate, and forming a plurality of gate trenches on the substrate;

[0007] Providing a composite functional layer disposed on the gate trench, the composite functional layer comprising a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on the bottom and sidewalls of the gate trench;

[0008] Depositing a first polysilicon layer in the gate trench, etching back the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching depth, and then continuing to etch back the first oxide layer, the silicon nitride layer, and the second oxide layer until they are flush with the first polysilicon layer;

[0009] Depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trench, and forming a third oxide layer on the gate trench, wherein the third oxide layer covers the sidewalls of the gate trench and connects adjacent gate trenches on the top surface of the substrate;

[0010] Depositing a second polysilicon layer covering the isolation oxide layer in the gate trench, etching back the second polysilicon layer from the top surface to the bottom surface of the substrate to a second etching back depth, and then depositing an isolation dielectric layer in the gate trench;

[0011] Performing self-aligned ion implantation and annealing between adjacent gate trenches on the substrate to form a body region and a source region located above the body region;

[0012] A contact hole region connected to the body region and a source metal layer covering the contact hole region are formed on the substrate, and a drain region is formed by back-coating the substrate.

[0013] The present application is further configured as follows: providing a substrate, forming a plurality of gate trenches on the substrate, including:

[0014] Providing an N+ doped substrate, and forming an N- epitaxial layer of the same ion doping type on the N+ doped substrate;

[0015] A plurality of gate trenches with set trench dimensions are formed on the epitaxial layer by etching through a trench mask, wherein the set trench dimensions include a set trench depth, a set trench width, and a set trench inclination angle, wherein the set trench depth is greater than 0.9um, the set trench width includes 0.15-0.3um, and the set trench inclination angle is greater than 88°.

[0016] The present application is further configured as follows: a ratio of a thickness of the first oxide layer to a thickness of the silicon nitride layer is in a range of 0.2-2.

[0017] The present application is further configured as follows: the thickness of the first oxide layer is formed to be 100-300Å, the thickness of the silicon nitride layer is formed to be 100-500Å, and the thickness of the second oxide layer is greater than 100Å.

[0018] The present application is further configured as follows: a pushed-well junction depth of the body region is greater than a pushed-well junction depth of the source region, and a pushed-well junction depth of the source region is greater than a second back-etching depth of the second polysilicon layer.

[0019] The present application is further configured as follows: a first etching back depth of the first polysilicon layer is greater than 0.5um, and a second etching back depth of the second polysilicon layer is greater than 0.1um.

[0020] The present application is further configured as follows: the initial thickness of the first polysilicon layer is 4000-8000Å, the initial thickness of the second polysilicon layer is 4000-8000Å, and the maintained thickness of the third oxide layer on the substrate is 100-400Å.

[0021] The present application is further configured as follows: forming a contact hole region connected to the body region on the substrate includes:

[0022] Etching a contact hole on the substrate using a contact hole mask, wherein the contact hole extends from the top surface to the bottom surface of the substrate into the body region, wherein the opening width of the contact hole is within a range of 0.05-0.2 μm, and the inclination angle of the contact hole is greater than 80°;

[0023] Ions of the same type as those implanted into the body region are implanted into the contact hole and annealed to form the contact hole region.

[0024] The present application is further configured as follows: the source metal layer includes an alloy layer and a surface metal layer, the alloy layer is deposited in the contact hole, and a passivation protection layer and / or a PI protection layer is formed on the surface metal layer.

[0025] According to the second aspect, the technical solution adopted is:

[0026] A semiconductor power device is prepared by the semiconductor power device preparation method described in any of the above embodiments, comprising:

[0027] a substrate, wherein the substrate is provided with a plurality of gate trenches;

[0028] a composite functional layer, disposed on the gate trench, the composite functional layer comprising a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially connected to the bottom and sidewalls of the gate trench, wherein a first polysilicon layer is disposed in the gate trench, the first polysilicon layer is filled on the second oxide layer, an isolation oxide layer and a third oxide layer are disposed in the gate trench, the isolation oxide layer covers the first polysilicon layer and the composite functional layer, the third oxide layer is covered by the isolation oxide layer in the gate trench, extends to the top surface of the substrate, and connects adjacent gate trenches, and a second polysilicon layer and an isolation dielectric layer are disposed in the gate trench, stacked on the isolation oxide layer;

[0029] a body region connected between adjacent gate trenches in the substrate;

[0030] a source region connected to the body region in the substrate;

[0031] a contact hole region, provided on the substrate between adjacent gate trenches and connected to the body region;

[0032] a source metal layer, disposed on the top surface of the substrate and covering the contact hole region;

[0033] The drain region is arranged on the bottom surface of the substrate.

[0034] In summary, compared with the prior art, the present application discloses a semiconductor power device and a method for preparing the same, the method for preparing the semiconductor power device comprising: forming a plurality of gate trenches on a substrate, configuring a composite functional layer on the gate trench, comprising a first oxide layer, a silicon nitride layer and a second oxide layer sequentially formed on the bottom and sidewalls of the gate trench, depositing a first polysilicon layer in the gate trench, etching back the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching depth, and then continuing to etch back the first oxide layer, the silicon nitride layer and the second oxide layer until they are flush with the first polysilicon layer, depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trench, and forming a third oxide layer on the gate trench, the third oxide layer covering the sidewalls of the gate trench and on the substrate. The top surface of the bottom is connected to the adjacent gate trench, a second polysilicon layer covering the isolation oxide layer is deposited in the gate trench, the second polysilicon layer is etched back from the top surface to the bottom surface of the substrate to a second etched back depth, an isolation dielectric layer is deposited in the gate trench, and self-aligned ion implantation and annealing are performed between adjacent gate trenches on the substrate to form a body region and a source region located above the body region, a contact hole region connected to the body region and a source metal layer covering the contact hole region are formed on the substrate, and a drain region is formed by back gold on the substrate. That is, through the above arrangement, the composite functional layer optimizes the insulation thickness of the gate structure of the power device and optimizes its RSP parameters, and the third oxide layer combined with the self-aligned ion implantation increases the integration density of the power device, thereby improving the performance of the semiconductor power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 This is a flow chart of the method for preparing a semiconductor power device of the present application;

[0037] Figure 2 This is a schematic structural diagram of the first semiconductor power device of the present application;

[0038] Figure 3 This is a schematic structural diagram of the second semiconductor power device of the present application;

[0039] Figure 4 This is a schematic structural diagram of the third semiconductor power device of the present application;

[0040] Figure 5 This is a schematic structural diagram of the fourth semiconductor power device of the present application;

[0041] Figure 6This is a schematic structural diagram of the fifth semiconductor power device of the present application;

[0042] Figure 7 This is a schematic structural diagram of the sixth semiconductor power device of the present application;

[0043] Figure 8 This is a schematic structural diagram of the seventh semiconductor power device of the present application. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0045] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0046] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0047] In the subsequent description, the use of suffixes such as "module", "component" or "unit" to represent elements is only for the purpose of facilitating the description of the present application and has no specific meaning. Therefore, "module", "component" or "unit" can be used interchangeably.

[0048] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0050] Please refer to Figure 1 , and combined Figures 2 to 8 The method for preparing a semiconductor power device according to an embodiment of the present application includes:

[0051] S101 , providing a substrate 1 , and forming a plurality of gate trenches 2 on the substrate 1 .

[0052] In the specific implementation process, refer to Figure 2 The material for forming the substrate 1 can be single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon. The material of the substrate 1 can also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure. It can also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, P atoms can be implanted into single crystal silicon to form an N-type conductive semiconductor substrate, and B atoms can be implanted into single crystal silicon to form a P-type conductive semiconductor substrate, so as to improve the selectivity of the material and the adaptability to the actual production environment.

[0053] In this embodiment, P atoms are implanted into the substrate 1 to form an N-type conductive semiconductor substrate, that is, the substrate 1 is an N+ doped substrate.

[0054] It should be noted that a buried layer and an epitaxial layer 10 stacked in sequence can be formed on the substrate 1. At this time, the functional layers of the semiconductor power device can all be formed on the epitaxial layer 10. It can be understood that the subsequent trench gate structure, body region, source region, and contact hole region of the embodiment of the present application can all be formed on the epitaxial layer 10.

[0055] The epitaxial layer 10 adopts the same ion doping type as the substrate 1 , that is, an N- epitaxial layer 10 of the same ion doping type is formed on the N+ doped substrate 1 .

[0056] In one embodiment, the epitaxial layer 10 may be divided into a plurality of cellular regions to include a large number of repeated basic units of the semiconductor power device, and the gate trench 2 may be regarded as a cellular trench.

[0057] In one embodiment, a substrate 1 is provided, and a plurality of gate trenches 2 are formed on the substrate 1, which may specifically include:

[0058] Providing an N+ doped substrate 1, and forming an N- epitaxial layer 10 of the same ion doping type on the N+ doped substrate 1;

[0059] A plurality of gate trenches 2 with predetermined trench dimensions are formed on the epitaxial layer 10 by etching using a trench mask.

[0060] Among them, setting the trench size includes setting the trench depth, setting the trench width and setting the trench inclination angle. If the trench depth is defined as S and the trench width is defined as K, then S>1um, K includes 0.15-0.3um, that is, the trench depth is set to be greater than 0.9um, the trench width is set to be 0.15-0.3um, and the trench inclination angle is set to be greater than 88°. Therefore, based on the limitation of setting the trench size, the gate trench density per unit area of ​​the power device is improved, thereby improving the integration density of the power device.

[0061] Preferably, the groove width is set to 0.2 μm.

[0062] Optionally, the aspect ratio of the gate trench 2 is greater than 8.

[0063] S102 , providing a composite functional layer 3 , which is disposed on the gate trench 2 . The composite functional layer 3 includes a first oxide layer 31 , a silicon nitride layer 32 , and a second oxide layer 33 , which are sequentially formed on the bottom and sidewalls of the gate trench 2 .

[0064] In the specific implementation process, refer to Figure 3 Specifically, a composite functional layer 3 comprising a first oxide layer 31, a silicon nitride layer 32, and a second oxide layer 33 is designed as an insulating shielding layer on the gate trench 2. This three-layer structure forms a high-performance gate dielectric, thereby effectively controlling the insulation thickness and electric field uniformity, thereby reducing the on-resistance (RSP) of the power device. In particular, the silicon nitride layer 32 sandwiched between the intermediate layers can suppress hot carrier injection, improve thermal stability, and reduce interface state density.

[0065] Furthermore, due to the high dielectric constant characteristics of the silicon nitride layer 32 , compared with conventional oxide layers, the film thickness can be thinner at the same withstand voltage, so as to reduce the width of the gate trench 2 and improve the integration density of power devices.

[0066] The first oxide layer 31 can be formed on the bottom and wall of the gate trench 2 by a thermal oxidation process, and then the silicon nitride layer 32 and the second oxide layer 33 are deposited in sequence, thereby forming a sandwich structure of oxide layer-silicon nitride-oxide layer.

[0067] The semiconductor power device preparation method of the embodiment of the present application, after forming a plurality of gate trenches 2 on the substrate 1, is designed for the gate structure on the gate trench 2. On the one hand, a composite functional layer 3 of a first oxide layer 31-silicon nitride layer 32-second oxide layer 33 is used to form a gate dielectric with excellent performance, and through the coordination of the three-layer structure, the overall insulation thickness and the uniformity of the electric field in the trench are effectively controlled to reduce the RSP of the power device and improve the channel opening performance and voltage resistance of the power device. On the other hand, the silicon nitride layer 32 located in the middle layer of the composite functional layer 3 can not only reduce the overall insulation layer thickness, reduce the trench width, and increase the trench density while maintaining the voltage resistance of the device, but also effectively suppress hot carrier injection, reduce the interface state density, and further improve the comprehensive performance and reliability of the power device.

[0068] Preferably, the ratio range of the thickness of the first oxide layer 31 and the thickness of the silicon nitride layer 32 includes 0.2-2, so as to improve the dielectric performance while ensuring the interface quality. That is, the ratio range of 0.2-2 enables the composite functional layer 3 to have good interface quality and to increase the equivalent gate dielectric capacitance by means of the high dielectric properties of silicon nitride, thereby enhancing the gate control capability and reducing the on-resistance.

[0069] Optionally, the ratio of the thickness of the first oxide layer 31 to the thickness of the silicon nitride layer 32 is 0.8.

[0070] In one embodiment, the first oxide layer 31 is formed to a thickness of 100-300 Å.

[0071] Preferably, the first oxide layer 31 is formed to a thickness of 200Å, thereby forming a dense and high-quality oxide layer at the bottom and sidewalls of the gate trench 2, suppressing the interface trap state density and enhancing the subthreshold characteristics and reliability of the device.

[0072] In one embodiment, silicon nitride layer 32 is formed to a thickness comprised between 100 and 500 Å.

[0073] Preferably, the silicon nitride layer 32 is formed to a thickness of 200Å to serve as a high-k gate dielectric main layer, thereby increasing the gate capacitance per unit area, enhancing channel control, and improving dielectric properties while ensuring interface quality.

[0074] It should be noted that if the thickness of the silicon nitride layer 32 in the embodiment of the present application is less than 100 Å, leakage points are likely to form, and if it is greater than 500 Å, film stress and crack risks are likely to be caused.

[0075] In one embodiment, the second oxide layer 33 is formed to a thickness greater than 100 Å.

[0076] Preferably, the second oxide layer 33 is formed to a thickness of 300Å. As the outermost encapsulation insulating layer of the gate structure, the thickness of 300Å can enhance the breakdown voltage of the trench sidewall and improve the reliable withstand voltage capability of the device.

[0077] In one application scenario, the first oxide layer 31 , the silicon nitride layer 32 , and the second oxide layer 33 included in the composite functional layer 3 are formed to the same thickness.

[0078] The first oxide layer 31 and the second oxide layer 33 are formed of materials including SiO 2 .

[0079] S103 , depositing a first polysilicon layer 41 in the gate trench 2 , etching back the first polysilicon layer 41 from the top surface to the bottom surface of the substrate 1 to a first etching depth, and then continuing to etch back the first oxide layer 31 , the silicon nitride layer 32 and the second oxide layer 33 until they are flush with the first polysilicon layer 41 .

[0080] In the specific implementation process, refer to Figure 4 , the first polysilicon layer 41 and the composite functional layer 3 are successively etched back, that is, the polysilicon layer and the composite functional layer 3 are coplanarized to ensure the alignment accuracy between the layers in the trench and the integrity of the dielectric coating, so that the first polysilicon layer 41 can be used as the embedded source polysilicon of the power device.

[0081] Among them, the first etching depth of the first polysilicon layer 41 is greater than 0.5um. If this first etching depth is defined as H1, that is, H1>0.5um, so that after the polysilicon layer is deposited in the groove, it has a suitable depth to form an effective source shielding structure in the gate trench 2, optimize the electric field distribution at the bottom and side wall of the gate trench 2, and help reduce the on-resistance and improve the voltage resistance performance of the device.

[0082] Optionally, the initial thickness of the first polysilicon layer 41 is 4000-8000Å.

[0083] S104, an isolation oxide layer 5 covering the first polysilicon layer 41 and the composite functional layer 3 is deposited in the gate trench 2, and a third oxide layer 6 is formed on the gate trench 2, wherein the third oxide layer 6 covers the sidewalls of the gate trench 2 and connects adjacent gate trenches 2 on the top surface of the substrate 1.

[0084] In the specific implementation process, refer to Figure 5 and Figure 6The isolation oxide layer 5 isolates the first polysilicon layer 41 and the composite functional layer 3 in the gate trench 2, and the third oxide layer 6 starts from the isolation oxide layer 5, covers the sidewalls of the gate trench 2 to the top surface of the substrate 1 and connects the adjacent gate trenches 2. Therefore, the structural design of the top isolation bridge of the third oxide layer 6 can reduce the design spacing between adjacent gate structures, and also facilitate the realization of a more compact gate arrangement. Combined with the subsequent self-aligned ion implantation process, a higher cell density is obtained to further reduce the on-resistance per unit area. At the same time, the sidewall coverage of the third oxide layer 6 provides a good nucleation platform for the subsequent second polysilicon layer, that is, it provides a regular inner cavity structure for the deposition of the second polysilicon layer to form a complete gate electrode channel.

[0085] In one embodiment, the third oxide layer 6 maintains a thickness of 100-400 Å on the substrate 1 .

[0086] Optionally, the third oxide layer 6 is maintained at a thickness of 300Å on the substrate 1 as a damage barrier layer, so that the oxide layer of a certain thickness can be maintained to effectively absorb the surface impact caused by the injection energy during the subsequent ion implantation process, thereby preventing the ion implantation from causing structural defects or electrical active damage to the oxide layer, silicon nitride layer or crystalline silicon structure at the edge of the groove.

[0087] Furthermore, the bridge-like structure formed by the third oxide layer 6 between adjacent gate trenches 2 can serve as a natural barrier structure for the injection window, preventing the injection from extending too wide or too deep, thereby improving the self-alignment accuracy and symmetry of subsequent body / source injections.

[0088] S105 , depositing a second polysilicon layer 42 covering the isolation oxide layer 5 in the gate trench 2 , etching back the second polysilicon layer 42 from the top surface to the bottom surface of the substrate 1 to a second etching depth, and then depositing an isolation dielectric layer 21 in the gate trench 2 .

[0089] In the specific implementation process, refer to Figure 6 and Figure 7 With the formation of the second polysilicon layer 42 and the isolation dielectric layer 21, the complete trench gate structure is completed. The second polysilicon layer 42 and the first polysilicon layer 41 thereunder constitute a distributed double-layer gate structure.

[0090] The second etching depth of the second polysilicon layer 42 is greater than 0.1 um. If the second etching depth is marked as H2, then H2>0.1 um.

[0091] S106 , performing self-aligned ion implantation and annealing between adjacent gate trenches 2 on the substrate 1 to form a body region 11 and a source region 12 located above the body region 11 .

[0092] In the specific implementation process, refer to Figure 7, self-aligned P- ion implantation is performed between adjacent gate trenches 2 on the substrate 1 to form a body region 11, and N+ ion implantation is performed to form a source region 12, and after annealing the well push-up junction depth of the body region 11 is greater than the pushed-well junction depth of the source region 12, and the pushed-well junction depth of the source region 12 is greater than the second back-etching depth.

[0093] S107 , forming a contact hole region 7 connected to the body region 11 and a source metal layer 8 covering the contact hole region 7 on the substrate 1 , and forming a drain region 9 on the back of the substrate 1 by gold coating.

[0094] In the specific implementation process, refer to Figure 8 , forming a contact hole region 7 connected to the body region 11 on the substrate 1, including: etching a contact hole 71 on the substrate 1 through a contact hole mask, the contact hole 71 extending from the top surface to the bottom surface of the substrate 1 into the body region 11; injecting ions of the same type as the ion implantation type of the body region 11 into the contact hole 71 and annealing to push the well to form the contact hole region 7.

[0095] The source metal layer 8 includes an alloy layer 81 and a surface metal layer 82 , and the alloy layer 81 is deposited in the contact hole 71 .

[0096] Among them, P++ ions of the same type as those injected into the body region 11 are injected into the contact hole 71 and annealed to push the well to form the contact hole region 7. Then, based on the direction from the top surface to the bottom surface of the substrate 1 to penetrate into the body region 11, the P++ ions diffuse out of the contact hole region 7 in the body region 11, and the design of the P++ ion concentration being greater than the P- ion concentration in the body region 11 is utilized, so that the contact hole region 7 forms a graded junction in the body region 11, thereby reducing the Schottky barrier.

[0097] Furthermore, P++ ions of the same type as those implanted in the body region 11 are implanted into the contact hole 71 and annealing is performed to form a well-driven contact hole region 7 . The hole junction depth of the contact hole 71 is greater than the well-driven junction depth of the source region 12 .

[0098] A contact hole 71 is formed on the substrate 1 by etching through a contact hole mask. The opening width of the contact hole 71 is within a range of 0.05-0.2 μm, and the inclination angle of the contact hole 71 is greater than 80°.

[0099] Preferably, the opening width of the contact hole 71 is 0.1 um.

[0100] In combination with the contents of the aforementioned embodiments, the semiconductor power device preparation method of the present application optimizes the insulation thickness of the gate structure of the power device and optimizes its RSP parameters through the composite functional layer 3, improves the integration density of the power device by combining the third oxide layer 6 with self-aligned ion implantation, and when the groove width is set to include 0.15-0.3um and the opening size width of the contact hole 71 includes 0.05-0.2um, compared with the prior art, the cell size of the power device can be reduced to 0.5-0.9um, thereby further improving the integration density of the power device and optimizing its Rsp parameters.

[0101] In one embodiment, the deposited material of the alloy layer 81 includes at least one of Ti, TiN, and W.

[0102] Optionally, the deposited material of the surface metal layer 82 includes Al or Cu, so that the alloy layer 81 and the surface metal layer 82 form a good ohmic contact.

[0103] In one embodiment, a passivation protection layer 83 is formed on the surface metal layer 82 to isolate and protect the source metal layer 8, and a source / gate window is opened based on the passivation protection layer 83, and / or a PI protection layer is formed on the surface metal layer 82.

[0104] The passivation protection layer 83 may include a silicon nitride layer and a silicon oxide layer, and the thickness of the passivation protection layer 83 may range from 0.8 to 2 μm.

[0105] Among them, the thickness of the PI protective layer is greater than 5um.

[0106] The drain region 9 is formed by coating the substrate 1 with gold on the back, which may include thinning the bottom surface of the substrate 1 to a thickness of 50-150 μm, and then depositing a metal layer on the bottom surface of the substrate 1 to form the drain region 9 .

[0107] Preferably, the thinning thickness is 100um.

[0108] Thus, in the method for preparing a semiconductor power device according to an embodiment of the present application, a plurality of gate trenches 2 are formed on a substrate 1, and a composite functional layer 3 is configured on the gate trench 2, including a first oxide layer 31, a silicon nitride layer 32, and a second oxide layer 33 sequentially formed on the bottom and sidewalls of the gate trench 2, a first polysilicon layer 41 is deposited in the gate trench 2, and the first polysilicon layer 41 is etched back from the top surface to the bottom surface of the substrate 1 to a first etch-back depth, and then the first oxide layer 31, the silicon nitride layer 32, and the second oxide layer 33 are further etched back until they are flush with the first polysilicon layer 41, an isolation oxide layer 5 covering the first polysilicon layer 41 and the composite functional layer 3 is deposited in the gate trench 2, and a third oxide layer 6 is formed on the gate trench 2, the third oxide layer 6 covering the sidewalls of the gate trench 2 and connecting adjacent ones on the top surface of the substrate 1. A gate trench 2 is formed, a second polysilicon layer 42 covering the isolation oxide layer 5 is deposited in the gate trench 2, the second polysilicon layer 42 is etched back from the top surface to the bottom surface of the substrate 1 to a second etching depth, an isolation dielectric layer 21 is deposited in the gate trench 2, and self-aligned ion implantation and annealing are performed between adjacent gate trenches 2 on the substrate 1 to form a body region 11 and a source region 12 located above the body region 11, a contact hole region 7 connected to the body region 11 and a source metal layer 8 covering the contact hole region 7 are formed on the substrate 1, and a drain region 9 is formed on the back of the substrate 1. Thus, the insulating thickness of the gate structure of the power device and its RSP parameters are optimized through the composite functional layer 3, and the integration density of the power device is improved by the third oxide layer 6 combined with the self-aligned ion implantation, thereby improving the performance of the semiconductor power device.

[0109] The present application also discloses a semiconductor power device, which is manufactured by the semiconductor power device manufacturing method of any of the above embodiments. Figure 8 The semiconductor power device includes: a substrate 1, the substrate 1 is provided with a plurality of gate trenches 2; a composite functional layer 3, arranged on the gate trench 2, the composite functional layer 3 including a first oxide layer 31, a silicon nitride layer 32 and a second oxide layer 33 sequentially connected to the bottom and sidewall of the gate trench 2, wherein a first polysilicon layer 41 is provided in the gate trench 2, the first polysilicon layer 41 is filled on the second oxide layer 33, an isolation oxide layer 5 and a third oxide layer 6 are provided in the gate trench 2, the isolation oxide layer 5 covers the first polysilicon layer 41 and the composite functional layer 3, and the third oxide layer 6 is provided in the gate trench 2 The sidewalls of the gate trench 2 are covered by an isolation oxide layer 5, extending to the top surface of the substrate 1 and connecting adjacent gate trenches 2, and a second polysilicon layer 42 and an isolation dielectric layer 21 stacked on the isolation oxide layer 5 are provided in the gate trench 2; a body region 11 is connected between adjacent gate trenches 2 in the substrate 1; a source region 12 is connected above the body region 11 in the substrate 1; a contact hole region 7 is provided between adjacent gate trenches 2 on the substrate 1 and connected to the body region 11; a source metal layer 8 is provided on the top surface of the substrate 1 and covers the contact hole region 7; and a drain region 9 is provided on the bottom surface of the substrate 1.

[0110] A buried layer and an epitaxial layer 10 stacked in sequence may be formed on the substrate 1 . In this case, the above-mentioned functional layers of the semiconductor power device may all be formed on the epitaxial layer 10 .

[0111] For other working principles and processes of the semiconductor power device of this embodiment, please refer to the description of the semiconductor power device preparation method of the aforementioned embodiment, which will not be repeated here.

[0112] The semiconductor power device and its preparation method provided by this application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of this application. It should be noted that in this application, the descriptions of each embodiment have their own emphasis. For parts that are not described or recorded in detail in a particular embodiment, please refer to the relevant descriptions of other embodiments.

[0113] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, all possible combinations of the various technical features in the above embodiments are not described. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, as long as there is no contradiction in the combination of these technical features, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor power device, characterized in that: include: Providing an N+ doped substrate, forming an N- epitaxial layer of the same ion doping type on the N+ doped substrate, and etching a plurality of gate trenches with set trench dimensions on the epitaxial layer using a trench mask, wherein the set trench dimensions include a set trench width, a set trench depth, and a set trench tilt angle, wherein the set trench width is 0.2 μm, the set trench depth is greater than 0.9 μm, the set trench tilt angle is greater than 88°, and the gate trench has an aspect ratio greater than 8; Providing a composite functional layer disposed on the gate trench, the composite functional layer comprising a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially formed on a bottom and sidewalls of the gate trench, wherein a ratio of a thickness of the first oxide layer to a thickness of the silicon nitride layer ranges from 0.2 to 2, and wherein the first oxide layer has a thickness of 200 Å, the silicon nitride layer has a thickness of 100 to 500 Å, and the second oxide layer has a thickness of 300 Å; Depositing a first polysilicon layer in the gate trench, where the initial thickness of the first polysilicon layer is 4000-8000 Å, etching back the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching depth, and then continuously etching back the first oxide layer, the silicon nitride layer, and the second oxide layer until they are flush with the first polysilicon layer; Depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trench, and forming a third oxide layer on the gate trench, wherein the third oxide layer covers the sidewalls of the gate trench and connects adjacent gate trenches on the top surface of the substrate, and the thickness of the third oxide layer on the substrate is maintained at 100-400 Å; Depositing a second polysilicon layer covering the isolation oxide layer in the gate trench, wherein the initial thickness of the second polysilicon layer is 4000-8000 Å, etching back the second polysilicon layer from the top surface to the bottom surface of the substrate to a second etching back depth, and then depositing an isolation dielectric layer in the gate trench, wherein the first etching back depth of the first polysilicon layer is greater than 0.5 μm, and the second etching back depth of the second polysilicon layer is greater than 0.1 μm; Performing self-aligned ion implantation and annealing to drive-in a well between adjacent gate trenches on the substrate to form a body region and a source region located above the body region, wherein a driven-in well junction depth of the body region is greater than a driven-in well junction depth of the source region, and a driven-in well junction depth of the source region is greater than a second back-etching depth of the second polysilicon layer; A contact hole is formed on the substrate by etching using a contact hole mask, wherein the contact hole is located between adjacent gate trenches on the substrate and extends from the top surface to the bottom surface of the substrate into the body region, wherein the opening width of the contact hole is within a range of 0.05-0.2 μm and the inclination angle of the contact hole is greater than 80°, and ions of the same type as those implanted in the body region are implanted into the contact hole and annealed to form a well, thereby forming a contact hole region; A source metal layer covering the contact hole area is formed on the substrate, and a drain area is formed on the back of the substrate. The source metal layer includes an alloy layer and a surface metal layer. The alloy layer is deposited in the contact hole, and a passivation protection layer and / or a PI protection layer is formed on the surface metal layer.

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