Determining correlations between power disturbances and data errors in test system

Abstract

An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel and analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT and compare the first data and the second data to determine whether there is a correlation between the power disturbance and the error.

Description

Technical Field

[0001] The present disclosure generally relates to testing a device, and more particularly, to determining whether there is a correlation between power disturbances in the power supplied to a device and bit errors or retry events on a communication channel to the device. Background Art

[0002] A test system is configured to test the operation of an electronic device, referred to as a device under test (DUT). The test system may include test instruments that send signals, including digital and analog signals, to the DUT for testing. The test system may also include a power supply that supplies power to the DUT and a computer bus that is part of the communication channel for communicating with the DUT. Summary of the Invention

[0003] An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT via a communication channel and analyze the first data to identify errors associated with the communication channel; and a power controller configured to receive second data based on power disturbances from the DUT and compare the first data and the second data to determine whether there is a correlation between the power disturbances and the errors. The example system may individually or in combination include one or more of the following features.

[0004] The system may include a power supply configured to supply power to the DUT. The power disturbances may be based on the power supplied to the DUT. The power supply may be configured to operate at a voltage level that sets a margin around the nominal voltage of the DUT. The power controller may be configured to manage the voltage level at the power supply to initiate power disturbances. The power supply may be configured to have a current limit that sets a margin around the maximum current consumption of the DUT. The power controller may be configured to manage the current level at the power supply to initiate power disturbances.

[0005] One or more processing devices may be configured to issue commands to the power controller to control the power supplied to the DUT by the power supply. The power controller may be configured to receive second data from the power supply. The power controller may be configured to timestamp the second data. The power controller may be configured to send the timestamped second data to one or more processing devices. The power controller may be configured to store the second data in a memory.

[0006] One or more processing devices may be configured to store first data in a memory. One or more processing devices may be configured to timestamp the first data. One or more processing devices may be configured to send the timestamped first data to a power controller. Errors from a communication channel may include one or more bit errors. One or more processing devices may be configured to use a bit error test to test for one or more bit errors. The communication channel may include a Peripheral Component Interconnect Express (PCIe) bus or Ethernet.

[0007] The power controller may be configured to generate a timestamped predetermined power perturbation at the DUT. The power perturbation may correspond to the predetermined power perturbation. Second data may be based on the predetermined power perturbation. One or more processing devices may be configured to control the ambient temperature around the DUT such that the ambient temperature changes from below freezing to above freezing but below the maximum operating temperature of the DUT. One or more processing devices may be configured to control the bandwidth of the first data in order to detect a correlation between a power perturbation and an error in the communication channel based on the bandwidth of the first data.

[0008] An example method for testing a device under test (DUT) includes: receiving first data from the DUT via a communication channel; analyzing the first data to identify errors associated with the communication channel; receiving second data based on a power perturbation from the DUT; and comparing the first data and the second data to determine whether there is a correlation between the power perturbation and the error. The example method may individually or in combination include one or more of the following features.

[0009] The method may include powering the DUT using a power supply. The power perturbation may be based on the power supplied to the DUT. Powering the DUT may include operating the power supply at a voltage level that is a margin around the nominal voltage of the DUT. Receiving the second data may include managing the voltage level at the power supply to initiate the power perturbation. The power supply may be configured to have a current limit that is a margin around the maximum current consumption of the DUT.

[0010] The method may include managing the current level at the power supply to initiate the power perturbation. The method may include issuing a command to the power controller to control the power supplied to the DUT by the power supply. The method may include receiving the second data from the power supply. The method may include timestamping the second data. The method may include using the power controller to send the timestamped second data to one or more processing devices. The method may include using the power controller to store the second data in a memory.

[0011] The method may include storing first data in a memory. The method may include timestamping the first data. The method may include sending the timestamped first data to a power controller. An error from a communication channel may include one or more bit errors. The method may include testing the one or more bit errors using a bit error test.

[0012] The communication channel may include a Peripheral Component Interconnect Express (PCIe) bus or Ethernet. The method may include generating a timestamped predetermined power perturbation at the DUT. The power perturbation may correspond to a predetermined power perturbation and the second data is based on the predetermined power perturbation. The method may include controlling the ambient temperature around the DUT such that the ambient temperature changes from below freezing to above freezing but below the maximum operating temperature of the DUT.

[0013] Comparing the first data and the second data may include controlling the bandwidth of the first data to detect a correlation between a power perturbation and an error in the communication channel based on the bandwidth of the first data.

[0014] Any two or more of the features described in this specification (including those included in the Summary of the Invention section) may be combined to form embodiments not specifically described in this specification.

[0015] At least a portion of the devices, systems, and processes described in this specification may be configured or controlled by executing instructions stored on one or more non-transitory machine-readable storage media on one or more processing devices. Examples of non-transitory machine-readable storage media include read-only memory, optical disk drives, memory disk drives, and random access memory. At least a portion of the devices, systems, and processes described in this specification may be configured or controlled using a computing system comprising one or more processing devices and a memory storing instructions executable by the one or more processing devices to perform various control operations. The devices, systems, and processes described in this specification may be configured, for example, by design, construction, composition, arrangement, placement, programming, operation, activation, deactivation, and / or control.

[0016] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description and drawings and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram showing components of an example test system for testing a DUT.

[0018] Figure 2It is a flowchart of an example method for testing a DUT, and the method includes correlating disturbances in the power supplied to the DUT with bit errors and retry events on the communication channel to the DUT.

[0019] Figure 3 It is a block diagram showing an example test system. Detailed implementation

[0020] The example test system is configured to determine whether there is a correlation between power disturbances in the power supplied to the DUT and bit errors or retry events on the communication channel to the DUT. The example test system includes one or more processing devices and a power controller, which can be part of one or more processing devices or a hardware device separate from one or more processing devices. One or more processing devices are configured to send test data to the DUT via the communication channel and identify bit errors and / or retry events in the response to the test data transmitted by the DUT. One or more processing devices are configured to timestamp data representing bit errors and / or retry events and store the timestamped data in a memory. The power controller is configured to monitor power disturbances associated with the power supply that supplies power to the DUT. The power controller is configured to timestamp data representing power disturbances and store the timestamped data in a memory. One or more processing devices are further configured to compare the timestamped data representing bit errors and / or retry events with the timestamped data representing power disturbances to determine whether there is a correlation between the power disturbances and the bit error / retry events. One or more processing devices are configured to store data indicating whether a correlation has been identified and / or output a notification to a user or a computer program based on whether a correlation has been identified or not.

[0021] Figure 1 It is a block diagram of an example component 100 of a test system configured to test a DUT 104. The component 100 can be part of an automatic test equipment (ATE) 300, an example of which is shown in Figure 3 as follows. The component includes a processing device 102, a communication channel 106, an event log 108, a power controller 110, a power supply 112, and a power log 114. The processing device 102, the power controller 110, the event log 108, and the power log 114 can be part of a test instrument that performs tests on the DUT (e.g., included on a test instrument that performs tests on the DUT), or they can be part of a control system that controls the operation of the test system. In some embodiments, each test instrument in the test system can include an instance of the processing device 102, the power controller 110, the event log 108, and the power log 114.

[0022] The processing device 102 may include one or more processing devices of the same type or different types, as described herein. For example, the processing device 102 may include one or more microprocessors and / or programmable integrated circuits with processing capabilities, such as field programmable gate arrays (FPGAs).

[0023] The component 100 may include one or more temperature control devices (not shown), and the one or more temperature control devices can be controlled in response to commands from the processing device. The temperature control device may include one or more heaters to increase the ambient temperature at the test system and / or at the DUT. The temperature control device may include one or more cooling devices (such as fans or Peltier devices) to lower the ambient temperature at the test system and / or at the DUT. One or more heating devices may be configured to make the ambient temperature at the test system and / or at the DUT higher than the freezing point (32 degrees Fahrenheit / 0 degrees Celsius). One or more cooling devices may be configured to make the ambient temperature at the test system and / or at the DUT lower than the freezing point. The processing device 102 is configured (e.g., programmed) to control the temperature control device.

[0024] The communication channel 106 includes one or more communication paths located between the DUT 104 and the test hardware. In some examples, the communication channel may include one or more physical transmission media through which test data is sent to the DUT and through which responses are received from the DUT. The physical transmission media may include, but are not limited to, separate electrical conductors or electrical conductors combined with optical conductors, wireless transmission media, or both optical conductors and wireless transmission media. For example, the communication channel may be or include a high-speed serial bus, such as a Peripheral Component Interconnect Express (PCIe) bus, a PCI bus, or an I2C (Inter-Integrated Circuit, I-squared C) bus. Other types of buses in addition to those listed may be part of the communication channel. The communication channel may be or include Ethernet. In some examples, the communication channel may include a frequency range within which signals are transmitted through a single transmission medium or through multiple transmission media of the same type or different types. Any number of communication channels may be included in the test system, for example, one or more test channels for each DUT to be tested.

[0025] The DUT 104 can be or include any type of electronic device that needs to be tested. The DUT 104 can be or include a storage device, such as a solid state drive (SSD) or a hard disk drive (HDD). The DUT 104 can be a memory device, such as a random access memory (RAM) or a read only memory (ROM). The DUT 104 can be a high performance computing (HPC) device, an input / output (I / O) device, such as a video card, a keyboard, or a computer monitor. The DUT 104 can be an integrated circuit. Other types of DUTs not listed herein can be tested by the test system.

[0026] The power controller 110 can be or include a programmable hardware device, such as one or more microprocessors or other types of processing devices described herein. The power controller 110 can be or include one or more software modules executed on the processing device 102. The power controller 110 can include software components executed on the processing device 102 and dedicated hardware devices that operate in response to signals from one or more software components. The power controller 110 can include a direct connection to the power supply 112 or a network connection to the power supply. For example, the power controller 110 can include a computer bus connection to the power supply.

[0027] The power controller 110 is configured to (e.g., programmed to) manage the voltage and / or current levels output by the power supply 112 to the DUT. For example, the power controller 110 can be configured to send instructions to the power supply 112, and in response, the power supply 112 can adjust its output voltage and / or current to the DUT based on those instructions. For example, the power supply 112 can increase or decrease its output power, voltage, and / or current to the DUT based on those instructions. The power controller 110 is also configured to monitor the power, voltage, and / or current levels output by the power supply 112 to the DUT. For example, the power controller can be configured to send instructions to the power supply 112 requesting the current or previous power output, voltage output, and / or current output of the power supply 112 to the DUT 104, and in response, the power supply 112 can respond with the requested information.

[0028] Power supply 112 can be a programmable power supply. For example, power supply 112 can include on-board intelligence (such as one or more processing devices of the type described herein) to enable the foregoing types of interactions with power supply controller 110 and / or other components of the test system (such as processing device 102). The on-board intelligence can be configured to receive one or more commands from an external device and set and reset voltage, current, and power output levels from power supply 112 based on the commands. Power supply 112 can be configured to operate at a voltage level that sets a margin around the nominal operating voltage of DUT 104 or the maximum operating voltage of the DUT. In one example, the operating voltage of the DUT includes the voltage required for normal DUT operation, and the maximum operating voltage of the DUT includes the maximum voltage that the DUT can tolerate before damage occurs to the DUT. Power supply 112 can be configured to operate at a current level that sets a margin around the nominal current consumption of DUT 104 or the maximum current consumption of the DUT. In one example, the nominal current consumption of the DUT includes the DUT current consumption that occurs during normal DUT operation, and the maximum current consumption of the DUT includes the maximum current that the DUT can tolerate before damage occurs to the DUT.

[0029] The test system also includes computer memory, which can consist of one or more machine-readable storage devices configured to store data. The memory can be internal or external to processing device 102 and / or internal or external to power controller 110. The computer memory can store error event log 108. Error event log 108 can be or include a database that stores timestamped data of the following types. The error event log can be configured to be accessed by processing device 102 and / or power controller 110. The computer memory can also store power log 114. Power log 114 can be or include a database that stores timestamped data of the following types. Power log 114 can be configured to be accessed by processing device 102 and / or power controller 110.

[0030] Figure 2 An example process 200 is shown for determining whether there is a correlation between power disturbances in the power supplied to the DUT and bit errors and / or retry events generated by the DUT. In some embodiments, process 200 can be implemented by processing device 102 in conjunction with power controller 110.

[0031] Process 200 includes the processing device 102 sending (201) test data to the DUT 104 via the communication channel 106. The test data may include test patterns designed to elicit responses from components of the DUT. The response includes response data sent back by the DUT via the communication channel 106 in reply to the test data. The response data may represent operations applied to the DUT based on the test data by the DUT or its individual components. In some examples, the response data may include data packets, each of which is composed of a plurality of bits.

[0032] In some embodiments, the processing device 102 is configured to control the ambient temperature at or around the DUT such that the ambient temperature changes from below freezing to above freezing but below the maximum operating temperature of the DUT, and vice versa. For example, the processing device may send commands to a temperature control device to effect the temperature change. The ambient temperature may affect the operation of the DUT. The change in the operation of the DUT may be reflected by the number and / or type of bit errors in the response data.

[0033] Process 200 receives (202) the response data and analyzes (203) the response data to identify bit errors and / or retry events in the response data. Regarding identifying retry events, for example, transient failures may be caused by an instantaneous loss of network connection or a timeout that occurs when the service is busy. In such a case, the DUT may retry sending the response data. This retry is referred to as a retry event. Retry events may be detected based on information contained in the data packet header or body, for example, identifying the data packet as a retransmission or a previously transmitted packet.

[0034] Regarding identifying bit errors, there are various ways to detect bit errors in data transmission. For example, each data packet in the response data can include added "parity" bits such that the sum of the bits is always odd or even. If the processing device 102 determines that a data packet in the response data contains an improper number of bits, a bit error is detected. In another example, assume the response data includes a byte sequence. Before transmission, a checksum byte or a fixed number of bytes is determined and appended to the message. The processor 102 can perform the same calculation on the received message after subtracting one or more checksum bytes. The result of this calculation is checked against the received checksum, and if they match, the message is assumed to be error-free. If they do not match, a bit error is detected. For example, when implementing forward error correction (FEC), the higher data rate, low latency version of PCIe supports these bit error detection methods, where redundant data is transmitted along with a checksum used to detect errors and separate the errors from the valid data. In another example, PCIe data transmission uses an encoding scheme such as 8-bit to 10-bit (8b / 10b) or 128-bit to 132-bit (128b / 132b) methods. Invalid 10-bit or 128-bit codes can respectively indicate bit errors. Bit error testing methods other than these can also be used.

[0035] When the processing device 102 detects a bit error and / or a retry event from the DUT 104, the processing device timestamps (204) the data representing each bit error and / or retry event. In one example, timestamping can include adding data representing the time when the bit error and / or retry event is detected and / or occurred to the data representing the bit error and / or retry event respectively. In another example, timestamping can include storing (e.g., in a lookup table) the data representing the time when the bit error and / or retry event is detected and / or occurred in association with the data representing the bit error and / or retry event. Any suitable method of timestamping can be used. The timestamped data can be stored (205) in the error event log 108.

[0036] The processing device 102 communicates (205a) with the power controller 114 to control and / or monitor the power output from the power supply 112 to the DUT 104. For example, to control the power output, the processing device 102 may issue one or more commands to the power controller 110 to control the amplitude and / or duration of the power supplied by the power supply 112 to the DUT 104. In response, the power controller 110 may issue commands to the power supply 112 to supply power to the DUT according to the instructions provided by the processing device 102. For example, to monitor the power output, the processing device 102 may issue one or more commands to the power controller 110 to obtain the amount or level of power (e.g., amplitude, duration, or other attributes) supplied by the power supply 112 to the DUT 104. In response, the power controller 110 may issue commands to the power supply 112 to obtain the amount or level of power that the power supply has supplied to the DUT over a period of time, at a specific moment in the past, or currently.

[0037] Process 200 includes receiving (205b) information about power disturbances in the power supply 112 from the power supply 112. Operation 205b may be performed by the power controller alone or in communication with the processing device 102. This information may be received in response to one or more commands issued by the power controller 110 to the power supply 112, or this information may be received by the power controller 110 without being requested from the power supply 112. The power disturbance may be based on a power perturbation (hereinafter simply referred to as "perturbation") experienced by the power supply 112 while delivering power to the DUT 104. The perturbation may include any deviation of the power output from the power supply to the DUT that exceeds the specification or exceeds the acceptable operating range of the power supply when supplying power to the DUT. For example, the power supply 112 is set with a margin to operate around the nominal power of the DUT (referred to herein as "P nominal "). In this example, the perturbation may be defined as ±1% from P nominal deviating from P nominal within a specified time period or at a certain moment, ±2% of P nominal , ±3% of P nominal , ±4% of P nominal , ±5% of P nominal , ±6% of P nominal , ±7% of P nominal , ±8% of P nominal , ±9% of P nominal , ±10% of P nominal , ±20% or more of P nominal . Other values may be used to define the perturbation.

[0038] Power disturbances can be natural or forced. If a power disturbance is not forced by the power controller 110, the power disturbance is considered natural. That is, if the power disturbance is the result of a power perturbation that is independent of commands or control provided to the power supply 112 or other devices external to the power supply, the power disturbance is natural. When the power controller 110 or other devices external to the power supply issue one or more commands to the power supply 112 to produce a power disturbance outside of an acceptable range near the nominal power of the DUT, the power disturbance is considered forced. In some embodiments, forced power disturbances are predetermined in a sense because they are based on instructions from the power controller 110, from the processor 102, or from other components of the test system. Forced power disturbances can be useful because they are controllable. That is, the timing and magnitude of the forced power disturbance are known and controllable, and, therefore, can be used to cause specific detectable bit errors on the communication channel as described herein.

[0039] The received (205b) information regarding the power disturbance can include, for example, the time at which the power disturbance occurred, the duration of the power disturbance, the magnitude of the power disturbance (including voltage and / or current levels), or any other suitable information available to the power controller regarding the power disturbance. Data representing such attributes constitutes information describing the power disturbance.

[0040] Process 200 timestamps (206) the data representing the power disturbance. Operation 206 can be performed by the power controller 110 alone or in communication with the processing device 102. In one example, timestamping can include adding data representing the time at which the power disturbance was detected and / or occurred to the data representing the power disturbance, respectively. In another example, timestamping can include storing (e.g., in a lookup table) data representing the time at which the power disturbance was detected and / or occurred in association with the data representing the power disturbance. Any suitable method of timestamping can be used. The timestamped data can be stored (207) in the power log 114. Operation 207 can be performed by the power controller 110 alone or in communication with the processing device 102.

[0041] After detecting and timestamping a predetermined number (e.g., a statistically significant number) of power disturbances and bit error / retry events, process 200 can analyze (208) the timestamped power disturbances and timestamped bit error / retry events to determine if there is a correlation between the timestamped power disturbances and the timestamped bit error / retry events. For example, processing device 102 can keep track of the number of bit error / retry events and power disturbances that are identified, timestamped, and stored. Processing device 102 can directly retrieve data representing the timestamped bit error and / or retry events from event log 108. Processing device 102 can retrieve this data by requesting data representing the timestamped power disturbances from power controller 110, which directly retrieves the data from power log 114. Alternatively, processing device 102 can directly retrieve data representing the timestamped power disturbances from power log 114.

[0042] The analysis (208) can include a correlation analysis performed during a predefined time window. The time window can be pre-programmed into processing device 102 or determined dynamically based on previous bit error / retry events and power disturbance measurements. Processing device 102 can use any suitable statistical correlation technique to determine the correlation or lack of correlation between the bit error / retry events and the power disturbances. Forced power disturbances can enable process 200 to perform a better correlation between the bit error / retry events and the power disturbances because the magnitude and timing of the power disturbances are known.

[0043] In some embodiments, the correlation analysis (208) includes comparing data representing the bit error / retry events (e.g., first data) with data representing the power disturbances (e.g., second data) to determine if there is a correlation between the bit error / retry events and the power disturbances. For example, as described above, data representing the bit error / retry events within a time window can be compared with data representing the power disturbances within the same time window to determine if there is a correlation between the bit error / retry events and the power disturbances. The comparison can be performed for multiple consecutive windows or for selected non-consecutive windows. In another example, data representing the power disturbances at a particular moment can be compared with data representing the bit error / retry events at the same moment to determine if there is a correlation between the power disturbances and the bit error / retry events. The comparison can be performed for multiple consecutive moments or for selected non-consecutive moments. The selection of the windows and / or moments can be programmed into processing device 102 or determined dynamically as described above.

[0044] In some embodiments, positive and / or negative statistical correlation techniques can be used to determine the correlation or lack of correlation between bit error / retry events and power disturbances. In some embodiments, linear and / or non-linear statistical correlation techniques can be used to determine the correlation or lack of correlation between bit errors and power disturbances. In statistical correlation techniques, simple, multiple, and / or partial statistical correlation techniques can be used to determine the correlation or lack of correlation between bit error / retry events and power disturbances. Communication channels with larger bandwidths may be less susceptible to bit errors than those with smaller bandwidths, which may affect the correlation results. In this regard, in some embodiments, the processing device 102 is configured to control the bandwidth of the communication channel to affect the correlation. This can be done, for example, by reducing or increasing the physical medium and / or frequency over which communication occurs.

[0045] Process 200 stores (209) data representing positive and / or negative correlation or lack of positive and / or negative correlation between bit error / retry events and power disturbances, e.g., along with time data identifying the window and / or moment when the bit error / retry events and power disturbances were detected or occurred. Process 200 can report this information, for example, by displaying the information on a graphical user interface or by sending the information to an external computing system.

[0046] Figure 3 is a block diagram showing the components of an example ATE 300 including a test device (referred to herein as a "tester") 301 and a control system 302. Figure 1 The component 100 can be part of the ATE 300.

[0047] The tester 301 includes a test head 303 and a device interface board (DIB) 304 that is physically and electrically connected to the test head 303. In this example, the DIB 304 includes a circuit board that includes a mechanical interface and an electrical interface at site 305. One or more DUTs (such as DUT 308) are connected to each of those sites for ATE testing. The DUT 308 can be Figure 1 an embodiment of the DUT 104.

[0048] In addition, the DIB 304 can include connectors, conductive traces, conductive layers, and circuitry for routing signals between test instruments in the test head 303, DUTs connected to the DIB sites, and other circuitry in the ATE. Power (including voltage and current) can run via one or more layers in the DIB to the DUTs connected to the DIB. The power can be provided by a power supply 310, which can be Figure 1 an embodiment of the power supply 112.

[0049] The test head 303 includes a plurality of test instruments 311a to 311n, each of which can be configured as appropriate to perform tests and / or other functions. Although only four test instruments are shown, the ATE 10 can include any suitable number of test instruments, including one or more test instruments located outside the test head 303. The test instrument can be a hardware device that can include one or more processing devices and / or other circuitry. The test instrument can be configured (e.g., programmed) to output commands to test the DUT held on the DIB. The commands to test the DUT can be or include instructions, signals, data, parameters, variables, test patterns, and / or any other information designed to elicit a response from the DUT. In some embodiments, all or part of the process 200 can be executed in one test instrument or multiple test instruments. For example, Figure 2 the operations included therein can be distributed over one or more test instruments and / or the control system 302.

[0050] One or more (e.g., all) test instruments can be configured to receive from the DUT a response to the commands sent from the ATE to the DUT. The response is in the form of response data. The test instrument can be configured to analyze the response data to determine whether the DUT has passed or failed the test. The test instrument can be configured to send the response data to the control system 302 for analysis according to the process 200.

[0051] The test channels 315 are configured to be located between the test head and the DIB to enable communication between the DUT and the test instruments. Although only four test channels are shown in Figure 3 it, any number of test channels can be included, such as one or more test channels per DUT. Figure 1 The communication channel 106 of can be or include one or more of the test channels 315.

[0052] The control system 302 is configured (e.g., programmed) to communicate with the test instruments 311a to 311n to direct and / or control the testing of the DUT. In some embodiments, the communication 320 link can be through a direct connection, such as a high-speed serial bus of the type described herein. In some embodiments, the communication link can be through a network. In some embodiments, the communication link can be considered part of one or more of the test channels. In some embodiments, the communication link can not be considered part of one or more of the test channels.

[0053] The control system 302 can be configured to provide test programs and / or commands to the test instruments 311a through 311n in the test head, and the test instruments use the test programs and / or commands to test the DUT. The control system 302 can be configured to receive response data from the test instruments and analyze the response data to determine whether the DUT has passed or failed the test. The control system 302 can also be configured to perform all or part of the Figure 2 operation process 200 described previously. In this regard, the control system 302 can include a power controller 325 that monitors and controls the power supplied to the test instruments via the power supply 310. The power controller 325 can be an Figure 1 embodiment of the power controller 110. In some embodiments, the process 200 can obtain response data containing bit errors and / or retry events from one or more of the test instruments via the link 320.

[0054] The memory 323 can store an event log 330, which can be an Figure 1 embodiment of the event log 108; and the memory 323 can store a power log 331, which can be an Figure 1 embodiment of the power log 114. The memory 323 also stores machine-executable instructions 334 (such as computer code in binary executable form) to implement all or part of the Figure 2 process 200. For example, the processing device 322 executes the instructions 322 alone (if the power controller 325 is a component thereof) or in combination with the power controller 325 (if the power controller is a separate hardware device) to implement all or part of the process 200. In embodiments where the process 200 is executed on the test instruments, the memory 323 and its contents can be included on the test instruments.

[0055] All or part of the test systems and processes described in this specification, as well as various modifications thereof, can be configured or controlled at least in part by one or more computers (such as the control system 302) using one or more computer programs tangibly embodied in one or more information carriers (such as in one or more non-transitory machine-readable storage media). The computer programs can be written in any form of programming language (including compiled languages or interpreted languages), and they can be deployed in any form (including as stand-alone programs or as modules, parts, subroutines, or other units suitable for use in a computing environment). The computer programs can be deployed to execute on one computer or multiple computers located at one site or distributed across multiple sites and interconnected by a network.

[0056] Acts associated with configuring or controlling the test systems and methods described herein can be performed by one or more programmable processors executing one or more computer programs to control or perform all or some of the operations described herein. All or part of the test systems and processes can be configured or controlled by dedicated logic circuitry, such as FPGAs (field programmable gate arrays) and / or ASICs (application specific integrated circuits), or embedded microprocessors localized to instrument hardware.

[0057] Processors suitable for executing computer programs include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only storage area or a random access storage area or both. Elements of a computer include one or more processors for executing instructions and one or more storage area devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to, one or more machine-readable storage media from which it will receive data or to which it will transfer data, or both, such as mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks. Machine-readable storage media suitable for embodying computer program instructions and data include all forms of non-volatile storage area, including, by way of example: semiconductor storage area devices, such as EPROMs (erasable programmable read only memories), EEPROMs (electrically erasable programmable read only memories), and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROMs (compact disk read only memories) and DVD-ROMs (digital versatile disk read only memories).

[0058] Elements of the different embodiments described can be combined to form other embodiments not specifically recited previously. Elements can be omitted from the systems previously described without generally having an adverse effect on their operation or the operation of the system. Additionally, the various individual elements can be combined into one or more independent elements to perform the functions described in this specification.

[0059] Other embodiments not specifically described in this specification are also within the scope of the claims.

Claims

1. A system for testing a device under test (DUT), the system comprising: One or more processing devices configured to receive first data from the DUT via a communication channel and analyze the first data to identify errors associated with the communication channel; And A power controller configured to receive second data based on a power perturbation from the DUT and compare the first data and the second data to determine whether there is a correlation between the power perturbation and the error.

2. The system according to claim 1, further comprising a power supply configured to supply power to the DUT, the power perturbation being based on the power supplied to the DUT.

3. The system according to claim 2, wherein The power supply is configured to operate at a voltage level that sets a margin around the nominal voltage of the DUT.

4. The system according to claim 2, wherein, The power controller is configured to manage the voltage level at the power supply to initiate the power perturbation.

5. The system according to claim 2, wherein, The power supply is configured to have a current limit that sets a margin around the maximum current consumption of the DUT.

6. The system according to claim 2, wherein The power controller is configured to manage the current level at the power supply to initiate the power perturbation.

7. The system according to claim 2, wherein, The one or more processing devices are configured to issue commands to the power controller to control the power supplied to the DUT by the power supply.

8. The system according to claim 2, wherein The power controller is configured to receive the second data from the power supply.

9. The system according to claim 8, wherein, The power controller is configured to timestamp the second data.

10. The system according to claim 9, wherein, The power controller is configured to send the timestamped second data to the one or more processing devices.

11. The system according to claim 1, wherein, The power controller is configured to store the second data in a memory.

12. The system according to claim 1, wherein The one or more processing devices are configured to store the first data in a memory.

13. The system according to claim 1, wherein The one or more processing devices are configured to timestamp the first data.

14. The system according to claim 13, wherein, The one or more processing devices are configured to send the timestamped first data to the power controller.

15. The system according to claim 1, wherein Errors from the communication channel include one or more bit errors.

16. The system according to claim 15, wherein, The one or more processing devices are configured to use a bit error test to test the one or more bit errors.

17. The system according to claim 1, wherein, The communication channel includes a Peripheral Component Interconnect Express (PCIe) bus or Ethernet.

18. The system according to claim 1, wherein, The power controller is configured to generate a timestamped predetermined power perturbation at the DUT, the power perturbation corresponding to the predetermined power perturbation, and the second data being based on the predetermined power perturbation.

19. The system according to claim 1, wherein The one or more processing devices are configured to control the ambient temperature around the DUT such that the ambient temperature changes from below freezing to above freezing but below the maximum operating temperature of the DUT.

20. The system according to claim 1, wherein The one or more processing devices are configured to control the bandwidth of the first data in order to detect a correlation between a power perturbation and an error in the communication channel based on the bandwidth of the first data.

21. A method for testing a device under test (DUT), the method comprising: Receiving first data from the DUT via a communication channel; Analyze the first data to identify an error associated with the communication channel; Receive second data based on a power perturbation from the DUT; and Compare the first data and the second data to determine whether there is a correlation between the power perturbation and the error.

22. The method according to claim 21, further comprising supplying power to the DUT using a power supply, the power perturbation being based on the power supplied to the DUT.

23. The method according to claim 22, wherein Supplying power to the DUT includes operating the power supply at a voltage level that sets a margin around the nominal voltage of the DUT.

24. The method according to claim 22, further comprising managing the voltage level at the power supply to initiate the power perturbation.

25. The method according to claim 22, wherein, The power supply is configured to have a current limit that sets a margin around the maximum current consumption of the DUT.

26. The method according to claim 22, further comprising managing the current level at the power supply to initiate the power perturbation.

27. The method according to claim 22, further comprising issuing a command to a power supply controller to control the power supplied by the power supply to the DUT.

28. The method according to claim 22, wherein Receiving the second data includes receiving the second data from the power supply.

29. The method according to claim 28, further comprising timestamping the second data.

30. The method according to claim 29, further comprising using the power supply controller to send the timestamped second data to the one or more processing devices.

31. The method according to claim 21, further comprising storing the second data in a memory using the power supply controller.

32. The method according to claim 21, further comprising storing the first data in a memory.

33. The method according to claim 21, further comprising timestamping the first data.

34. The method according to claim 33, further comprising sending the timestamped first data to the power supply controller.

35. The method according to claim 21, wherein, The error from the communication channel includes one or more bit errors.

36. The method according to claim 25, further comprising testing the one or more bit errors using a bit error test.

37. The method according to claim 21, wherein The communication channel includes a Peripheral Component Interconnect Express (PCIe) bus or Ethernet.

38. The method according to claim 21, further comprising generating a timestamped predetermined power perturbation at the DUT, the power perturbation corresponding to the predetermined power perturbation, and the second data being based on the predetermined power perturbation.

39. The method according to claim 21, further comprising controlling the ambient temperature around the DUT such that the ambient temperature changes from below freezing to above freezing but below the maximum operating temperature of the DUT.

40. The method according to claim 21, further comprising controlling a bandwidth of the first data, and wherein, Comparing includes detecting a correlation between the power perturbation and the error in the communication channel based on the bandwidth of the first data.

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