Frequency / phase lock detector for clock and data recovery circuits

Abstract

The invention relates to a frequency / phase lock detector for a clock and data recovery circuit. A circuit includes a phase and frequency detector circuit (102) to generate a first phase detection signal indicating whether a polarity of a first clock is the same as a polarity of a second clock when an edge of a data signal appears. The second clock is 90 degrees out of phase relative to the first clock. A lock detection circuit (137) determines, based on the first phase detection signal, that the third clock is one of a frequency and phase locked to the data signal, a frequency and quadrature locked to the data signal, and a non-frequency locked to the data signal.

Description

[0001] This application is a divisional application of a Chinese patent application with the application date of September 9, 2019, the title of "Frequency / Phase Locked Detector for Clock and Data Recovery Circuits", and the application number of 201980059955.5. Background Art

[0002] In a data communication system, data is sent from a transmitter to a receiver. At the receiver, the sent data is retrieved and consumed. Generally, the clock signal used by the transmitter to send data is not sent to the receiver. In such a system, the receiver uses the received data signal itself to recover the clock, and then uses the recovered clock to sample the received data signal to recover the data being sent. Summary of the Invention

[0003] In some embodiments, a circuit includes a phase and frequency detector circuit to generate a first phase detection signal that indicates whether the polarity of a first clock is the same as the polarity of a second clock when an edge of a data signal occurs. The second clock is out of phase with the first clock by 90 degrees. A lock detection circuit determines, based on the first phase detection signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal. Brief Description of the Drawings

[0004] For a detailed description of various examples, reference will now be made to the drawings, in which:

[0005] Figure 1 Illustrates a clock and data recovery circuit or at least a portion thereof according to one example.

[0006] Figure 2 Illustrates a phase and frequency detector that can be used in the Figure 1 clock and data recovery circuit.

[0007] Figure 3 and Figure 4 Illustrates an example of a phase detector that can be used in the Figure 3 phase and frequency detector.

[0008] Figure 5 Illustrates waveforms demonstrating frequency and phase lock that can be detected by the clock and data recovery circuit described herein.

[0009] Figure 6 Illustrates waveforms demonstrating frequency and quadrature phase lock that can be detected by the clock and data recovery circuit described herein.

[0010] Figure 7 Illustrates waveforms demonstrating a lack of frequency lock that can be detected by the clock and data recovery circuit described herein.

[0011] Figure 8 illustrates an example of a counter and related waveforms related to the frequency / phase lock detector of the clock and data recovery circuit of Figure 1

[0012] Figure 9 illustrates a flowchart for controlling the power state of the clock and data recovery circuit described herein based on the locked state of the circuit.

[0013] Figure 10 illustrates an example clock and data recovery circuit including a filter and a comparator.

[0014] Figure 11 illustrates an example of a full-rate clock and data recovery circuit.

[0015] Figure 12 illustrates waveforms related to the Figure 11 full-rate clock and data recovery circuit of

[0016] Figure 13 illustrates an example of a clock and data recovery circuit based on a Pottbacker frequency and phase detector.

[0017] Figure 14 illustrates a receiver in which any of the clock and data recovery circuits described herein can be used. Detailed Description

[0018] The examples described are directed to circuits that can be used to recover a clock based on a received data signal. The circuit is referred to as a clock and data recovery circuit (CDR), and the disclosed examples include circuits representing at least a portion of the CDR. The disclosed examples determine when the recovered clock has achieved phase and frequency lock to the data signal. In response to determining that phase lock and frequency lock have been achieved, the disclosed circuit disconnects power to at least a portion of the CDR, thereby saving power. In other possible embodiments, the disclosed circuit can also connect power to additional circuits (e.g., phase detectors) within the CDR to improve performance.

[0019] Figure 1 illustrates an example of CDR 100. Figure 1 ​The circuit in Figure 14 includes at least a portion of a CDR. An example CDR 100 includes a phase and frequency detector (PFD) 102, charge pumps (CP) 110 and 115, a loop filter 120, a voltage controlled oscillator (VCO) 130, a counter 140, a controller 150, a power gating circuit 160, and a power supply 170. The counter 140 and the controller 150 include or are at least a part of a lock detection circuit 137 that performs the functions attributed herein to the counter 140 and the controller 150. An input data signal (DATA_IN) is provided to the PFD 102. DATA_IN is a signal transmitted by a transmitter to a receiver including the CDR100. The VCO 130 (which can be other types of frequency tunable oscillators, such as a current controlled oscillator) generates a clock signal CLK_OUT. As explained below with respect to Figure 1 CLK_OUT is used to sample the state of DATA_IN to recover the data transmitted from the transmitter to the receiver. The PFD 102 includes a phase detector (PD) 103 and a frequency detector (FD) 104. In this example, the PFD 102 includes another PD 112 and may also include additional PDs. The FD 104 generates a control signal 105 to the CP 115, and the PD 103 generates a control signal 107 to the CP 110. Each charge pump 110, 115 includes a current source device (such as a transistor) that is controlled by a corresponding control signal to cause a variable amount of current to flow to the loop filter 120. Figure 1 Examples of

[0020] include two charge pumps, but other examples include a single charge pump. Further, Figure 1 The outputs of the two charge pumps 110 and 115 of

[0021] are connected together, but in other examples, the outputs of the charge pumps need not be connected together. The loop filter 120 filters the varying current from the CPs 110 and 115 and produces a voltage control input 129 to the VCO 130. Figure 1In the example, CLK_OUT generated by VCO 130 and other clocks having the same frequency as CLK_OUT are provided to PFD 102. In other examples, the frequency of the VCO output clock CLK_OUT is higher than the frequency of DATA_IN, and thus a frequency divider may be included in the clock feedback loop to divide the feedback clock 132.

[0022] In Figure 1 the example, loop filter 120 is a low-pass filter and includes resistor R and capacitors C1 and C2. The series combination of R and C1 forms a first low-pass filter, and C2 serves as a ripple filter to further reduce the ripple on the voltage control input 129 to the VCO.

[0023] Power supply 170 generates one or more voltages suitable for operating PFD 102, CPs 110, 115, counter 140, and controller 150. The power supply may include one or more direct current (DC)-DC converters. Power gating circuit 160 includes one or more power transistor switches (e.g., metal oxide semiconductor field effect transistors), which may be controlled by controller 150 to turn on and off the power to Figure 1 several of the components shown. For example, CP 115 and FD 104 of PFD 102 may be selectively turned on and off individually by power gating circuit 160, as specified by controller 150.

[0024] The PFD 102 generates a phase detection (PHASE DETECT) signal 109 indicating whether the polarity of the first clock of the multi-clock feedback clock 132 at the edge of DATA_IN is the same as the polarity of the second clock of the multi-clock feedback clock 132. The second clock is out of phase with the first clock by 90 degrees or 180 degrees. A counter 140 represents at least a portion of a lock detection circuit 137 that generates an output signal (COUNT) 141 processed by a controller 150. Based on the PHASE DETECT 109, the controller determines whether the third clock of the multi-clock feedback clock 132 is (a) frequency and phase locked to a midpoint between the edges of DATA_IN (referred to as "true" phase lock), (b) frequency and quadrature locked to DATA_IN, and (c) not frequency locked to DATA_IN. If frequency lock and / or phase lock (to the correct phase of DATA_IN) has been achieved, at least a portion of the PFD 102 can be powered down. The controller 150 asserts a control signal 151 to a power gating circuit 160 that disconnects power to the appropriate portions of the PFD 102 as described below. In some examples, the controller 150 is implemented as a finite state machine. In other examples, the controller 150 is implemented as a central processing unit (CPU) core that executes machine instructions (e.g., firmware). Additionally, the controller 150 and the power gating circuit 160 can be used in combination to enable power to additional blocks in the CDR. For example, as shown in the example of Figure 1 Each of the PDs 103, 112 in the PFD 102 can be optimized for different purposes. For example, the PD 103 can be optimized to achieve a fast initial lock, while the PD 112 can be optimized for jitter tolerance or some other performance metric. Once frequency and phase lock have been achieved, the PD 112 can be enabled while the PD 103 is disabled to provide a fast-lock CDR with superior performance in certain operating modes.

[0025] Figure 2 An example of the PFD 102 coupled to the CPs 110 and 115 and the counter 140 is shown. In this example, Figure 1 the PD 103 of includes PD 202 and PD 212. The PFD 102 also includes an FD circuit 220 (which represents the FD 104 of Figure 1 ). DATA_IN is provided to both the PD 202 and 212. The outputs of both the PD 202 and 212 are provided to the FD circuit 220. An example implementation of the FD circuit 220 is in Figure 13is shown and described below. The output of PD 202 is provided to and controls CP 110, and the output of FD circuit 220 is provided to and controls CP 115. The output of PD 212 includes PHASE DETECT 109 and is provided to counter 140.

[0026] As described above, feedback clock 132 includes multiple clocks CLKA-n. In Figure 2 the example of, clocks CLKA-n include four clocks CLK0, CLK45, CLK90, and CLK135. All four clocks have the same frequency but have a phase shift relative to each other. Relative to CLK0, CLK45 is offset by 45 degrees, CLK90 is offset by 90 degrees, and CLK135 is offset by 135 degrees. CLK0 and CLK90 are provided to PD 202, while CLK45 and CLK135 are provided to PD 212. Any suitable IQ filter and / or phase interpolator circuit can be used to generate the clocks.

[0027] Figure 3 An example of PD 202 is shown. In this example, PD 202 includes flip-flops 302 and 304 (e.g., D flip-flops) and logic gate 306. In this example, logic gate 306 is a NAND-XOR gate, but can be implemented as an XOR gate or other type of logic gate. Each flip-flop 302, 304 is clocked by DATA_IN. CLK0 is provided to the data input (D) of flip-flop 302, while CLK90 is provided to the D input of flip-flop 304. At the occurrence of an edge of DATA_IN, the state of the D input (CLK0) of flip-flop 302 is clocked through its Q output, and similarly, the state of the D input (CLK90) is clocked through its corresponding Q output. Thus, at the occurrence of a DATA_IN edge, the Q outputs represent the polar states of CLK0 and CLK90. The Q outputs are XORed together by XOR gate 306, and if the polarities of the Q outputs from flip-flops 302, 304 are different (one is 1 and the other is 0), then XOR gate 306 produces a logic 0 output, or if the polarities of the Q outputs are the same, then XOR gate 306 produces a logic 1 output. Flip-flops 302 and 304 can be clocked by one or both of the rising and falling edges of DATA_IN. Figure 3 the embodiment of as well as the Figure 4 and Figure 2 is a half-rate phase detector, which means that both edges of the recovered clock are used to sample the incoming data. In a half-rate phase detector (also see Figure 14 ), the clock signal has half the rate of DATA_IN. The DATA_IN data rate can be the symbol rate of the data.

[0028] In Figure 4The architecture of PD 212 in [reference] is the same as that of PD 202. However, as shown in the figure, the D inputs of flip - flops 402 and 404 receive CLK45 and CLK135. The output of the XNOR gate 406 indicates whether the polarities of CLK45 and CLK135 are the same or different when an edge of DATA_IN occurs.

[0029] With respect to Figures 5 - 7 the timing diagram, it illustrates the usefulness of the phase - shifted clocks CLK0, CLK45, CLK90, and CLK135 for detecting phase and frequency lock. Figure 5 It illustrates the case where CLK0 is frequency - and phase - locked to approximately the mid - point 500 (true phase lock) between the DATA_IN edges (e.g., edges 501 and 502), which is desirable for accurately sampling DATA_IN. A 90 - degree offset means that CLK90 is phase - aligned with the DATA_IN edge. The edges 510 and 512 of CLK45 and CLK135 are offset from the DATA_IN edge 502. The edge 510 of CLK45 leads the data edge 502, while the edge 512 of CLK135 lags the edge 502. At the edge of DATA_IN, the polarity of CLK45 is opposite to the polarity of CLK135. For example, with respect to edge 502, as shown in the figure, CLK45 is high while CLK135 is low.

[0030] At the edge of DATA_IN (e.g., edge 502), the flip - flops 402 and 404 of PD 212 will latch the states of CLK45 and CLK135, and the output of the XNOR gate 406 will be logic 0 because the polarities of CLK45 and CLK135 are opposite to each other. Thus, assuming frequency lock and assuming that CLK0 is locked to the mid - point 500, the output of PD 212 will always or at least mainly produce a signal (0 in the example of logic gate 406 being an XOR gate), which indicates that CLK45 and CLK135 have opposite polarities for each DATA_IN edge.

[0031] For PD 202, the output of the XNOR gate 306 is sometimes 0 and sometimes 1 because the edge of CLK90 is aligned with the edge of DATA_IN. In this way, depending on the amount of jitter present in CLK90, sometimes the flip - flop 304 will latch to 0 for CLK90 and sometimes to 1.

[0032] Figure 6 It illustrates the case where CLK0 is frequency - locked to DATA_IN but orthogonally phase - locked, which means that CLK0 is phase - locked to the edge 602 of DATA_IN instead of the mid - point 600. CLK45 and CLK135 have the same polarity at each edge 602 of DATA_IN, with respect to Figure 5The opposite polarities in the case of phase and frequency locking. In this way, the output of the NAND XOR gate 406 will always or mainly be logic 1. Additionally, since CLK0 is phase-aligned with the edge 602, the flip-flop 302 will latch 0 for CLK0 according to the jitter present in CLK0 and sometimes latch 1.

[0033] PD 202 cannot distinguish Figure 5 The illustrated frequency and phase locking conditions and Figure 6 The illustrated frequency and quadrature locking conditions. However, PD 212 can distinguish between these two conditions. The references in this text to frequency and phase locking (to the midpoint of DATA_IN) refer to determining that the polarities of CLK45 and CLK135 often (above a threshold) have opposite polarities when sampled by the edge of DATA_IN. Similarly, the references in this text to frequency and quadrature locking (or just quadrature locking) refer to determining that the polarities of CLK45 and CLK135 often (above a threshold) have the same polarities when sampled by the edge of DATA_IN.

[0034] Figure 7 Illustrates the case where CLK0 is not frequency-locked to DATA_IN. In this way, the edges of CLK0, CLK45, CLK90, and CLK135 occur at different times during each cycle of DATA_IN, as Figure 7 Indicated by the arrows in. The output of PD 202 is sometimes 0 and sometimes 1. Similarly, the output of PD 212 is sometimes 0 and sometimes 1.

[0035] For Figure 5 The frequency and phase locking of, PD 212 will always or mainly produce a signal of a specific polarity (e.g., 0). For Figure 6 The frequency and quadrature locking of, PD 212 will also always or mainly produce a signal with a specific but different polarity (e.g., 1) compared to Figure 5 . For the case of no frequency locking, PD 212 will produce logic 1 about half the time and logic 0 about half the time. In this way, the output of PD 212 can be used to detect Figures 5 - 7 The three conditions illustrated. If frequency and true phase locking (to the midpoint of DATA_IN) are detected, the controller 150 will cause the power of the FD circuit 220 and PD 212 to be disabled because these circuits are no longer needed. If frequency and quadrature locking are detected, the controller 150 is configured to disable the power to the FD circuit 220, but maintain the power supply to PD 212 and the reset counter 140 (discussed below) to allow the circuit to continue detecting true phase locking. If no frequency locking is detected, the power supply to the FD circuit and PD 212 is maintained.

[0036] Figure 8 An example of an implementation of counter 140 is shown. In this example, counter 140 includes multiplexer 802 and flip-flops 804, 806, 808, and 810 (e.g., D flip-flops). The Q output of flip-flop 804 is provided back to the first input 147 (labeled "0") and the second input of multiplexer 802. Multiplexer input 142 (labeled "1") is an inverted input that inverts the signal from the Q output of flip-flop 804. Multiplexer input 147 is not inverted. Control input 143 receives PHASE DETECT 109 generated by PD 212 to control which of the Q output of flip-flop 804 or the inversion of the Q output is provided as the output from multiplexer 802 to the D input of flip-flop 804. Flip-flop 804 is clocked by CLK0 (but can be any of CLK0, CLK45, CLK90, or CLK135).

[0037] Whenever PHASE DETECT 109 is high during the rising edge of CLK0, the Q output of flip-flop 804 (labeled signal "X") toggles. Thus, whenever CLK0 samples PHASE DETECT 109 as high, X toggles. As described above, PHASE DETECT 109 being high means that CLK45 and CLK135 have the same polarity ( Figure 6 ), and PHASE DETECT 109 being high for an extended period of time indicates that CLK0 is in a frequency-locked state but is quadrature-locked with respect to DATA_IN. Whenever CLK0 samples PHASE DETECT 109 as low, X does not toggle. As described above, PHASE DETECT 109 being low means that CLK45 and CLK135 have opposite polarities ( Figure 5 ), and PHASE DETECT 109 being low for an extended period of time indicates that CLK0 is frequency and phase-locked with respect to the midpoint of DATA_IN. If frequency locking is not achieved ( Figure 7 ), then the signal X toggles less frequently than when frequency and quadrature locking are achieved, but more frequently than when frequency and phase locking (to the midpoint of DATA_IN) are achieved. The combination of multiplexer 802 and flip-flop 804 is a toggle flip-flop.

[0038] Flip-flops 806, 808, and 810 are configured as ripple counters. The X signal from flip-flop 804 is used to clock flip-flop 806. The Q output of flip-flop 806 (signal "Y") is used to clock flip-flop 808, and the Q output of flip-flop 808 (signal "Z") is used to clock flip-flop 810. The Q output of flip-flop 810 is COUNT signal 141. AlthoughFigure 8 Three flip - flop ripple counters are shown, but any number of flip - flops can be used to implement a ripple counter. As shown, the D inputs to flip - flops 806, 808, and 810 are inverted, and the Q output of each flip - flop is provided back to its corresponding inverted D input. In Figure 8 illustrative waveforms of CLK0, PHASE DETECT 109, X, Y, Z, and COUNT are shown. Y changes state (switches) on the rising edge of X. Similarly, Z switches each state on the rising edge of Y, and COUNT 141 switches each state on the rising edge of Z. Thus COUNT 141 indicates the frequency at which PHASE DETECT 109 is high or low on the rising edge of CLK0. In Figure 1 the example of, COUNT 141 is provided to controller 150, which asynchronously counts the rising or falling edges of COUNT 141 over a fixed time period and then compares the resulting count value to a pair of threshold values, as Figure 9 shown.

[0039] Figure 9 includes flowchart 900 that illustrates the operation of CDR 100. At 902, CDR 100 is enabled (e.g., powered on). At 904, controller 150 reads the count value (CNT). In some embodiments, controller 150 receives the COUNT signal 141 from counter 140 and counts the number of edges of COUNT (e.g., number of rising edges, number of falling edges, or number of rising and falling edges) to generate CNT, stores it in a register or memory, and then reads it back. At 906, the controller determines whether CNT is less than the lower threshold (lo_thresh). If CNT is less than lo_thresh (indicating frequency and phase lock (to the mid - point of DATA_IN)), then at 908, controller 150 asserts a signal to power - gate circuit 160 ( Figure 1 ) to disable the power supply to FD circuit 220 and the power supply to PD 212.

[0040] If CNT is not less than lo_thresh, then at 910 controller 150 determines whether CNT is greater than the higher threshold (hi_thresh), which would indicate frequency lock and quadrature lock. If CNT does exceed hi_thresh, then at 912, controller 150 asserts a signal to power - gate circuit 160 to disable only FD circuit 220. Counter 140 then resets at 914 (e.g., by sending a Figure 8The reset input of each flip-flop in ) asserts a signal). Additionally, if CNT is not greater than hi_thresh (meaning CNT is between lo_hresh and hi_thresh), then frequency lock is not achieved, and at 914 the counter is reset and the process continues.

[0041] Figure 10 An example implementation of CDR 1000 is shown, which includes filter 1010 and comparators 1020 and 1025 instead of a counter (e.g., counter 140). Filter 1010 and comparators 1020, 1025 include another example of lock detection circuit 1037. Controller 150 can also be part of lock detection circuit 1037. Filter 1010 includes resistor R1 coupled to capacitor C1. Filter 1010 is a low-pass filter that low-pass filters PHASE DETECT 109 to recover the direct current (DC) component of PHASE DETECT as filter output signal 1015 (FILTER_OUT). FILTER_OUT 1015 is provided to the positive input (+) of comparator 1020 and the negative input (-) of comparator 1025. The negative input of comparator 1020 is coupled to upper threshold voltage (V_HI), and the positive input of comparator 1025 is coupled to lower threshold voltage (V_LO).

[0042] The magnitude of FILTER_OUT is a function of how long PHASE DETECT 109 is high versus low. Comparators 1020 and 1025 along with threshold voltages V_HI and V_LO establish three regions relative to V_HI and V_LO. If PHASE DETECT 109 is greater than V_HI (indicating frequency and quadrature lock), then the output of comparator 1020 (D_OUT_HI) will be logic high, while the output of comparator 1025 (D_OUT_HI) will be logic low. If PHASE DETECT 109 is between V_HI and V_LO (indicating no frequency lock), then both D_OUT_HI and D_OUT_LO are logic low. If PHASE DETECT 109 is less than V_LO (indicating frequency and phase locked to the midpoint of DATA_IN), then D_OUT_HI will be logic low and D_OUT_LO will be logic high. Controller 150 receives D_OUT_HI and D_OUT_LO and responds to the states of these signals to modify the power state of CDR 100 as described previously.

[0043] Figure 11An embodiment of a full-rate CDR 1100 is shown. The full-rate CDR 1100 uses a clock signal whose frequency is equal to the data rate of DATA_IN, and samples DATA_IN using only the rising edge of the recovered clock. In this example, PD 1102 receives CLK0 and PD 1112 receives CLK90. The output signal 1109 from PD 1112 is provided to counter 140 (or a filter and comparator as in Figure 10 ). Figure 12 An example of data and clock waveforms for frequency and phase locking is shown.

[0044] When PD 1112 always or mainly produces a 1, frequency and true phase lock (to the midpoint of DATA_IN) is detected because CLK90 is 1 at the edge of DATA_IN during true phase lock. When PD 1112 always or mainly produces a 0, frequency and quadrature phase lock is detected because CLK90 is 0 at the edge of DATA_IN during quadrature lock. When not in a frequency-locked state, PD 1112 produces a 1 approximately half the time and a 0 approximately half the time. PD 1102 in Figure 11 can be implemented as a single flip-flop. PD 1102 supplies CLK0 to the D input and uses DATA_IN to clock the flip-flop. Similarly, PD 1112 can be implemented as a single flip-flop. PD 1112 supplies CLK90 to the D input and uses DATA_IN to clock the flip-flop.

[0045] Figure 13 An implementation of a phase and frequency detector 1300 is shown. Figure 13The phase and frequency detector 1300 is based on the architecture of a rotational phase and frequency detector. The phase and frequency detector 1300 includes flip - flops 1302, 1304, 1306, 1308, 1314, 1316, latches 1320 and 1322, exclusive - OR gates 1310 and 1312, and AND gates 1324 and 1326. DATA_IN is used to clock flip - flops 1302 - 1308, 1314, and 1316. The combination of flip - flops 1302, 1302, and 1314 and XOR gate 1310 includes PD202. The combination of flip - flops 1306, 1308, and 1316, XOR gate 1312, and inverter 1318 includes PD 212. The combination of flip - flops 1320 and 1322 and AND gates 1324 and 1326 includes the FD circuit 220. CLK0 is provided to the D input of flip - flop 1302. CLK90 is provided to the D input of flip - flop 1304. CLK45 is provided to the D input of flip - flop 1306. CLK135 is provided to the D input of flip - flop 1308. The Q outputs of flip - flops 1302 and 1304 are XORed together by exclusive - OR gate 1310. The Q outputs of flip - flops 1306 and 1308 are XORed together by exclusive - OR gate 1312. Flip - flop 1314 latches the output of exclusive - OR gate 1310 to its Q output. Flip - flop 1316 latches the output of exclusive - OR gate 1312 to its Q output. The outputs of the two flip - flops 1314 and 1316 (and the output of flip - flop 1316 through inverter 1318) are provided to the FD circuit 220 to generate the frequency detector output control signal 105. In this example, the control signal 105 includes an up (UP) signal and a down (DN) signal that are provided to the charge pump 115. The output signal 1331 from flip - flop 1314 is the output of PD 202 and is provided to the charge pump 110. The output signal 1309 from PD 212 is provided to the counter 140 (or a filter and comparator as in Figure 10 ). In some embodiments, DATA_IN may be encoded according to non - return - to - zero (NRZ) coding or according to pulse amplitude modulation 4 (PAM4) coding. For PAM4 data, in some embodiments, the received data to the receiver is passed through a limiting amplifier before being provided to the PFD 102 to convert the PMA4 data to NRZ - like data. For example, assuming the PAM4 data has four levels of + 3V, + 1V, - 1V, and - 3V, the limiting amplifier will output 1 for the + 3V and + 1V levels and 0 for the - 1V and - 3V levels, i.e., the limiting amplifier acts as a non - clocked comparator with a threshold of 0V.

[0046] Figure 14An example of at least a portion of a receiver 1400 is shown. The receiver 1400 includes an equalizer 1402, a sampler 1410, a CDR 1420, a controller 1450, and a power gating circuit 1460. The CDR 1420, the controller 1450, and the power gating circuit 1460 may be implemented using, for example, any of the embodiments described herein. In some embodiments, the equalizer 1402 includes a linear equalizer to process a received data signal 1401 using a linear filter. The CDR 1420 also receives the received data signal 1401 (referred to as DATA_IN as used above) and generates a CLK_OUT signal to the sampler 1410. The CLK_OUT signal is a clock signal recovered based on the received data signal 1401. The CLK_OUT generated by the CDR 1420 is used to sample the output of the equalizer to produce a data output (DATA_OUT) signal 1470 for consumption by other components in the receiver 1400 or other components coupled to the receiver 1400. As previously explained under the control of the controller 1450, the power gating circuit 1460 disables power to certain components and enables power to certain other components to the CDR 1420.

[0047] In this specification, the term "coupled" means a direct or indirect wired or wireless connection. Thus, if a first device is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The phrase "based on" means "at least in part based on". Thus, if X is based on Y, X may be a function of Y and many other factors.

[0048] Within the scope of the claims, modifications may be made in the described embodiments, and so may in other embodiments.

Claims

1. A circuit, comprising: A first phase detector circuit that generates a first phase detection signal indicating whether a first clock is early or late relative to a data signal; A second phase detector circuit that generates a second phase detection signal indicating whether a second clock is early or late relative to the data signal, the second clock being out of phase with the first clock by 90 degrees; And A counter that counts the second phase detection signal to generate a count value.

2. The circuit according to claim 1, further comprising a power gating circuit to disable power to the second phase detector circuit.

3. The circuit according to claim 2, further comprising a frequency detector, and the power gating circuit is configured to disable power to the frequency detector based on the second phase detection signal.

4. The circuit according to claim 3, wherein, The power gating circuit disables power to the frequency detector and the second phase detector circuit based on the second phase detection signal.

5. The circuit according to claim 1, wherein The counter includes a trigger counter coupled to a ripple counter.

6. A circuit, comprising: A first phase detector circuit that generates a first phase detection signal indicating whether the polarity of a first clock is the same as the polarity of a second clock when an edge of a data signal occurs, the second clock being out of phase with the first clock by 90 degrees; A second phase detector circuit that generates a second phase detection signal indicating whether the polarity of a third clock is the same as the polarity of a fourth clock when an edge of the data signal occurs, the third clock being out of phase with the fourth clock by 90 degrees; A filter that filters the second phase detection signal to generate a filter signal; And A comparator that compares the filter signal with a threshold.

7. The circuit according to claim 6, further comprising a controller and a power gating circuit, the controller being coupled to receive an output of the comparator to assert a signal to the power gating circuit to disable power to one of the first phase detector circuit or the second phase detector circuit based on the output from the comparator.

8. The circuit according to claim 7, further comprising a frequency detector and the controller to assert a signal to the power gating circuit to disable power to the frequency detector based on the output from the comparator.

9. The circuit according to claim 6, wherein, The comparator includes a first comparator and a second comparator, the first comparator being coupled to receive a first threshold voltage and the filter signal, and the second comparator being coupled to receive a second threshold voltage and the filter signal.

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