A signal processing method, device, apparatus, storage medium and chip

Abstract

The present disclosure provides a signal processing method, comprising: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal; determining a second phase shift angle of the first signal; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle; and compensating a DC offset of a transmitting path and / or a feedback path based on the first DC offset coefficient and the second DC offset coefficient. The method of the present disclosure determines the first DC offset coefficient and the second DC offset coefficient in the loop under two different phase shift angles, and then obtains the compensation coefficient of the transmitting path and / or the feedback path, so that the DC offset compensation of the transmitting path and / or the feedback path can be realized in real time under the working condition of the first signal, the application range of the signal processing method is expanded, and the convenience of the DC offset compensation is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of signal calibration, and particularly relates to a signal processing method and device, equipment, storage medium and chip. BACKGROUND

[0002] In a signal processing system, DC offset is a common problem mainly caused by local oscillator leakage and circuit interference. The DC offset can cause the average level of the signal to be no longer zero, and further cause the performance of the system to decrease, for example, causing decision errors, increasing the bit error rate, etc. In addition, the DC offset can also cause the error of the device to increase, thereby reducing the accuracy and reliability thereof. Therefore, how to effectively eliminate or compensate the DC offset of the signal has become a problem to be solved. SUMMARY

[0003] The present disclosure provides a signal processing method, device, equipment, storage medium and chip to realize real-time compensation for the DC offset of a transmit path and / or a feedback path.

[0004] In a first aspect of the present disclosure, a signal processing method is provided. The method comprises: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmit path and a feedback path at the first phase shift angle, the transmit path being configured to transmit the first signal, and the feedback path being configured to transmit a feedback signal of the first signal; determining a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising the transmit path and the feedback path at the second phase shift angle; and performing DC offset compensation on the transmit path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0005] In some embodiments, determining the first DC offset coefficient of the first loop based on the first signal and the first phase shift angle of the first signal comprises: determining a second signal based on the first signal and the first phase shift angle, the second signal being a feedback signal of the first signal at the first phase shift angle; and determining the first DC offset coefficient of the first loop based on the first signal and the second signal.

[0006] In some embodiments, determining the second DC offset coefficient of the second loop based on the first signal and the second phase shift angle comprises: determining a third signal based on the first signal and the second phase shift angle, the third signal being a feedback signal of the first signal at the second phase shift angle; and determining the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0007] In some embodiments, determining the second DC offset coefficient of the second loop based on the first signal and the second phase shift angle comprises: determining a third signal based on the first signal and the second phase shift angle, the third signal being a feedback signal of the first signal at the second phase shift angle; determining the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0008] In some embodiments, the method further comprises: determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, the third compensation coefficient being used for calibrating the compensation transmit path, and the fourth compensation coefficient being used for calibrating the compensation feedback path; performing DC offset compensation on the compensation transmit path based on the third compensation coefficient; and performing DC offset compensation on the compensation feedback path based on the fourth compensation coefficient.

[0009] In some embodiments, the method further comprises: determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, the third compensation coefficient being used for calibrating the compensation transmit path, and the fourth compensation coefficient being used for calibrating the compensation feedback path; performing DC offset compensation on the compensation transmit path based on the third compensation coefficient; and performing DC offset compensation on the compensation feedback path based on the fourth compensation coefficient.

[0010] A second aspect embodiment of the present disclosure provides a signal processing apparatus, comprising: a first processing unit configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmit path and a feedback path at the first phase shift angle, the transmit path being configured to transmit the first signal, and the feedback path being configured to transmit a feedback signal of the first signal; a second processing unit configured to determine a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; a third processing unit configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising the transmit path and the feedback path at the second phase shift angle; and a fourth processing unit configured to perform DC offset compensation on the transmit path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0011] A third aspect embodiment of the present disclosure provides a communication device, comprising a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program stored in the memory to enable the device to perform the method of the first aspect.

[0012] A fourth aspect embodiment of the present disclosure provides a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are configured to enable a computer to perform the method of the first aspect.

[0013] A fifth aspect of the present disclosure provides a chip, comprising at least one processor and a communication interface; the communication interface is used to receive a signal input into the chip or output a signal from the chip, and the processor is in communication with the communication interface and implements the method described in the first aspect of the present disclosure through a logic circuit or an execution code instruction.

[0014] In summary, the signal processing method according to the present disclosure comprises: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmission path and a feedback path at the first phase shift angle, the transmission path being used for transmitting the first signal, and the feedback path being used for transmitting a feedback signal of the first signal; determining a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising a transmission path and a feedback path at the second phase shift angle; and performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient. The method of the present disclosure determines the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, and then obtains the compensation coefficient of the transmission path and / or the feedback path, so that the DC offset compensation of the transmission path and / or the feedback path can be performed in real time under the working condition of the first signal, the application range of the signal processing method is expanded, and the convenience of DC offset compensation is improved.

[0015] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure, and do not constitute an improper limitation on the present disclosure.

[0017] Figure 1 An application scenario diagram of a signal processing method provided by an embodiment of the present disclosure;

[0018] Figure 2 A flowchart of a signal processing method provided by an embodiment of the present disclosure;

[0019] Figure 3 A flowchart of another signal processing method provided by an embodiment of the present disclosure;

[0020] Figure 4 A flowchart of another signal processing method provided by an embodiment of the present disclosure;

[0021] Figure 5A structural schematic diagram of a signal processing device provided by an embodiment of the present disclosure is shown in FIG. 1.

[0022] Figure 6 A structural schematic diagram of a communication device provided by an embodiment of the present disclosure is shown in FIG. 2.

[0023] Figure 7 A structural schematic diagram of a chip provided by an embodiment of the present disclosure is shown in FIG. 3. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, unless otherwise indicated, like numbers in the attached drawings refer to the same or similar elements. The embodiments described in the following exemplary embodiments are not meant to represent all embodiments consistent with an embodiment of the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of an embodiment of the present disclosure as detailed in the appended claims.

[0025] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of an embodiment of the present disclosure. As used in the present disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0026] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or hierarchy among the information. These terms are used only to distinguish one from another. For example, a first information can be termed a second information, and, similarly, a second information can be termed a first information, without departing from the scope of an embodiment of the present disclosure. Depending on the context, the word "if' and "when' as used herein can be interpreted to mean "upon determining" or "in response to determining."

[0027] To facilitate understanding, background art related to the present application is introduced first.

[0028] In a signal processing system, DC offset is a common problem, which is mainly caused by LO leakage, circuit interference. DC offset will cause the average level of the signal to be no longer zero, and further cause the performance of the system to decline, for example, causing decision errors, increasing the bit error rate, etc. In addition, DC offset will also cause the error of the device to increase, thereby reducing its accuracy and reliability. Therefore, how to effectively eliminate or compensate the DC offset of the signal has become a problem to be solved.

[0029] For a single transmitter or receiver, the DC offset elimination or compensation scheme mainly includes hardware calibration, software calibration and filtering methods. However, in an actual chip digital front end, in order to ensure the signal transmission quality, a feedback channel is usually borrowed to calibrate the transmission link. However, the transmitter (TX) and the feedback receive (FbRX) usually use the same local oscillator, which will cause the DC offsets of the TX and the FbRX to be located at the same frequency point and cannot be decoupled.

[0030] Under the same local oscillator, it is a challenging task to separate the TX and the FbRX, because for the feedback receive channel, only the overall DC offset influence of the TX and the FbRX can be perceived. For this problem, the industry has tried various solutions. One solution is to first independently calibrate the DC offset on the feedback channel, and then calibrate the DC offset of the entire TX and FbRX channel, and then the second obtained calibration coefficient is considered as the DC offset of the TX channel. However, this method needs to close the service signal when calibrating, and cannot achieve real-time calibration under the service flow.

[0031] Before introducing the detailed scheme of the present disclosure, the scene to which the scheme of the present disclosure is applied is described.

[0032] The application scene of a signal processing method is, for example Figure 1 As shown in the figure, the data represent service signals, which are composed of a digital-to-analog converter (DAC) on the upper side, Figure 1 a IQ modulator on the lower side, a feedback channel composed of an analog-to-digital converter (ADC) on the upper side, Figure 1 a IQ demodulator on the lower side, wherein the phase shifter is used to phase shift the IQ modulated signal to calculate the TX coefficient and the FB coefficient, and the power amplifier (PA) is used to convert the service signal into a radio frequency signal for transmission in the radio frequency channel.

[0033] It can be understood that the description of the embodiments of the present disclosure is to more clearly illustrate the technical solutions of the embodiments of the present disclosure, and does not constitute a limitation on the signal processing method, device, equipment, storage medium and chip proposed by the embodiments of the present disclosure. It can be known by those skilled in the art that with the evolution of system architecture and the appearance of new business scenarios, the technical solutions proposed by the embodiments of the present disclosure are also applicable to similar technical problems.

[0034] Figure 2 A flowchart of a signal processing method provided by the embodiments of the present disclosure is shown in FIG. 1. Figure 2As shown, the signal processing method comprises steps 201-204.

[0035] In step 201, a first DC offset coefficient of a first loop is determined based on a first signal and a first phase shift angle of the first signal.

[0036] In some embodiments, a feedback signal of the first signal at the first phase shift angle can be determined based on the first signal and the first phase shift angle of the first signal, and then the first DC offset coefficient of the first loop is determined based on the first signal and the feedback signal at the first phase shift angle.

[0037] In some embodiments, the first loop comprises a transmission path and a feedback path at the first phase shift angle, for example Figure 1 As shown, when the phase shift angle of the phase shifter is the first phase shift angle, the loop formed by the transmission path comprising the DAC and the upper side IQ modulator and the feedback path comprising the lower side IQ demodulator and the ADC is the first loop.

[0038] In some embodiments, the transmission path is configured to transmit the first signal, and the feedback path is configured to transmit a feedback signal of the first signal.

[0039] In some embodiments, the first signal can be a service signal transmitted by a transmission source, for example Figure 1 As shown, the signal output by the upper side IQ modulator.

[0040] In some embodiments, the specific angle value of the first phase shift angle is not limited, which can be the phase shift angle after the phase shifter is initialized, or can be a preset phase shift angle.

[0041] In some embodiments, the first phase shift angle can be determined by setting the phase shift angle of the phase shifter, but is not limited thereto, and the first phase shift angle can also be determined by other phase shift methods.

[0042] In some embodiments, the first DC offset coefficient is a coefficient of the overall DC offset of the first loop, that is, the first DC offset coefficient is a DC offset coefficient of the overall DC offset of the first loop formed by the DC offset of the transmission path and the DC offset of the feedback path at the first phase shift angle.

[0043] In step 202, a second phase shift angle of the first signal is determined.

[0044] In some embodiments, the second phase shift angle can be determined by setting the phase shift angle of the phase shifter, but is not limited thereto, and the second phase shift angle can also be determined by other phase shift methods.

[0045] In some embodiments, the second phase shift angle should satisfy a first preset condition, and the disclosure does not limit the specific content of the first preset condition, which is, for example, that the second phase shift angle should be at least 1° larger than the first phase shift angle and at most 179° larger than the first phase shift angle, for example: the second phase shift angle is different from the first phase shift angle.

[0046] In step 203, a second DC offset coefficient of the second loop is determined based on the first signal and the second phase shift angle.

[0047] In some embodiments, the feedback signal of the first signal at the second phase shift angle can be determined based on the first signal and the second phase shift angle, and then the second DC offset coefficient of the second loop is determined based on the first signal and the feedback signal at the second phase shift angle.

[0048] In some embodiments, the second loop includes a transmission path and a feedback path at the second phase shift angle, for example Figure 1 As shown, when the phase shift angle of the phase shifter is the second phase shift angle, the loop formed by the transmission path composed of the DAC and the upper side IQ modulator and the feedback path formed by the lower side IQ demodulator and the ADC is the second loop.

[0049] In some embodiments, the second DC offset coefficient is a coefficient related to the overall DC offset of the second loop, that is, the second DC offset coefficient is a DC offset coefficient of the overall DC offset of the second loop composed of the DC offset of the transmission path and the DC offset of the feedback path at the second phase shift angle.

[0050] In step 204, the DC offset compensation is performed on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0051] In some embodiments, the DC offset conditions of the transmission path and the feedback path can be determined based on the first DC offset coefficient and the second DC offset coefficient, and then the DC offset compensation is performed on the transmission path and / or the feedback path through the DC offset conditions of the transmission path and the feedback path, so as to realize the real-time DC offset compensation of the transmission path and / or the feedback path.

[0052] In summary, the signal processing method proposed in this disclosure includes: determining a first DC offset coefficient for a first loop based on a first signal and a first phase shift angle of the first signal, wherein the first loop includes a transmission path and a feedback path at the first phase shift angle, the transmission path being used to transmit the first signal and the feedback path being used to transmit a feedback signal of the first signal; determining a second phase shift angle of the first signal, wherein the second phase shift angle satisfies a first preset condition; determining a second DC offset coefficient for a second loop based on the first signal and the second phase shift angle, wherein the second loop includes a transmission path and a feedback path at the second phase shift angle; and performing DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient. This method, by determining the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, thereby obtaining the compensation coefficients for the transmission path and / or the feedback path, enables real-time DC offset compensation for the transmission path and / or the feedback path when the first signal is operating, expanding the applicability of the signal processing method and improving the convenience of DC offset compensation.

[0053] Figure 3 This is a schematic flowchart of a signal processing method proposed in an embodiment of this disclosure, as shown below. Figure 3 As shown, in Figure 2 Based on the illustrated embodiment, for Figure 2 Further explanation includes steps 301-307.

[0054] Step 301: Determine the second signal based on the first signal and the first phase shift angle.

[0055] In some embodiments, the second signal is a feedback signal of the first signal at the first phase shift angle. For example... Figure 1 As shown, the second signal can be the signal output by the ADC when the phase shift angle of the phase shifter is the first phase shift angle.

[0056] In some embodiments, the first signal can be phase-shifted based on a first phase-shift angle, and the phase-shifted first signal can be subjected to IQ modulation and analog-to-digital conversion to determine the signal output by the ADC as the second signal. It should be understood that the second signal has the same signal length as the first signal.

[0057] Step 302: Determine the first DC offset coefficient of the first loop based on the first signal and the second signal.

[0058] In some embodiments, before determining the first DC offset coefficient, the first signal and the second signal also need to be time delay aligned to reduce the error of the first DC offset coefficient. The manner of time delay alignment is not limited in the disclosure, for example, time delay alignment of the first signal and the second signal is performed by fourth-order delay spectrum estimation; for example, time delay alignment of the first signal and the second signal is performed by calculating the second-order conjugate complex correlation of the first signal and the second signal, etc.

[0059] In some embodiments, the first DC offset coefficient of the first loop can be determined by the following formula:

[0060]

[0061] Wherein, dc1 represents the first DC offset coefficient, N represents the signal length of the first signal, x(t) represents the first signal, and fb1(t) represents the second signal.

[0062] Step 303, determining a third signal based on the first signal and the second phase shift angle.

[0063] In some embodiments, the third signal is a feedback signal of the first signal at the second phase shift angle. For example Figure 1 As shown, the third signal can be the signal output by the ADC when the phase shift angle of the phase shifter is the second phase shift angle.

[0064] In some embodiments, the first signal can be phase shifted based on the second phase shift angle, and the phase-shifted first signal can be IQ modulated and analog-to-digital converted to determine the signal output by the ADC as the third signal. It should be understood that the third signal has the same signal length as the first signal.

[0065] Step 304, determining a second DC offset coefficient of a second loop based on the first signal and the third signal.

[0066] In some embodiments, before determining the second DC offset coefficient, the first signal and the third signal also need to be time delay aligned to reduce the error of the second DC offset coefficient. The manner of time delay alignment is not limited in the disclosure, for example, time delay alignment of the first signal and the second signal is performed by fourth-order delay spectrum estimation; for example, time delay alignment of the first signal and the second signal is performed by calculating the second-order conjugate complex correlation of the first signal and the second signal, etc.

[0067] In some embodiments, the second DC offset coefficient of the second loop can be determined by the following formula:

[0068]

[0069] Wherein, dc2 represents the second DC offset coefficient, N represents the signal length of the first signal, x(t) represents the first signal, and fb2(t) represents the third signal.

[0070] Step 305, determining the loop gain of the first loop and the loop gain of the second loop.

[0071] In some embodiments, the method for determining the loop gain of the first loop and the loop gain of the second loop is not limited, such as voltage injection method, current injection method, etc.

[0072] Step 306, based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop and the loop gain of the second loop, determining the first compensation coefficient of the transmission path and / or the second compensation coefficient of the feedback path.

[0073] In some embodiments, the first compensation coefficient of the transmission path and / or the second compensation coefficient of the feedback path can be determined by the following formula:

[0074]

[0075] Wherein, g1 represents the loop gain of the first loop, g2 represents the loop gain of the second loop, d tx represents the first compensation coefficient of the transmission path, d fb represents the second compensation coefficient of the feedback path, dc1 represents the first DC offset coefficient, and dc2 represents the second DC offset coefficient.

[0076] Further, by solving the equation shown in formula 2, the first compensation coefficient and / or the second compensation coefficient can be determined,

[0077] Wherein, the solution is as follows:

[0078]

[0079] Step 307, based on the first compensation coefficient, performing DC offset compensation on the transmission path to obtain a compensated transmission path; and / or based on the second compensation coefficient, performing DC offset compensation on the feedback path to obtain a compensated feedback path.

[0080] In some embodiments, the first compensation coefficient can be used to perform DC offset compensation on the transmission path to obtain a compensated transmission path, so as to realize the DC offset compensation on the transmission path.

[0081] For example Figure 1 As shown, the first DC offset coefficient d tx is input into the TX DC offset compensation module, so as to realize the DC offset compensation on the transmission path, wherein the TX DC offset compensation module and the transmission path constitute a compensated transmission path.

[0082] In some embodiments, the DC offset compensation of the feedback path can be achieved by inputting the second DC offset coefficient d

[0083] For example Figure 1 The second DC offset coefficient d fb is input into the FB DC offset compensation module, thereby achieving the DC offset compensation of the feedback path, wherein the FB DC offset compensation module and the transmission path constitute a compensated transmission path.

[0084] In some embodiments, the DC offset compensation of the transmission path and / or the feedback path can be achieved by the following formula:

[0085] sig out = sig in -dc (Formula 5)

[0086] Wherein, sig out represents the output signal of the TX DC offset compensation module or the FB DC offset compensation module, sig in represents the input signal of the TX DC offset compensation module, and dc represents the first compensation coefficient or the second compensation coefficient. For example, when the DC offset compensation of the transmission path is performed, sig out represents the output signal of the TX DC offset compensation module, sig in represents the input signal of the FB DC offset compensation module, and dc represents the first compensation coefficient, i.e. dc is equivalent to d tx calculated by Formula 4. For example, when the DC offset compensation of the feedback path is performed, sig out represents the output signal of the FB DC offset compensation module, sig in represents the input signal of the FB DC offset compensation module, and dc represents the second compensation coefficient, i.e. dc is equivalent to d fb calculated by Formula 4.

[0087] In summary, the signal processing method according to the present disclosure comprises: determining a second signal based on a first signal and a first phase shift angle, the second signal being a feedback signal of the first signal at the first phase shift angle; determining a first DC offset coefficient of a first loop based on the first signal and the second signal; determining a third signal based on the first signal and a second phase shift angle, the third signal being a feedback signal of the first signal at the second phase shift angle; determining a second DC offset coefficient of a second loop based on the first signal and the third signal; determining a loop gain of the first loop and a loop gain of the second loop; determining a first compensation coefficient of a transmit path and / or a second compensation coefficient of a feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop and the loop gain of the second loop; performing DC offset compensation on the transmit path based on the first compensation coefficient to obtain a compensated transmit path; and / or performing DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path. The method of the present disclosure sets two different phase shift angles to determine the first DC offset coefficient and the second DC offset coefficient in the loop at the two different phase shift angles, and obtains the loop gain of the first loop and the loop gain of the second loop, and uses the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop and the loop gain of the second loop to establish an equation, and determines the solution of the equation as the first compensation coefficient of the transmit path and / or the second compensation coefficient of the feedback path, so as to realize DC offset compensation on the transmit path and / or the feedback path by using the first compensation coefficient and / or the second compensation coefficient, thereby expanding the application range of the signal processing method and improving the convenience of DC offset compensation.

[0088] Figure 4 A flowchart of a signal processing method according to an embodiment of the present disclosure is shown in FIG. 4. Figure 4 As shown in the embodiment shown in FIG. 4, the method further comprises steps 401-403. Figure 3 When the temperature, humidity and other environments of the compensated transmit path and / or the compensated feedback path change, in order to ensure the accuracy of the DC offset compensation of the compensated transmit path and / or the compensated feedback path, the method further comprises steps 401-403.

[0089] Step 401: determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient.

[0090] In some embodiments, a third DC offset coefficient of a third loop can be determined based on the first compensation coefficient, wherein the third loop comprises the compensated transmit path and the compensated feedback path at a third phase shift angle.

[0091] For example Figure 1The first compensation coefficient is configured in the TX DC offset compensation module, the second compensation coefficient is configured in the FB DC offset compensation module, and the phase shift angle of the phase shifter is set as a third phase shift angle. By obtaining the feedback signal of the first signal in the compensation transmission path and the first signal in the compensation feedback path, the third DC offset coefficient can be determined by using the formula shown in formula 1.

[0092] In some embodiments, the third phase shift angle can be the same as or different from the first phase shift angle, and the present disclosure does not limit this.

[0093] In some embodiments, the fourth DC offset coefficient of the fourth loop can be determined based on the second compensation coefficient, wherein the fourth loop includes a compensation transmission path and a compensation feedback path under a fourth phase shift angle.

[0094] For example Figure 1 The first compensation coefficient is configured in the TX DC offset compensation module, the second compensation coefficient is configured in the FB DC offset compensation module, and the phase shift angle of the phase shifter is set as a fourth phase shift angle. By obtaining the feedback signal of the first signal in the compensation transmission path and the first signal in the compensation feedback path, the fourth DC offset coefficient can be determined by using the formula shown in formula 2.

[0095] In some embodiments, the third phase shift angle and the fourth phase shift angle satisfy a second preset condition, and the present disclosure does not limit the specific content of the second preset condition. For example, the second phase shift angle should be at least greater than the first phase shift angle by 1°, and at most greater than the first phase shift angle by 179°. For example, the second phase shift angle is different from the first phase shift angle. In other words, in some embodiments, the first preset condition can have the same content as the second preset condition.

[0096] Step 402, based on the third compensation coefficient, DC offset compensation is performed on the compensation transmission path.

[0097] In some embodiments, the first compensation coefficient can be calibrated based on the third compensation coefficient, so as to configure the calibrated first compensation coefficient in the TX DC offset compensation module, thereby realizing DC offset compensation on the compensation transmission path.

[0098] In some embodiments, the first compensation coefficient can be calibrated by the following formula:

[0099] d txr = d tx + dc txerr (Formula 6)

[0100] Wherein, d txr represents the calibrated first compensation coefficient, d tx represents the first compensation coefficient, and dc txerra third compensation coefficient is represented.

[0101] In step 403, a direct current offset compensation is performed on the compensation feedback path based on the fourth compensation coefficient.

[0102] In some embodiments, the second compensation coefficient can be calibrated based on the fourth compensation coefficient, and the calibrated second compensation coefficient is configured in the FB direct current offset compensation module, so as to realize the direct current offset compensation on the compensation feedback path.

[0103] In some embodiments, the calibration of the first compensation coefficient can be realized by the following formula:

[0104] d fbr = d fb + dc fberr (Formula 7)

[0105] Wherein, d fbr represents the calibrated second compensation coefficient, d fb represents the second compensation coefficient, and dc fberr represents the fourth compensation coefficient.

[0106] In summary, according to the signal processing method provided by the present disclosure, the third compensation coefficient is used to calibrate the compensation transmission path, and the fourth compensation coefficient is used to calibrate the compensation feedback path; the direct current offset compensation is performed on the compensation transmission path based on the third compensation coefficient; the direct current offset compensation is performed on the compensation feedback path based on the fourth compensation coefficient, so as to realize the direct current offset compensation on the compensation transmission path and / or the compensation feedback path, and ensure the accuracy of the direct current offset compensation on the compensation transmission path and / or the compensation feedback path when the external link changes.

[0107] Therefore, the present scheme has the following beneficial effects:

[0108] 1. The direct current offset compensation can be performed on the transmission path and / or the feedback path in real time under the condition that the first signal works, which expands the application range of the signal processing method and improves the convenience of the direct current offset compensation.

[0109] 2. The accuracy of the direct current offset compensation is ensured when the external link changes.

[0110] Figure 5 A structural schematic diagram of a signal processing device 500 provided by the embodiment of the present disclosure is provided, and the communication device comprises:

[0111] The first processing unit 510 is configured to determine a first DC offset coefficient of a first loop based on the first signal and a first phase shift angle of the first signal, the first loop comprising a transmission path and a feedback path at the first phase shift angle, the transmission path being configured to transmit the first signal, and the feedback path being configured to transmit a feedback signal of the first signal.

[0112] The second processing unit 520 is configured to determine a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition.

[0113] The third processing unit 530 is configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising a transmission path and a feedback path at the second phase shift angle.

[0114] The fourth processing unit 540 is configured to perform DC offset compensation on the transmission path and / or the feedback path based on the first DC offset coefficient and the second DC offset coefficient.

[0115] In some embodiments, the first processing unit 510 is further configured to determine a second signal based on the first signal and the first phase shift angle, the second signal being a feedback signal of the first signal at the first phase shift angle; and determine the first DC offset coefficient of the first loop based on the first signal and the second signal.

[0116] In some embodiments, the third processing unit 530 is further configured to determine a third signal based on the first signal and the second phase shift angle, the third signal being a feedback signal of the first signal at the second phase shift angle; and determine the second DC offset coefficient of the second loop based on the first signal and the third signal.

[0117] In some embodiments, the fourth processing unit 540 is further configured to determine a loop gain of the first loop and a loop gain of the second loop; determine a first compensation coefficient of the transmission path and / or a second compensation coefficient of the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop; perform DC offset compensation on the transmission path based on the first compensation coefficient to obtain a compensated transmission path; and / or perform DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path.

[0118] In some embodiments, the fourth processing unit 540 is further configured to determine a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, the third compensation coefficient being configured to calibrate the compensated transmission path, and the fourth compensation coefficient being configured to calibrate the compensated feedback path; perform DC offset compensation on the compensated transmission path based on the third compensation coefficient; and perform DC offset compensation on the compensated feedback path based on the fourth compensation coefficient.

[0119] In some embodiments, the fourth processing unit 540 is further configured to determine, based on the first compensation coefficient and the second compensation coefficient, a third DC offset coefficient of a third loop and a fourth DC offset coefficient of a fourth loop, the third loop comprising a compensated transmit path and a compensated feedback path at a third phase shift angle, the fourth loop comprising a compensated transmit path and a compensated feedback path at a fourth phase shift angle, the third phase shift angle and the fourth phase shift angle satisfying a second preset condition; determine a loop gain of the third loop and a loop gain of the fourth loop; and determine a third compensation coefficient and a fourth compensation coefficient based on the third DC offset coefficient, the fourth DC offset coefficient, the loop gain of the third loop, and the loop gain of the fourth loop.

[0120] In summary, the signal processing device according to the present disclosure comprises: a first processing unit configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmit path and a feedback path at the first phase shift angle, the transmit path being configured to transmit the first signal, and the feedback path being configured to transmit a feedback signal of the first signal; a second processing unit configured to determine a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; a third processing unit configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising the transmit path and the feedback path at the second phase shift angle; and a fourth processing unit configured to compensate the transmit path and / or the feedback path for DC offset based on the first DC offset coefficient and the second DC offset coefficient. The device according to the present disclosure determines the first DC offset coefficient and the second DC offset coefficient in the loop at two different phase shift angles, and then obtains the compensation coefficient of the transmit path and / or the feedback path, so that the transmit path and / or the feedback path can be compensated for DC offset in real time in the case of the first signal, thereby expanding the application range of the signal processing method and improving the convenience of DC offset compensation.

[0121] Since the device provided by the embodiments of the present disclosure corresponds to the methods provided by the above-mentioned several embodiments, the implementation of the methods is also applicable to the device provided by the present embodiment, which will not be described in detail in the present embodiment.

[0122] The method and device provided by the embodiments of the present disclosure are introduced in the above embodiments of the present disclosure. In order to realize the functions in the above-mentioned method provided by the embodiments of the present disclosure, the communication device can include a hardware structure, a software module, and realize the above-mentioned functions in the form of hardware structure, software module, or hardware structure plus software module. Some of the above-mentioned functions can be executed in the form of hardware structure, software module, or hardware structure plus software module.

[0123] Figure 6FIG. 6 is a structural diagram of a communication device 600 provided by an embodiment of the present application. The communication device 600 can be a network device, a terminal device, a chip, a chip system, a processor, or the like supporting the network device to implement the method, or a chip, a chip system, a processor, or the like supporting the terminal device to implement the method. The device can be used to implement the method described in the method embodiments, and details can be referred to the description in the method embodiments.

[0124] The communication device 600 can include one or more processors 601. The processor 601 can be a general-purpose processor or a special-purpose processor, or the like. For example, the processor 601 can be a baseband processor or a central processing unit. The baseband processor can be used to process a communication protocol and communication data, and the central processing unit can be used to control the communication device (for example, a base station, a baseband chip, a terminal device, a terminal device chip, a DU, a CU, or the like), execute a computer program, and process data of the computer program.

[0125] Optionally, the communication device 600 can further include one or more memories 602, and the memories 602 can have computer programs 604 stored thereon. The processor 601 executes the computer programs 604 to enable the communication device 600 to perform the method described in the method embodiments. Optionally, the memories 602 can further store data. The communication device 600 and the memories 602 can be separately arranged or integrated together.

[0126] Optionally, the communication device 600 can further include a transceiver 605 and an antenna 606. The transceiver 605 can be referred to as a transceiving unit, a transceiver, or a transceiving circuit, and is used to implement the transceiving function. The transceiver 605 can include a receiver and a transmitter. The receiver can be referred to as a receiver or a receiving circuit, and is used to implement the receiving function. The transmitter can be referred to as a transmitter or a transmitting circuit, and is used to implement the transmitting function.

[0127] Optionally, the communication device 600 can further include one or more interface circuits 606. The interface circuit 606 is used to receive code instructions and transmit the code instructions to the processor 601. The processor 601 runs the code instructions to enable the communication device 600 to perform the method described in the method embodiments.

[0128] In an implementation manner, the processor 601 can include a transceiver for implementing the receiving and transmitting functions. For example, the transceiver can be a transceiving circuit, or an interface, or an interface circuit. The transceiving circuit, the interface, or the interface circuit for implementing the receiving and transmitting functions can be separate or integrated together. The transceiving circuit, the interface, or the interface circuit described above can be used for reading and writing of codes / data, or the transceiving circuit, the interface, or the interface circuit described above can be used for transmission or transfer of signals.

[0129] In an implementation, the processor 601 can store a computer program 603, which, when run on the processor 601, can cause the communication device 600 to perform the methods described in the above method embodiments. The computer program 603 can be fixed in the processor 601, in which case the processor 601 can be implemented by hardware.

[0130] In an implementation, the communication device 600 can include a circuit, which can implement the functions of sending or receiving or communicating in the above method embodiments. The processor and the transceiver described in the present application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit (RFIC), a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and the transceiver can also be manufactured by various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), positive channel metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0131] The communication device described in the above embodiments can be a network device or a terminal device, but the scope of the communication device described in the present application is not limited thereto, and the structure of the communication device can not be limited by Figure 6 The communication device can be a standalone device or can be part of a larger device. For example, the communication device can be:

[0132] (1) a standalone integrated circuit (IC), or a chip, or a chip system or a subsystem;

[0133] (2) a set of one or more ICs, optionally the set of ICs can also include a storage component for storing data, a computer program;

[0134] (3) an ASIC, such as a Modem;

[0135] (4) a module that can be embedded in other devices;

[0136] (5) receivers, terminal devices, intelligent terminal devices, cellular phones, wireless devices, handsets, mobile units, car kits, network devices, cloud devices, artificial intelligence devices, and the like;

[0137] (6) others, and the like.

[0138] For the case that the communication device can be a chip or a chip system, refer to Figure 7 the structural schematic diagram of the chip.

[0139] Embodiments of the present disclosure also propose a chip, as shown in Figure 7 The chip includes at least one processor 701 and a communication interface 702. The communication interface 702 is configured to receive a signal input into the chip or output a signal from the chip. The processor 701 is in communication with the communication interface 702 and implements the method described in the above embodiments of the present disclosure through a logic circuit or by executing code instructions.

[0140] Optionally, the chip further includes a memory 703 configured to store necessary computer programs and data.

[0141] Embodiments of the present disclosure also propose a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are configured to cause a computer to execute the method described in the above embodiments of the present disclosure.

[0142] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether the function is implemented by hardware or software depends on the specific application and design requirements of the overall system. Those skilled in the art can implement the function in various ways for each specific application, but such implementation should not be interpreted as beyond the scope of the embodiments of the present application.

[0143] It should be noted that the terms "first", "second", and the like in the specification and claims of the present disclosure and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The implementation described in the following exemplary embodiments does not represent all implementations consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0144] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "certain embodiments", "an example", "a specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples as appropriate.

[0145] Any process or method descriptions or descriptions of the flow diagrams in the specification are understood to represent one or more steps that can be performed in any order, including sequentially, simultaneously, or in an overlapping manner, as appropriate, and that can include performing or deploying additional processes not depicted, depending upon the circumstances. Furthermore, any described process or method can be performed by hardware, software, or any combination thereof.

[0146] Logic and / or steps represented in the flow diagrams or otherwise described herein, for example, can be embodied in computer-readable instructions, which can be used to cause one or more processors to perform the actions indicated in the flow diagrams and / or described in this specification. Just as an example, one or more of the flow diagrams can represent a portion of a computer program that can be implemented in any computer readable medium for use by or in connection with an instruction execution system such as a computer based system or processor based or other system that can fetch the instructions from the instruction execution system, circuit or device, and execute the instructions. In the context of this specification, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus or device. Computer readable medium can comprise any one of the following: electrical connection (conventional or other) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Additionally, the computer readable medium can be paper or other comparable medium upon which the program is printed, as the program can be electronically captured, for example via an optical scanner, then compiled, interpreted, or otherwise processed, and stored in a computer memory in order to be executed.

[0147] It should be understood that parts of the embodiments of the present application can be realized by hardware, software, firmware, or a combination thereof. In the above-described embodiments, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if realized by hardware, and as in another embodiment, any one or a combination of the following technologies known in the art can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0148] Those skilled in the art of the present technology can understand that all or part of the steps carried out by the above-mentioned embodiment methods can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0149] In addition, each functional unit in each embodiment of the present application can be integrated into one processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be realized in the form of hardware or in the form of a software functional module. The integrated module, if realized in the form of a software functional module and sold or used as an independent product, can also be stored in a computer readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

[0150] Although the embodiments of the present application have been shown and described above, it should be understood that the above-described embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A signal processing method, characterized by, The method comprises: determining a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmitting path and a feedback path under the first phase shift angle, the transmitting path being used for transmitting the first signal, and the feedback path being used for transmitting a feedback signal of the first signal; determining a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; determining a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising a transmitting path and a feedback path under the second phase shift angle; determining a loop gain of the first loop and a loop gain of the second loop; determining a first compensation coefficient of the transmitting path and / or a second compensation coefficient of the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop and the loop gain of the second loop; performing DC offset compensation on the transmitting path based on the first compensation coefficient to obtain a compensated transmitting path; and / or performing DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path.

2. The method of claim 1, wherein, The method further comprises: determining a third compensation coefficient and a fourth compensation coefficient based on the first compensation coefficient and the second compensation coefficient, the third compensation coefficient being used for calibrating the compensated transmitting path, and the fourth compensation coefficient being used for calibrating the compensated feedback path; performing DC offset compensation on the compensated transmitting path based on the third compensation coefficient; 3. The method of claim 1, wherein, performing DC offset compensation on the compensated feedback path based on the fourth compensation coefficient. The method further comprises: determining a third DC offset coefficient of a third loop and a fourth DC offset coefficient of a fourth loop based on the first compensation coefficient and the second compensation coefficient, the third loop comprising the compensated transmitting path and the compensated feedback path under a third phase shift angle, and the fourth loop comprising the compensated transmitting path and the compensated feedback path under a fourth phase shift angle, the third phase shift angle and the fourth phase shift angle satisfying a second preset condition; 4. The method according to any one of claims 1 to 3, characterized in that, determining a loop gain of the third loop and a loop gain of the fourth loop; determining a third DC offset coefficient of a third loop and a fourth DC offset coefficient of a fourth loop based on the first compensation coefficient and the second compensation coefficient, the third loop comprising the compensated transmitting path and the compensated feedback path under a third phase shift angle, and the fourth loop comprising the compensated transmitting path and the compensated feedback path under a fourth phase shift angle, the third phase shift angle and the fourth phase shift angle satisfying a second preset condition; determining a loop gain of the third loop and a loop gain of the fourth loop; ​ 5. The method of claim 4, wherein, ​ ​ ​ The third compensation coefficient and the fourth compensation coefficient are determined based on the third DC offset coefficient, the fourth DC offset coefficient, a loop gain of the third loop, and a loop gain of the fourth loop.

6. A signal processing device, characterized by The method comprises: A first processing unit is configured to determine a first DC offset coefficient of a first loop based on a first signal and a first phase shift angle of the first signal, the first loop comprising a transmission path and a feedback path at the first phase shift angle, the transmission path being configured to transmit the first signal, and the feedback path being configured to transmit a feedback signal of the first signal; A second processing unit is configured to determine a second phase shift angle of the first signal, the second phase shift angle satisfying a first preset condition; A third processing unit is configured to determine a second DC offset coefficient of a second loop based on the first signal and the second phase shift angle, the second loop comprising a transmission path and a feedback path at the second phase shift angle; A fourth processing unit is configured to: determine a loop gain of the first loop and a loop gain of the second loop; determine a first compensation coefficient of the transmission path and / or a second compensation coefficient of the feedback path based on the first DC offset coefficient, the second DC offset coefficient, the loop gain of the first loop, and the loop gain of the second loop; perform DC offset compensation on the transmission path based on the first compensation coefficient to obtain a compensated transmission path; and / or, perform DC offset compensation on the feedback path based on the second compensation coefficient to obtain a compensated feedback path.

7. A communication device, characterized by The communication device comprises a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program stored in the memory, so that the communication device performs the method according to any one of claims 1-5.

8. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to make the computer perform the method according to any one of claims 1-5.

9. A chip, characterized by The chip comprises at least one processor and a communication interface, the communication interface is configured to receive a signal input into the chip or output a signal from the chip, the processor is in communication with the communication interface and implements the method according to any one of claims 1-5 through a logic circuit or execution of code instructions.

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