TDD digital front-end processing system suitable for ORAN equipment

Abstract

The invention discloses a TDD (Time Division Duplexing) digital front-end processing system suitable for ORAN (Orthogonal Radio Access Network) equipment. The TDD digital front-end processing system comprises an ORAN forward transmission interface module, a downlink module, an uplink module, a management module and a TDD control module, the ORAN forward transmission interface module is connected between an O-DU and an O-RU, the downlink module comprises a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC Mixer module, a CFR module, a DPD module and a PAP module, and the uplink module comprises a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, a PRACH channel processing module and an AGC module. The management module comprises a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module and a TA timing management module. According to the invention, a unified system test and management scheme can be realized, and radio frequency equipment and digital equipment of different manufacturers can be butted.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication devices, and particularly to a TDD digital front-end processing system applicable to ORAN devices. Background Art

[0002] For traditional radio access network devices, due to the use of CPRI and eCPRI interfaces in traditional devices, the interface protocols are relatively closed, and the interface protocols of each manufacturer are different. Moreover, the uplink and downlink processing of the data front-end of each manufacturer has different hierarchical processing, resulting in a large number of interfaces for each module and the lack of unity in the data link; as a result, the radio frequency devices and digital devices of different manufacturers are not compatible, and the device docking and debugging are cumbersome and complex, lacking a unified system test and device management solution. The Open Radio Access Network, abbreviated as ORAN, uses a design of independent building blocks, allowing interoperability between cellular network devices developed by different suppliers. With the development of technology and the improvement of data processing capabilities, as a component of ORAN, ORU will have a wider range of application fields.

[0003] Therefore, in view of this situation, a TDD digital front-end processing system based on FPGA and applicable to ORAN devices is developed to realize the docking of radio frequency devices and digital devices of different manufacturers. Summary of the Invention

[0004] The purpose of the present invention is to provide a TDD digital front-end processing system applicable to ORAN devices to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A TDD digital front-end processing system applicable to ORAN devices includes an ORAN fronthaul interface module, a downlink module, an uplink module, a management module, and a TDD control module;

[0006] The ORAN fronthaul interface module is interconnected between the O-DU and the O-RU. The downlink module includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC Mixer module, a CFR module, a DPD module, and a PAP module. The uplink module includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, a PRACH channel processing module, and an AGC module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module.

[0007] Preferably, the ORAN fronthaul interface module includes:

[0008] 10 / 25G line rate Fronthaul Interface;

[0009] C-Plane, U-Plane, S-Plane, M-Plane link data processing;

[0010] Beamforming Management;

[0011] AXI-Lite configuration interface;

[0012] Fronthaul Interface Package filter module processing;

[0013] ORAN router module;

[0014] Support for 1588v2 protocol;

[0015] Support for module simulation and system simulation;

[0016] Support for TDD Pattern and TDD Switch Point modes.

[0017] Preferably, the downlink module is used for the system to obtain beamforming-related information from the ORAN C-Plane section field, and then send it to the beamforming management module. According to the time information given by the timing module, weight processing is performed on all IQ data.

[0018] Preferably, the OFDM module is used for orthogonal frequency division multiplexing to perform mutual conversion between the frequency domain and the time domain. The module is configurable and supports 8 antennas and 8 CC dynamic aggregation on specific antennas. The OFDM module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling, and cyclic prefix insertion / removal.

[0019] Preferably, the functional modules of the CFR module include peak detection, peak scaling, distributor, and clipper pulse generator;

[0020] Peak detection: The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase that exceed the threshold.

[0021] Peak scaling: The detected peak and phase are used as the input of this module. This module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak and the threshold value, and the phase is the phase information of the peak signal.

[0022] Distributor: The distributor includes a peak distributor and a CPG distributor. The peak distributor calculates an indication signal after peak scaling based on the provided peak delay and the set maximum allowable delay, and this indication signal corresponds to a scaling factor.

[0023] Peak clipping pulse generator: The peak clipping pulse generator is designed to have the same frequency band as the input signal, and the coefficient of the peak clipping pulse is obtained by the method of filter design.

[0024] Preferably, the DPD simulation algorithm implementation platform of the DPD module is Matlab. The entire DPD simulation architecture consists of three modules, including source data reading, PD model calculation, and PA output calculation.

[0025] Preferably, the PAP module uses the Verilog coding language. The function implementation is divided into three major modules: the PAP_CTRL module, the SRL_DET module, and the Data_Ramping module, which jointly protect the PA.

[0026] Preferably, the PIM Cancellation module includes a passive intermodulation cancellation system. The entire system operates on the XCZU67 RF-SoC(5) hardware platform, which includes a PS processing unit(4), a PL logic unit(6), and a radio frequency link(8). Among them, PIM usually occurs in the radio frequency link(8). The PIM Cancellation module includes PIMI(3) and PIMD(2) software algorithm controls and a PIMC(9) custom logic module. Among them, the PIMD(2) and PIMI(3) modules are implemented by software control in a dual-frequency device, and the PIMC(9) module needs to be processed in real time by FPGA custom logic. The input and configuration are determined by the PIMD(2) and PIMI(3) modules. The Data Capture (7) required by the PIMD(2) and PIMI(3) is also completed by FPGA, and the PS processing unit(4) needs to be configured for this.

[0027] Preferably, the TDD control module is responsible for controlling and managing the time slot allocation of the uplink and downlink. Through precise time allocation, the TDD control module can achieve two-way communication on the same frequency band, effectively utilize spectrum resources, improve system capacity and spectrum efficiency. The TDD control module supports LTE TDD and NR TDD, and also supports the TDD Pattern and TDD Switch Point modes.

[0028] The TDD control module uses the Verilog coding language, and its function implementation is divided into eight major modules: radio_10ms_cdc module, frame_timing module, tdd_ctrl_S_AXI module, reg_mapping module, tdd_turn_point_gen module, tdd_sw_gen module, sw_project module, and tdd_mon module, which jointly manage the timing of uplink and downlink transmissions.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] System modular design framework;

[0031] Convenient transplantation of different hardware solutions, accelerating the R & D cycle;

[0032] Covering the entire product R & D and testing cycle;

[0033] Supporting seamless docking of devices from different ORAN manufacturers;

[0034] ORAN Interface / Beamforming Management / PIMC Cancellation / PAPOFDM / DFE Channel Filter / DFE DUC / DDC Mixer / CFR / DPD / PRACH / AGC Power Meter / TA Timing / Temperature Frequency Compensation / Calibration Interface / DFE / TDD_Ctrl unified peripheral management;

[0035] Signal simulation analysis for in-depth data simulation and analysis at multiple module points on the link. Description of the drawings

[0036] Figure 1 Schematic diagram for the specific module description of the present invention;

[0037] Figure 2 Schematic diagram of the ORAN fronthaul interface module of the present invention;

[0038] Figure 3 Schematic diagram of the Beamforming Management module of the present invention;

[0039] Figure 4 Schematic diagram of the OFDM module of the present invention;

[0040] Figure 5 Schematic diagram of the Channel Filter module of the present invention;

[0041] Figure 6 Schematic diagram of the DUC Mixer module of the present invention;

[0042] Figure 7 Schematic diagram of the CFR module of the present invention;

[0043] Figure 8 Schematic diagram of the DPD module of the present invention;

[0044] Figure 9 Schematic diagram of the PAP module of the present invention;

[0045] Figure 10 Schematic diagram of the PIM Cancellation module of the present invention;

[0046] Figure 11 Schematic diagram of the PRACH channel processing module of the present invention;

[0047] Figure 12 Schematic diagram of the TDD control module of the present invention. Specific implementation manners

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0049] Please refer to Figure 1 , the present invention provides a technical solution: a TDD digital front-end processing system applicable to ORAN devices, including an ORAN fronthaul interface module, a downlink module, an uplink module, a management module, and a TDD control module;

[0050] The ORAN fronthaul interface module is interconnected between the O-DU and the O-RU. The downlink module includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC Mixer module, a CFR module, a DPD module, and a PAP module. The uplink module includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, a PRACH channel processing module, and an AGC module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module. The radio frequency devices of this system can implement a unified system test and management solution, and realize the docking of radio frequency devices and digital devices from different manufacturers.

[0051] Refer to Figure 2, the system of the present invention uses VHDL coding language and integrates the ORAN fronthaul interface interconnected between the O-DU and the O-RU, including:

[0052] · 10 / 25G line rate Fronthaul Interface.

[0053] · C-Plane, U-Plane, S-Plane, M-Plane link data processing.

[0054] · Beamforming Management.

[0055] · AXI-Lite configuration interface.

[0056] · Fronthaul Interface Package filter module processing.

[0057] · ORAN router module.

[0058] · Support for 1588v2 protocol.

[0059] · Support for module simulation and system simulation.

[0060] · Support for TDD Pattern and TDD Switch Point modes.

[0061] In the present invention, the Beamforming Management module:

[0062] ORAN C-Plane section extension 1 is applicable to sending beamforming weights from the O-DU to the O-RU. When section extension 1 appears in the section description, the O-RU shall associate the set of beamforming weights transmitted in section extension 1 with the set of beamforming weights transmitted in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again. The meanings of each field are as follows:

[0063]

[0064]

[0065] ORAN C-Plane section extension 2 is applicable to sending beamforming attributes from the ODU to the ORU;

[0066]

[0067]

[0068] Refer to Figure 3 , this system obtains beamforming-related information from the ORAN C-Plane section field and then sends it to the beamforming management module. According to the time information given by the timing module, weight processing is performed on all IQ data;

[0069] Refer to Figure 4 , OFDM:

[0070] Orthogonal Frequency Division Multiplexing (OFDM) performs mutual conversion between the frequency domain and the time domain. The module is configurable and supports up to 8 antennas

[0071] And up to 8 CCs are dynamically aggregated on specific antennas. The module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling, and cyclic prefix insertion / removal. The supported functions are as follows:

[0072] The maximum sampling rate is 491.52 MSPS

[0073] Supports up to 8 CCs, supports LTE and 5G-NR

[0074] Supports subcarrier spacings (SCS) of 15 kHz, 30 kHz, and 60 kHz (FR1)

[0075] Supports FFT sizes of 512, 1K, 2K, and 4K

[0076] Supports up to 8 downlink or uplink (or antennas)

[0077] Each I or Q sample uses a 16-bit data interface

[0078] Enables CC programming through the processor (AXI4-Lite) interface

[0079] Provides an indication of CC buffer overflow through the status register

[0080] Delay matching passes the TUSER information attached to the data of the IP core

[0081] Refer to Figure 5 , the functions supported by the Channel Filter are as follows:

[0082] Each instance supports up to 16 CCs.

[0083] Supports 8 programmable coefficient sets.

[0084] 16-bit coefficients, up to 256 Tap Engines (symmetric) or 128 Tap Engines (asymmetric).

[0085] 16-bit or 18-bit I+Q input and output, AXI4-Stream interface.

[0086] Flexible time division multiplexing for multi-component carriers and antennas.

[0087] Support for time division duplex (TDD) switching of uplink and downlink channels.

[0088] Delay compensation sideband channel (TUSER) for sampling accurate frames.

[0089] Trigger coefficient switching, buffer refresh, uplink / downlink switching.

[0090] Support for power-down and dynamic power-saving modes.

[0091] Memory-mapped AXI4-Lite control and status interface provided with software API.

[0092] See Figure 6 , the functions supported by the DUC-DDC Mixer are as follows:

[0093] Support for up to 16 component carriers and up to 8 antennas.

[0094] Interpolation and decimation factors up to 16 times.

[0095] Cordic-based dual-mode NCO for operation without frequency error.

[0096] 16-bit or 18-bit I+Q input and output, AXI4-Stream interface.

[0097] Flexible time division multiplexing for multi-component carriers and antennas.

[0098] Delay compensation sideband channel (TUSER) for sampling accurate frames.

[0099] Trigger parameter change operation and buffer refresh.

[0100] Support for power-down and dynamic power-saving modes.

[0101] AXI4-Lite memory-mapped control and status interface provided with software API.

[0102] Support for uplink and downlink channel switching.

[0103] See Figure 7 , CFR module: The crest factor reduction (CFR) algorithm clips the signal before the power amplifier to effectively reduce the peak-to-average ratio of the system signal. By reducing the peak-to-average ratio of the signal, the back-off of the power amplifier is reduced, thereby improving the efficiency of the power amplifier.

[0104] The basic principle of the PC_CFR algorithm is to subtract the spectral pulse matching the input signal spectrum from the signal peak exceeding the threshold, so as to achieve the purpose of reducing the peak-to-average power ratio of the signal. In the figure, the process of peak clipping by the PC_CFR algorithm is as follows: the peak detection module detects the amplitude of the input signal, provides each peak position indication signal, as well as the amplitude and phase information of the corresponding peak; the peak scaling module generates an amplitude difference according to the peak amplitude and the threshold value, combines the amplitude difference with the phase information to generate a complex weight, which is used to scale the coefficient of the peak clipping pulse. While performing peak scaling, the distributor will allocate a peak clipping pulse generator for the detected peak signal to perform peak clipping. The peak-clipped signal is then multiplied by the coefficient of the scaled peak clipping pulse, and finally summed to obtain the peak-clipped signal;

[0105] The main functional modules of the PC_CFR algorithm include peak detection, peak scaling, distributor, and cancellation pulse generation (CPG). Among them, the cancellation pulse generator is the core part of the PC_CFR algorithm. The design of the filter coefficient is related to the impact of peak clipping on the EVM index, and its length and number determine the efficiency of peak clipping.

[0106] Peak detection: The peak detection module first calculates the amplitude and phase of the input signal, and then indicates the amplitude and phase exceeding the threshold.

[0107] Peak scaling: The detected peak and phase are used as the inputs of this module. This module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak and the threshold value, and the phase is the phase information of the peak signal.

[0108] Distributor: The distributor includes a peak distributor and a CPG distributor. Among them, the peak distributor calculates the indicated signal after peak scaling according to the provided peak delay and the set maximum allowable delay, and this indicated signal corresponds to the scaling coefficient.

[0109] Cancellation pulse generator: The design of the cancellation pulse generator is the core of the PC_CFR algorithm. The cancellation pulse is required to be designed to have the same frequency band as the input signal, and the coefficient of the cancellation pulse can be obtained by the method of filter design. First, a prototype filter matching the single-carrier spectrum needs to be designed. If the input signal is a single carrier, the coefficient of the prototype filter is the coefficient required for the cancellation pulse. For multi-carrier configurations, frequency shifting needs to be performed on the basis of the prototype filter. The replicated prototype filters after shifting are required to be placed at the center frequency points of each carrier, and then these replicated prototype filters are added together to obtain a composite multi-band filter, and the coefficient of this composite multi-band filter is the coefficient required for peak clipping.

[0110] See Figure 8 , DPD module:

[0111] The power amplifier PA (power amplifier) is a key component affecting the performance of a communication system, and the non-linearity of the power amplifier is its inherent characteristic. In a wireless communication system, the non-linear distortion of the power amplifier will have two consequences for the entire system: one is in-band signal distortion, which will cause signal distortion, increase the bit error rate of the system, and seriously affect the transmission of signals; the other is out-of-band spectrum expansion, and the out-of-band expanded spectrum will interfere with the normal transmission of signals of users in adjacent channels. In order to ensure the linearity and efficiency of the power amplifier, various methods can be used to linearize the power amplifier, such as Cartesian feedback technology, feedforward linearization, and digital predistortion. Among all these linearization processes, digital predistortion DPD (digital predistortion) is a technology with the highest cost performance.

[0112] In the PA, its non-linearity can be described by amplitude AM (amplitude modulation) distortion and phase distortion PM (phase modulation). Amplitude-amplitude (AM-AM) transformation and amplitude-phase (AM-PM) transformation.

[0113] For a memoryless power amplifier, this is the main part to consider. The essence of linearizing the power amplifier is actually to eliminate the influence brought by these two transformations of AM-AM and AM-PM. The 1dB compression point is used to determine the division of the linear region and the non-linear region (saturation region) of the power amplifier. The 1dB compression point is defined as: the position of the input signal when the actual gain value drops 1dB compared to the ideal gain value. When the input signal is small, the power amplifier works in the linear region, and the input and output are in a linear relationship.

[0114] For a system using non-constant envelope modulation technology commonly, the input signal is non-constant amplitude, and there will be relatively serious spectrum growth in the output signal, which will cause intermodulation interference to some adjacent channels, and ACPR (adjacent channel power rate) mainly reflects the interference of amplifier distortion to adjacent channels.

[0115] The ACPR value is defined as the ratio of the adjacent channel power to the main channel power. For the non-linearity of high-power amplifiers in a communication system, ACPR can be said to be the most practical and effective parameter. When testing the indicators of the system, the ACPR value is usually tested to see if it meets the requirements. When the bit error rate of the system is the same, the smaller the ACPR value, the higher the frequency band utilization rate and the smaller the mutual interference between channels. Therefore, it is more reasonable to use ACPR to analyze the working characteristics of a power amplifier operating in the non-linear region.

[0116] The error vector magnitude (EVM) is one of the important metrics for evaluating the performance of the crest factor reduction (CFR) algorithm and digital predistortion (DPD) algorithm in a system.

[0117] When analyzing the nonlinear characteristics of a power amplifier, it is first necessary to establish a suitable model for the power amplifier. Since different power amplifiers have different characteristics, corresponding models need to be established for different power amplifiers when conducting analysis, so as to more accurately describe some characteristics of the power amplifier. Generally, according to whether the power amplifier has memory effects, power amplifier models can be divided into two categories: memoryless models and memory models.

[0118] When the bandwidth of the signal becomes wider and wider, the memory effect becomes more and more significant. The result of the memory effect is that the current output of the power amplifier depends not only on the current input signal, but also on the past inputs. At this time, the memory of the power amplifier cannot be ignored. For such a power amplifier, the memoryless model cannot fully describe its nonlinear characteristics and can only provide very limited linearization ability during the predistortion process. Therefore, the power amplifier model must have memory.

[0119] The simulation algorithm implementation platform for DPD is Matlab. The entire DPD simulation architecture mainly consists of three modules, including source data reading, PD model calculation, and PA output calculation. Now, the working principles of the three modules will be briefly introduced respectively.

[0120] The source data reading model is used to read forward and feedback data. The data is obtained from the mat file collected by Xilinx software. There are a total of 8192 32-bit read data in the mat file. Among them, the first 4096 data are used as tx_data forward data, and the subsequent 4096 data are used as rx_data received data. The 32-bit rx_data is converted into two 16-bit signed I and Q signals, and these two signals are interpolated into a single 8192-point signal.

[0121] The rx_data after the PA is processed by a filter, and the output is the feedback data fb_data of the PA. The feedback data is the data after being amplified by the power amplifier PA. The amplification factor, i.e., the gain, of the feedback data needs to be eliminated. The method for eliminating the gain is to divide the power of the transmitted signal by the power of the feedback signal to obtain the amplification factor. Then, divide the feedback signal by the amplification factor, so that the unamplified feedback data can be obtained.

[0122] The PD model is used to implement the predistortion function. PD usually adopts the memory polynomial structure. Here, code can be written to select different types of PD models. In the PD module, the source data also needs to be read first, and the process is the same as that of the PA for reading the data source. After that, the dpd_process function is used to calculate the parameters of the PD module.

[0123] In the dpd_process, first, the input signal and the feedback signal are synchronized and power-aligned. Then, according to the model of the power amplifier, the corresponding PD model is selected. Finally, the parameters of the PD polynomial are calculated based on the forward and feedback data and stored in the corresponding data file for subsequent processing. Here, there are three polynomial models: memoryless polynomial, memory polynomial, and Volterra series. After calculating the PD parameters, the parameters are saved. Then, the calculation of the PD polynomial needs to be implemented, and usually, the memory polynomial structure is used to describe the PD model. The PD coefficients are obtained by reading the parameter data file. If there is no data file, the default output is equal to the input, that is, there is no PD function.

[0124] Refer to Figure 9 , PAP module:

[0125] The power amplifier is an important component in the communication system, mainly responsible for amplifying the radio frequency signal and outputting the corresponding power. Its performance and reliability have a significant impact on the operation of the entire transmission system. In wireless communication, the efficiency and performance optimization of the power amplifier are a continuously concerned issue because it not only relates to the quality of signal transmission but also directly affects the overall quality of communication services. For example, adopting the latest wireless standards can transmit more data over a fixed spectrum, but these new standards are very sensitive to the distortion of the base station power amplifier. Distortion will lead to a decline in signal quality and a reduction in data traffic. Therefore, wireless service providers need to take measures such as reducing the transmission power of the power amplifier or using a larger-power amplifier to cover the same area.

[0126] In addition, with the development of technology, such as the introduction of 5G communication, higher requirements are put forward for the efficiency and performance of the power amplifier. For example, the power amplifier with the Doherty architecture has received attention due to its high-efficiency characteristics, and this architecture can effectively alleviate the problem of increased power consumption brought by the power increase in 5G. The development and application of these technologies aim to improve the efficiency and reliability of the communication system and ensure the quality and speed of signal transmission.

[0127] This function uses the Verilog coding language, and the function implementation is divided into three major modules: (1) PAP_CTRL module; (2) SRL_DET module; (3) Data_Ramping module; to jointly protect the PA.

[0128] Refer to Figure 10, PIM Cancellation includes a Passive Inter Modulation (PIM) cancellation system. The entire system operates on the XCZU67 RF-SoC (5) hardware platform, which includes a PS processing unit (4), a PL logic unit (6), and a radio frequency link (8). PIM usually occurs in the radio frequency link (8). The whole is characterized by including modules such as PIMI (3) and PIMD (2) software algorithm controls and PIMC (9) custom logic. Among them, the PIMD (2) and PIMI (3) modules are implemented by software control in dual-frequency devices, and the PIMC (9) module needs to be processed in real time by FPGA custom logic. The input and configuration are determined by the PIMD (2) and PIMI (3) modules. The Data Capture (7) required for PIMD (2) and PIMI (3) is also completed by the FPGA, and the PS processing unit (4) needs to be configured for this.

[0129] See Figure 11 , the functions supported by the PRACH processing module of the present invention are as follows:

[0130] Support up to three independent frequency bands;

[0131] Support up to 8 antennas, with 16 component carriers per antenna on each frequency band;

[0132] Up to 245.76 MSPS component carrier sampling rate;

[0133] 16-bit or 18-bit IQ data input, 16-bit IQ data output;

[0134] Have a flexible time-division multiplexed AXI4-Stream data interface;

[0135] Each antenna processes up to 16 PRACH channels on all component carriers;

[0136] Support all LTE and 5G NR PRACH formats;

[0137] Memory-mapped AXI interface for control, status, and static PRACH scheduling;

[0138] Optional axi4-stream control interface for dynamic scheduling;

[0139] Power-down and dynamic power-saving modes.

[0140] See Figure 12, The TDD control module plays a core role in the TDD communication system and is mainly responsible for controlling and managing the time slot allocation of the uplink and downlink. Through precise time allocation, the TDD system can achieve two-way communication on the same frequency band, effectively utilize spectrum resources, and improve system capacity and spectrum efficiency. TDD_Ctrl supports LTE TDD and NR TDD, and also supports TDDPattern and TDD Switch Point modes.

[0141] This function uses the Verilog coding language, and the function implementation is divided into eight major modules: (1) radio_10ms_cdc module; (2) frame_timing module; (3) tdd_ctrl_S_AXI module; (4) reg_mapping module; (5) tdd_turn_point_gen module; (6) tdd_sw_gen module; (7) sw_project module; (8) tdd_mon module. They jointly manage the timing of uplink and downlink transmissions.

[0142] The content not described in detail in this specification belongs to the prior art well-known to those skilled in the art. Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A TDD digital front-end processing system applicable to ORAN devices, characterized in that: It includes an ORAN fronthaul interface module, a downlink module, an uplink module, a management module, and a TDD control module; The ORAN fronthaul interface module is interconnected between the O-DU and the O-RU. The downlink module includes a Beamforming Management module, an OFDM module, a Channel Filter module, a DUC Mixer module, a CFR module, a DPD module, and a PAP module. The uplink module includes a Beamforming module, a frequency compensation module, a temperature compensation module, a PIM Cancellation module, a PRACH channel processing module, and an AGC module. The management module includes a calibration interface configuration module, a power measurement interface configuration module, a DEF unified peripheral management module, and a TA timing management module.

2. The TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The ORAN fronthaul interface module includes: 10 / 25G line rate Fronthaul Interface; C-Plane, U-Plane, S-Plane, M-Plane link data processing; Beamforming Management; AXI-Lite configuration interface; Fronthaul Interface Package filter module processing; ORAN router module; Support for the 1588v2 protocol; Support for module simulation and system simulation; Support for TDD Pattern and TDD Switch Point modes.

3. A TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The downlink module is used for the system to obtain beamforming-related information from the ORAN C-Plane section field and then send it to the beamforming management module. According to the time information given by the timing module, weight processing is performed on all IQ data.

4. A TDD digital front-end processing system applicable to an ORAN device according to claim 1, characterized in that: The OFDM module is used to perform the mutual conversion between the frequency domain and the time domain for orthogonal frequency division multiplexing. The module is configurable and supports 8 antennas and the dynamic aggregation of 8 CCs on specific antennas. The OFDM module performs partial mapping of subcarriers, FFT / IFFT conversion, scaling, and cyclic prefix insertion / removal.

5. A TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The functional modules of the CFR module are peak detection, peak scaling, distributor, and peak clipping pulse generator; Peak detection: The peak detection module first calculates the amplitude and phase of the input signal and then indicates the amplitude and phase that exceed the threshold. Peak scaling: The detected peak and phase are used as the input to this module. This module determines the complex scaling, and its scaling amplitude is equal to the difference between the signal peak and the threshold value, and the phase is the phase information of the peak signal. Distributor: The distributor includes a peak distributor and a CPG distributor. The peak distributor calculates the indicated signal after peak scaling according to the provided peak delay and the set maximum allowable delay, and this indicated signal corresponds to the scaling coefficient; Peak Clipping Pulse Generator: The peak clipping pulse generator is designed to have the same frequency band as the input signal, and the coefficient of the peak clipping pulse is obtained by the method of filter design.

6. The TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The DPD simulation algorithm implementation platform of the DPD module is Matlab. The entire DPD simulation architecture consists of three modules, including source data reading, PD model calculation, and PA output calculation.

7. The TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The PAP module uses the Verilog coding language. The function implementation is divided into three major modules: PAP_CTRL module, SRL_DET module, and Data_Ramping module, which jointly protect the PA.

8. A TDD digital front-end processing system applicable to ORAN devices according to claim 1, characterized in that: The PIM Cancellation module includes a passive intermodulation cancellation system. The entire system runs on the XCZU67 RF-SoC(5) hardware platform, including a PS processing unit (4), a PL logic unit (6), and a radio frequency link (8). Among them, PIM usually occurs in the radio frequency link (8). The PIM Cancellation module includes PIMI(3) and PIMD(2) software algorithm controls and a PIMC(9) custom logic module. Among them, the PIMD(2) and PIMI(3) modules are implemented by software control in the dual-frequency device. The PIMC(9) module needs to be processed in real time by FPGA custom logic. The input and configuration are determined by the PIMD(2) and PIMI(3) modules. The Data Capture (7) required by the PIMD(2) and PIMI(3) is also completed by FPGA, and the PS processing unit (4) needs to be configured for this.

9. The TDD digital front-end processing system applicable to ORAN devices according to claim 1, wherein: The TDD control module is responsible for controlling and managing the time slot allocation of the uplink and downlink. Through precise time allocation, the TDD control module can achieve two-way communication on the same frequency band, effectively utilize spectrum resources, improve system capacity and spectrum efficiency. The TDD control module supports LTE TDD and NR TDD, and also supports the TDD Pattern and TDD Switch Point modes; The TDD control module uses the Verilog coding language. The function implementation is divided into eight major modules: radio_10ms_cdc module, frame_timing module, tdd_ctrl_S_AXI module, reg_mapping module, tdd_turn_point_gen module, tdd_sw_gen module, sw_project module, and tdd_mon module, which jointly manage the timing of uplink and downlink transmissions.

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