Integrated circuit device

Abstract

An integrated circuit device includes: a substrate; a fin-type active region on the substrate; comprising a plurality of nanosheets; a gate electrode surrounding the nanosheet stack structure on the fin-type active region; and a source / drain region connected to one end of the plurality of nanosheets on the fin-type active region, wherein the source / drain region includes a first source / drain layer in contact with an upper surface of the fin-type active region and side surfaces of the plurality of nanosheets, a second source / drain layer covering the first source / drain layer, a third source / drain layer covering a portion of the second source / drain layer, and a fourth source / drain layer covering the second source / drain layer and the third source / drain layer.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit devices. Background Art

[0002] As the integration degree of integrated circuit devices increases, the size of the devices has been reduced to the limit, and the size reduction of the devices has reached the limit. Therefore, in order to improve the performance of the devices, new methods need to be found by changing the structure of the devices, and integrated circuit devices including transistors such as MOSFETs with new structures have been proposed. Summary of the Invention

[0003] Generally, in some aspects, the present disclosure is directed to an integrated circuit device having a transistor including a multi-gate metal oxide semiconductor field effect transistor (MOSFET) that ensures operational reliability.

[0004] According to some embodiments, the present disclosure is directed to an integrated circuit device including: a substrate; a fin-type active region extending in a first horizontal direction on the substrate; a nanosheet stack structure including a plurality of nanosheets spaced apart from each other in a vertical direction and extending parallel to the upper surface of the fin-type active region at a position spaced apart from the upper surface of the fin-type active region; a gate electrode surrounding the nanosheet stack structure on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction; and source / drain regions connected to one end of the plurality of nanosheets on the fin-type active region, wherein the source / drain regions include: a first source / drain layer in contact with the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets; a second source / drain layer covering the first source / drain layer; a third source / drain layer covering a part of the second source / drain layer and having a top end lower than the top end of each of the first source / drain layer and the second source / drain layer; and a fourth source / drain layer covering the second source / drain layer and the third source / drain layer.

[0005] According to some embodiments, the present disclosure is directed to an integrated circuit device, comprising: a substrate having a first region and a second region; fin-type active regions extending in a first horizontal direction in each of the first region and the second region; a nanosheet stack structure including a plurality of nanosheets in each of the first region and the second region, the plurality of nanosheets being spaced apart in a vertical direction and extending parallel to the upper surface of the fin-type active regions at a position spaced apart from the upper surface of the fin-type active regions; gate electrodes surrounding the nanosheet stack structure in each of the first region and the second region on the fin-type active regions and extending in a second horizontal direction intersecting the first horizontal direction; and a first source / drain region connected to one end of the plurality of nanosheets in the first region on the fin-type active regions, wherein the first source / drain region includes: a first source / drain layer contacting the upper surface of the fin-type active regions and the side surfaces of the plurality of nanosheets, having a first thickness on the side surfaces of the plurality of nanosheets and a second thickness on the upper surface of the fin-type active regions; a second source / drain layer covering the first source / drain layer and having a third thickness smaller than each of the first thickness and the second thickness; a third source / drain layer covering a part of the second source / drain layer and having a top end lower than the top end of each of the first source / drain layer and the second source / drain layer; and a fourth source / drain layer covering the second source / drain layer and the third source / drain layer, and the second source / drain layer extends between the first source / drain layer and the third source / drain layer and between the first source / drain layer and the fourth source / drain layer.

[0006] According to some embodiments, the present disclosure is directed to an integrated circuit device, comprising: a substrate having a first region and a second region; fin-type active regions extending in a first horizontal direction in each of the first region and the second region; a nanosheet stack structure including a plurality of nanosheets in each of the first region and the second region, the plurality of nanosheets being spaced apart in a vertical direction and extending parallel to the upper surface of the fin-type active regions at a position spaced apart from the upper surface of the fin-type active regions; gate electrodes surrounding the nanosheet stack structure in each of the first region and the second region on the fin-type active regions and extending in a second horizontal direction intersecting the first horizontal direction; a first source / drain region connected to one end of the plurality of nanosheets on the fin-type active region in the first region; and a second source / drain region connected to one end of the plurality of nanosheets on the fin-type active region in the second region, wherein the first source / drain region includes: a first source / drain layer in contact with the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets, having a first thickness on the side surfaces of the plurality of nanosheets and a second thickness on the upper surface of the fin-type active region; a second source / drain layer covering the first source / drain layer and having a third thickness smaller than each of the first thickness and the second thickness; a third source / drain layer covering a part of the second source / drain layer, having a top end lower than the top ends of each of the first source / drain layer and the second source / drain layer, and having a concave upper surface; and a fourth source / drain layer covering the second source / drain layer and the third source / drain layer, the second source / drain region includes a fifth source / drain layer in contact with the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets, a sixth source / drain layer covering the fifth source / drain layer and having a convex upper surface, and a seventh source / drain layer covering the sixth source / drain layer and having a convex upper surface, and the top ends of each of the fourth source / drain layer and the seventh source / drain layer are at a vertical level higher than the top end of the nanosheet stack structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0008] Figures 1 to 4 , Figure 5A , Figure 5B and Figures 6 to 13 are cross-sectional views showing examples of a method of manufacturing an integrated circuit device according to some embodiments.

[0009] Figure 14A , Figure 14B and Figure 15 are cross-sectional views of examples of integrated circuit devices according to some embodiments.

[0010] Figure 16 is a cross-sectional view of an example of an integrated circuit device according to some embodiments.

[0011] Figure 17 and Figure 18 are cross-sectional views of examples of integrated circuit devices according to some implementations. Detailed implementation

[0012] The example implementations will be described in detail below with reference to the accompanying drawings.

[0013] Figures 1 to 4 、 Figure 5A 、 Figure 5B and Figures 6 to 13 are cross-sectional views showing examples of methods for manufacturing integrated circuit devices according to some implementations. For example, Figures 1 to 4 and Figure 5A are Y-Z vertical cross-sectional views, Figure 5B and Figures 6 to 13 are X-Z vertical cross-sectional views, Figure 5B is a cross-sectional view taken along the line Figure 5A VB-VB'.

[0014] In Figure 1 , a plurality of sacrificial semiconductor layers 106S and a plurality of nanosheet semiconductor layers NS can be alternately stacked one layer at a time on a substrate 102. The plurality of sacrificial semiconductor layers 106S and the plurality of nanosheet semiconductor layers NS can include different semiconductor layers. The plurality of sacrificial semiconductor layers 106S can include a material having an etching selectivity with respect to the plurality of nanosheet semiconductor layers NS. In some implementations, the plurality of nanosheet semiconductor layers NS can include a material having etching characteristics the same as or similar to those of the material of the substrate 102. In some implementations, the plurality of sacrificial semiconductor layers 106S can include silicon germanium (SiGe), and the plurality of nanosheet semiconductor layers NS can include silicon (Si). However, the present disclosure is not limited thereto.

[0015] The plurality of sacrificial semiconductor layers 106S can all be formed to have the same thickness, but the present disclosure is not limited thereto. In some implementations, the thickness of the sacrificial semiconductor layer 106S closest to the substrate 102 among the plurality of sacrificial semiconductor layers 106S can be greater than the thickness of the remaining sacrificial semiconductor layers 106S.

[0016] The substrate 102 may include a semiconductor material, such as Si or germanium (Ge), or a compound semiconductor material, such as SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate 102 may include at least one of a group III-V material and a group IV material. The group III-V material may be a binary, ternary, or quaternary compound semiconductor material containing at least one group III element and at least one group V element. The substrate 102 may include a conductive region, e.g., a doped well or a doped structure. In some embodiments, when an n-type metal oxide semiconductor field effect transistor (NMOS) is formed on a portion of the substrate 102, that portion of the substrate 102 may include one of the above group III-V materials. In some embodiments, when a p-type metal oxide semiconductor field effect transistor (PMOS) is formed on a portion of the substrate 102, that portion of the substrate 102 may include Ge. In another example, the substrate 102 may have silicon-on-insulator (SOI).

[0017] In Figure 2 it, a stacked structure of a plurality of sacrificial semiconductor layers 106S and a plurality of nanosheet semiconductor layers NS and a portion of the upper side of the substrate 102 may be etched to form a plurality of trenches TRE. A plurality of fin-shaped active regions FA defined by the plurality of trenches TRE may be formed. The plurality of fin-shaped active regions FA may extend parallel to each other in a first horizontal direction (X direction). The plurality of fin-shaped active regions FA may protrude upward from the main surface 102M of the substrate 102 in a vertical direction (Z direction). The plurality of fin-shaped active regions FA may be arranged at a constant pitch in a second horizontal direction (Y direction).

[0018] A plurality of sacrificial semiconductor layers 106S and a plurality of nanosheet stacked structures NSS may be disposed on the plurality of fin-shaped active regions FA. The plurality of nanosheet stacked structures NSS may include a plurality of nanosheets N1, N2, and N3. The plurality of nanosheets N1, N2, and N3 may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, which are arranged to be sequentially spaced apart in a vertical direction (Z direction) from bottom to top. However, this is merely an example, and the present disclosure is not limited thereto. For example, the nanosheet stacked structure NSS may include four or more nanosheets. Here, for convenience of description, the first nanosheet N1 and the third nanosheet N3 are described as the lowermost nanosheet and the uppermost nanosheet, respectively, among the plurality of nanosheets N1, N2, and N3 included in the nanosheet stacked structure NSS.

[0019] In Figure 3In [the structure], a preliminary device isolation film 118p can be formed to cover multiple fin-type active regions FA, multiple sacrificial semiconductor layers 106S, and multiple nanosheet stack structures NSS and fill multiple trenches TRE. The preliminary device isolation film 118p can be formed to cover the side surfaces of multiple fin-type active regions FA, the side surfaces of multiple sacrificial semiconductor layers 106S, and the side surfaces and upper surface of multiple nanosheet stack structures NSS. For example, the preliminary device isolation film 118p can include a material containing at least one of silicon oxide, silicon nitride, and silicon oxynitride. The preliminary device isolation film 118p can include a single layer containing one insulating film, a bilayer containing two insulating films, or a multilayer containing a combination of at least three insulating films. For example, the preliminary device isolation film 118p can include two different types of insulating films. For example, the preliminary device isolation film 118p can include a silicon oxide film and a silicon nitride film. For example, the preliminary device isolation film 118p can include a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0020] In Figure 3 and Figure 4 [the structure], the device isolation film 118 can be formed by performing a recess process to remove the preliminary device isolation film 118p from its upper part to a specific thickness. To perform this recess process, dry etching, wet etching, or a combination of dry etching and wet etching can be used.

[0021] The recess process can be performed such that the upper surface of the device isolation film 118 is at the same or substantially similar level as the upper surface of the fin-type active region FA. As a result, the upper surface and side surfaces of the multiple nanosheet stack structures NSS on the multiple fin-type active regions FA and the side surfaces of the multiple sacrificial semiconductor layers 106S can be exposed.

[0022] In Figure 5A and Figure 5B [the structure], multiple dummy gate structures DGS extending across at least a portion of the multiple fin-type active regions FA can be formed over the multiple fin-type active regions FA, on which multiple nanosheet stack structures NSS and multiple sacrificial semiconductor layers 106S are formed. The multiple dummy gate structures DGS can extend parallel to each other in a second horizontal direction (Y direction).

[0023] The dummy gate structure DGS can have a structure in which an oxide film D12, a dummy gate layer D14, and a capping layer D16 are stacked in sequence. In an example of forming the dummy gate structure DGS, the oxide film D12, the dummy gate layer D14, and the capping layer D16 are sequentially formed to cover the exposed surfaces of the multiple fin-type active regions FA, the exposed surfaces of the multiple sacrificial semiconductor layers 106S, and the upper surface of the device isolation film 118, and then can be patterned to only retain the portions where the oxide film D12, the dummy gate layer D14, and the capping layer D16 are necessary.

[0024] The oxide film D12 can be formed by a thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), metalorganic ALD (MOALD), or metalorganic CVD (MOCVD) process. Each of the dummy gate layer D14 and the capping layer D16 can be formed by an ALD, CVD, PVD, MOALD, or MOCVD process. In some implementations, the dummy gate layer D14 can include polysilicon, and the capping layer D16 can include a silicon nitride film. However, the present disclosure is not limited thereto.

[0025] Thereafter, a gate spacer 130 can be formed to cover opposite side surfaces of the dummy gate structure DGS. To form the gate spacer 130, a spacer layer is formed on the semiconductor substrate 102 on which the dummy gate structure DGS is formed, and then, the spacer layer can be etched back again such that the gate spacer 130 remains. The gate spacer 130 can include, for example, a silicon nitride film.

[0026] In Figure 6 , the dummy gate structure DGS and the gate spacer 130 can be used as an etch mask to form a recessed space RS by etching away a portion of the plurality of nanosheet stack structures NSS and a portion of the plurality of sacrificial semiconductor layers 106S. The fin-type active region FA can be exposed on the lower surface of the recessed space RS. In some implementations, in the process of etching away a portion of the plurality of nanosheet stack structures NSS and a portion of the plurality of sacrificial semiconductor layers 106S, an upper portion of the fin-type active region FA can also be removed.

[0027] In Figure 6 and Figure 7 , when a portion of the plurality of nanosheet stack structures NSS and a portion of the plurality of sacrificial semiconductor layers 106S are etched, the etching conditions can be controlled such that the etching amount of the plurality of sacrificial semiconductor layers 106S is greater than the etching amount of the plurality of nanosheet stack structures NSS, and the side surfaces of the plurality of sacrificial semiconductor layers 106S are recessed more than the side surfaces of the plurality of nanosheet stack structures NSS, thereby forming a plurality of sacrificial recesses 106R.

[0028] In Figure 8In [the structure], a first source / drain layer 161, a second source / drain layer 163, and a preliminary source / drain layer 165P can be sequentially formed in the recessed space RS. The first source / drain layer 161 can be formed to cover the bottom surface and the side surface of the recessed space RS while filling multiple sacrificial recesses 106R. The second source / drain layer 163 can be formed to cover the surface of the first source / drain layer 161, and the preliminary source / drain layer 165P can be formed to cover the surface of the second source / drain layer 163. The second source / drain layer 163 can be located between the first source / drain layer 161 and the preliminary source / drain layer 165P. In some embodiments, the uppermost ends of each of the first source / drain layer 161, the second source / drain layer 163, and the preliminary source / drain layer 165P can be at a first vertical level LV1. For example, the upper surface of the third nanosheet N3, which is the uppermost nanosheet among the multiple nanosheets N1, N2, and N3, can be at the first vertical level LV1.

[0029] The first source / drain layer 161 can be formed from the fin-type active region FA and the multiple nanosheets N1, N2, and N3 exposed within the multiple sacrificial recesses 106R and the recessed space RS by using an epitaxial growth process. The second source / drain layer 163 can be formed from the first source / drain layer 161 by using an epitaxial growth process. The preliminary source / drain layer 165P can be formed from the second source / drain layer 163 by using an epitaxial growth process. The growth temperature of the second source / drain layer 163 can be higher than the growth temperature of each of the first source / drain layer 161 and the preliminary source / drain layer 165P. For example, the growth temperature of the second source / drain layer 163 can be about 5 °C to about 15 °C higher than the growth temperature of each of the first source / drain layer 161 and the preliminary source / drain layer 165P. For example, the growth temperature of the second source / drain layer 163 can be about 679 °C to about 688 °C, and the growth temperature of each of the first source / drain layer 161 and the preliminary source / drain layer 165P can be about 669 °C to about 678 °C

[0030] The second source / drain layer 163 may include a material different from that of each of the first source / drain layer 161 and the preliminary source / drain layer 165P. In some implementations, the first source / drain layer 161 and the preliminary source / drain layer 165P may include the same material. For example, the second source / drain layer 163 may include Si but not Ge. In some implementations, the second source / drain layer 163 may include undoped Si. In some implementations, the second source / drain layer 163 may include Si doped with an impurity such as boron (B). Each of the first source / drain layer 161 and the preliminary source / drain layer 165P may include SiGe. In some implementations, each of the first source / drain layer 161 and the preliminary source / drain layer 165P may include SiGe having a relatively low Ge content ratio. For example, each of the first source / drain layer 161 and the preliminary source / drain layer 165P may include SiGe having a Ge content ratio greater than 0% and less than or equal to about 10%. The Ge content ratio of each of the first source / drain layer 161 and the preliminary source / drain layer 165P may be referred to as the first Ge content ratio.

[0031] The first source / drain layer 161 may be in contact with the upper surface of the fin-type active region FA and the side surfaces of one ends of the plurality of nanosheets N1, N2, and N3. The first source / drain layer 161 may be formed to have a thickness of about 2 nm to about 5 nm on the fin-type active region FA and the side surfaces of the plurality of nanosheets N1, N2, and N3. The second source / drain layer 163 may be formed to have a thickness of about 0.5 nm to about 1.5 nm. The preliminary source / drain layer 165P may be formed to have a thickness of about 3 nm to about 6 nm.

[0032] In Figure 8 and Figure 9 it, the third source / drain layer 165 may be formed by reflowing the preliminary source / drain layer 165P. The third source / drain layer 165 formed by reflowing the preliminary source / drain layer 165P may have a thickness of about 6 nm to about 12 nm. The upper surface of the third source / drain layer 165 may have a concave shape. The growth temperature of the second source / drain layer 163 is higher than the growth temperatures of the first source / drain layer 161 and the preliminary source / drain layer 165P, and when the preliminary source / drain layer 165P is reflowed, the first source / drain layer 161 covered by the second source / drain layer 163 may maintain its shape without reflowing. The second source / drain layer 163 may perform the function of a reflow stop layer for preventing the first source / drain layer 161 from reflowing.

[0033] The uppermost end of the third source / drain layer 165 formed by refluxing the preliminary source / drain layer 165P may be located at a second vertical level LV2 lower than the first vertical level LV1. The second vertical level LV2 may be lower than the uppermost end of the nanosheet stack structure NSS and higher than the lowermost end of the nanosheet stack structure NSS. For example, the second vertical level LV2 may be lower than the upper surface of the third nanosheet N3, which is the uppermost nanosheet among the plurality of nanosheets N1, N2, and N3, and may be higher than the lower surface of the first nanosheet N1, which is the lowermost nanosheet among the plurality of nanosheets N1, N2, and N3.

[0034] In Figure 10 the fourth source / drain layer 167 and the source / drain capping layer 169 may be sequentially formed on the third source / drain layer 165 to form a plurality of source / drain regions 160, which respectively include the first source / drain layer 161, the second source / drain layer 163, the third source / drain layer 165, the fourth source / drain layer 167, and the source / drain capping layer 169. The fourth source / drain layer 167 may be formed from the second source / drain layer 163 and the third source / drain layer 165 by using an epitaxial growth process. The fourth source / drain layer 167 may cover the second source / drain layer 163 and the third source / drain layer 165. The fourth source / drain layer 167 may be formed to fill the recessed space RS. The upper surface of the fourth source / drain layer 167 may protrude from the recessed space RS and may have a convex shape. The source / drain capping layer 169 may be formed from the fourth source / drain layer 167 by using an epitaxial growth process. The source / drain capping layer 169 may be formed to cover the upper surface of the fourth source / drain layer 167.

[0035] The fourth source / drain layer 167 may include SiGe. In some embodiments, the fourth source / drain layer 167 may include SiGe having a relatively high Ge content ratio. For example, the fourth source / drain layer 167 may include SiGe having a Ge content ratio of about 40% to about 60%. The Ge content ratio of the fourth source / drain layer 167 may be referred to as the second Ge content ratio. The source / drain capping layer 169 may include Si or SiGe. In some embodiments, the source / drain capping layer 169 may include Si doped with an impurity such as boron (B). When each of the second source / drain layer 163 and the source / drain capping layer 169 includes Si doped with an impurity such as B, the concentration of the impurity included in the second source / drain layer 163 may be higher than the concentration of the impurity included in the source / drain capping layer 169. In some embodiments, the source / drain capping layer 169 may have a higher Ge content ratio than each of the first source / drain layer 161 and the third source / drain layer 165, and may include SiGe having a relatively low Ge content ratio compared to the fourth source / drain layer 167. For example, the source / drain capping layer 169 may include SiGe having a Ge content ratio greater than about 20% and less than about 40%. The Ge content ratio of the source / drain capping layer 169 may be referred to as the third Ge content ratio.

[0036] The fourth source / drain layer 167 may be formed such that the uppermost vertical level of the fourth source / drain layer 167 is higher than the first vertical level LV1. The source / drain capping layer 169 may be formed to have a thickness of about 1 nm to about 2 nm. The uppermost end of the source / drain region 160, i.e., the uppermost end of the source / drain capping layer 169, may be at a third vertical level LV3 higher than the first vertical level LV1.

[0037] In Figure 10 and Figure 11 , after the inter-gate insulating film 172 is formed on the plurality of dummy gate structures DGS and the plurality of source / drain regions 160, the inter-gate insulating film 172 may be planarized to remove the capping layer D16 covering the upper surface of the dummy gate layer D14 and the gate spacers 130 around the capping layer D16, and the inter-gate insulating film 172 may be polished from its upper surface to a certain thickness such that the upper surface of the inter-gate insulating film 172 is at approximately the same level as the upper surface of the dummy gate layer D14. In some embodiments, the inter-gate insulating film 172 may include a silicon oxide film.

[0038] In Figure 11 and Figure 12In [the structure], a plurality of gate spaces GS can be formed by removing a dummy gate layer D14 and an oxide film D12 thereunder that are exposed through an inter-gate insulating film 172 and gate spacers 130, and by removing a plurality of sacrificial semiconductor layers 106S. The surfaces of a plurality of nanosheets N1, N2, and N3 and a partial upper surface of a fin-type active region FA can be exposed through the gate spaces GS. In some embodiments, a portion of the plurality of sacrificial semiconductor layers 106S can be retained without being removed. In some embodiments, the dummy gate layer D14 and the oxide film D12 can be removed by performing a wet etching process. To perform the wet etching, for example, an etchant including nitric acid (HNO3), dilute hydrofluoric acid (DHF), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), or a combination thereof can be used.

[0039] In Figure 13 [the structure], a plurality of gate dielectric films 145 can be formed on the surfaces exposed in the plurality of gate spaces GS, and a plurality of gate electrodes 150 filled in the plurality of gate spaces GS can be formed on the plurality of gate dielectric films 145. For example, the plurality of gate dielectric films 145 can be formed to cover the surfaces of the plurality of nanosheets N1, N2, and N3, a partial upper surface of the fin-type active region FA, and the surfaces of the plurality of source / drain regions 160 that are exposed in the plurality of gate spaces GS. The plurality of gate electrodes 150 can extend parallel to each other in a second horizontal direction (Y direction). For example, the plurality of gate dielectric films 145 and the plurality of gate electrodes 150 can be formed by a replacement metal gate (RMG) process.

[0040] The gate dielectric film 145 can include a silicon oxide film, a high-k dielectric film, or a combination thereof. In some embodiments, the gate dielectric film 145 can include a stacked structure of an interface layer and a high-k dielectric film. The interface layer can include a low dielectric material having a dielectric constant of about 9 or less. For example, the interface layer can include an oxide, a nitride, or a nitrogen oxide. The high-k dielectric film can include a metal oxide or a metal nitride oxide. The high-k dielectric film can include a material having a higher dielectric constant than the silicon oxide film. For example, the high-k dielectric film can have a dielectric constant of about 10 to about 25. The high-k dielectric film can include a material selected from hafnium oxide, hafnium nitride oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, and combinations thereof. However, the materials included in the high-k dielectric film are not limited thereto. The high-k dielectric film can be formed by an ALD, CVD, or PVD process. The high-k dielectric film can have a thickness of about to about The thickness is as such, but not limited thereto. In some embodiments, the interface layer may be omitted. For example, the gate dielectric film 145 may include hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO3), tantalum oxide (Ta2O3), or titanium dioxide (TiO2).

[0041] In some embodiments, the gate dielectric film 145 may include a ferroelectric material film having ferroelectric properties or a paraelectric material film having paraelectric properties. For example, the gate dielectric film 145 may include a ferroelectric material film. For example, the gate dielectric film 145 may include a plurality of ferroelectric material films spaced apart from each other. For example, the gate dielectric film 145 may have a stacked layer structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0042] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. On the other hand, when at least one of the two capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0043] When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor including a ferroelectric material film can have a subthreshold swing (SS) of less than approximately 60 mV / decade.

[0044] The ferroelectric material film may have ferroelectric properties. For example, the ferroelectric material film may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, and lead zirconium titanate. Here, for example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0045] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on the ferroelectric material included in the ferroelectric material film, the type of dopant included in the ferroelectric material film may vary. When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of Gd, Si, Zr, Al, and Y. When the dopant is Al, the ferroelectric material film may include from about 3 atomic percent (at%) to about 8 at% of Al. Here, the ratio of the dopant may be the ratio of Al to the sum of hafnium and Al. When the dopant is Si, the ferroelectric material film may include from about 2 at% to about 10 at% of Si. When the dopant is Y, the ferroelectric material film may include from about 2 at% to about 10 at% of Y. When the dopant is Gd, the ferroelectric material film may include from about 1 at% to about 7 at% of Gd. When the dopant is Zr, the ferroelectric material film may include from about 50 at% to about 80 at% of Zr.

[0046] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0047] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film may be different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0048] The ferroelectric material film may have a thickness with ferroelectric properties. The thickness of the ferroelectric material film may be, for example, from about 0.5 nm to about 10 nm, but is not limited thereto. Since the threshold thickness representing ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0049] The gate electrode 150 may include a metal-containing layer for adjusting the work function and a metal-containing layer for gap filling, and the metal-containing layer for gap filling is filled in the upper surface of the metal-containing layer for adjusting the work function. The metal-containing layer for adjusting the work function may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), Nb, molybdenum (Mo), Hf, nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), Dy, Er and palladium (Pd). In some implementations, the gate electrode 150 may have a structure in which a metal nitride layer, a metal layer, a conductive cap layer and a gap filling metal film are stacked in sequence. The metal nitride layer and the metal layer may include at least one metal selected from Ti, tantalum (Ta), W, Ru, Nb, Mo and Hf. The gap filling metal film may include a W film or an Al film. In some embodiments, the gate electrode 150 may include a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W, but is not limited thereto.

[0050] The gate electrode 150 may include a main gate portion 150M covering an upper surface of the nanosheet stack structure NSS including the plurality of nanosheets N1, N2, and N3, and a plurality of sub-gate portions 150S connected to the main gate portion 150M and formed in a space between each of the plurality of nanosheets N1, N2, and N3 and the fin type active area FA.

[0051] Figure 14A , Figure 14B and Figure 15 is a cross-sectional view of an example of an integrated circuit device according to some implementations. Figure 14A is the YZ vertical section view, Figure 14B and Figure 15 is the XZ vertical section view, where Figure 14B It is along Figure 14A A cross-sectional view taken along line XIVB-XIVB', Figure 15 yes Figure 14B An enlarged cross-sectional view of area XV.

[0052] exist Figure 14A and Figure 14BIn [the structure], an interlayer insulating film 174 covering a plurality of gate electrodes 150 and the inter-gate insulating film 172 can be formed. For example, the interlayer insulating film 174 can include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the interlayer insulating film 174 can include a tetraethyl orthosilicate (TEOS) film or an ultra-low-k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK film can include a silicon carbon oxide (SiOC) film or a SiCOH film. The interlayer insulating film 174 and the inter-gate insulating film 172 can be partially etched to form a first contact hole 192H exposing the source / drain region 160. A metal silicide film 182 can be formed on the upper surface of the source / drain region 160 exposed through the first contact hole 192H. The metal silicide film 182 can include tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi).

[0053] In addition, the interlayer insulating film 174 can be partially etched to form a second contact hole 194H exposing the upper surface of the gate electrode 150 (i.e., the upper surface of the main gate portion 150M). In some embodiments, the first contact hole 192H and the second contact hole 194H can be formed together by a single etching process. However, the present disclosure is not limited thereto, and the first contact hole 192H and the second contact hole 194H can each be formed by a separate etching process. In some embodiments, the first contact hole 192H can extend into the source / drain region 160. For example, the first contact hole 192H can pass through the source / drain capping layer 169 and extend into the fourth source / drain layer 167, and the metal silicide film 182 can be in contact with the fourth source / drain layer 167.

[0054] Thereafter, the integrated circuit device 1 can be formed by forming a first contact plug 192 filled in the first contact hole 192H and a second contact plug 194 filled in the second contact hole 194H. The first contact plug 192 can be connected to the source / drain region 160 through the metal silicide film 182, and the second contact plug 194 can be connected to the gate electrode 150. In some embodiments, the first contact plug 192 and the second contact plug 194 can be formed together. However, the present disclosure is not limited thereto, and the first contact plug 192 and the second contact plug 194 can each be formed by a separate process. Each of the first contact plug 192 and the second contact plug 194 can include a metal material (such as W, Al, Cu, Ti, Ta, Ru, manganese (Mn), or Co), a metal nitride (such as TiN, TaN, CoN, or WN), or an alloy (such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphide (CoWBP)). In some embodiments, at least a portion of the first contact plug 192 and the second contact plug 194 can include a conduction barrier layer and a conductive core layer covering the conduction barrier layer. The conduction barrier layer can include Ti, Ta, TiN, TaN, or a combination thereof, and the conductive core layer can include Co, W, Cu, Ru, iridium (Ir), Mo, or a combination thereof. In a plan view, each of the first contact plug 192 and the second contact plug 194 can have a circular shape, an oval shape, or a polygonal shape, and can have a vertical column shape extending in the vertical direction (Z direction).

[0055] The integrated circuit device 1 can be a logic semiconductor chip. For example, the integrated circuit device 1 can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. Here, the logic semiconductor chip does not refer to a memory semiconductor chip, but to a semiconductor chip that performs logic operations. For example, the logic semiconductor chip can include logic units. In some embodiments, the logic semiconductor chip can include a logic unit and a storage unit together. The logic unit can include a plurality of circuit elements, such as transistors and resistors, and can be configured in various ways. The logic unit can be configured, for example, as AND, NAND, OR, NOR, exclusive OR (XOR), exclusive NOR (XNOR), inverter (INV), adder (ADD), buffer (BUF), delay element (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / inverter (OAI), AND / OR (AO), AND / OR / inverter (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, or latch, and the logic unit can be configured as a standard cell that performs a desired logic function, such as a counter.

[0056] The integrated circuit device 1 may include a fin-type active region FA protruding upward from a main surface 102M of a substrate 102 in a vertical direction (Z direction) and extending in a first horizontal direction (X direction), and a plurality of nanosheet stack structures NSS facing the upper surface of the fin-type active region FA at a position spaced apart from the upper surface of the fin-type active region FA, thereby providing a multi-gate MOSFET. In some embodiments, the integrated circuit device 1 may include a multi-gate PMOS.

[0057] A plurality of trenches TRE defining a plurality of fin-type active regions FA may be formed in the substrate 102. Side surfaces of the plurality of fin-type active regions FA may be covered with a device isolation film 118 filled in the plurality of trenches TRE. The level of the upper surface of the fin-type active region FA and the level of the upper surface of the device isolation film 118 may be the same or similar to each other.

[0058] The plurality of nanosheet stack structures NSS may be spaced apart from the upper surface of the fin-type active region FA. The plurality of nanosheet stack structures NSS may include a plurality of nanosheets N1, N2, and N3 extending parallel to the upper surface of the fin-type active region FA on the substrate 102.

[0059] The plurality of nanosheets N1, N2, and N3 forming one nanosheet stack structure NSS may be sequentially stacked one by one on the upper surface of the fin-type active region FA. In this example, one nanosheet stack structure NSS includes three nanosheets N1, N2, and N3. However, the present disclosure is not limited thereto. Each of the plurality of nanosheets N1, N2, and N3 may have a channel region. In some embodiments, the plurality of nanosheets N1, N2, and N3 may include the same material as the substrate 102.

[0060] On the fin-type active region FA, a plurality of gate electrodes 150 may extend in a second horizontal direction (Y direction intersecting the first horizontal direction (X direction)). The plurality of gate electrodes 150 may at least partially overlap with each of the plurality of nanosheet stack structures NSS in a vertical direction (Z direction). Each of the plurality of gate electrodes 150 may surround the nanosheet stack structure NSS. For example, each of the plurality of gate electrodes 150 may be formed to surround at least a portion of the plurality of nanosheets N1, N2, and N3 and cover the nanosheet stack structure NSS. The gate electrode 150 may include a main gate portion 150M covering the upper surface of the nanosheet stack structure NSS and a plurality of sub-gate portions 150S connected to the main gate portion 150M and formed in a space between the fin-type active region FA and the plurality of nanosheets N1, N2, and N3 (i.e., formed under each of the plurality of nanosheets N1, N2, and N3). A gate dielectric film 145 may be formed between the nanosheet stack structure NSS and the gate electrode 150 and between the fin-type active region FA and the gate electrode 150. The gate dielectric film 145 may surround the gate electrode 150.

[0061] Between the fin-type active region FA and the nanosheet stack structure NSS (i.e., between the fin-type active region FA and the first nanosheet N1), and between a plurality of nanosheets N1, N2, and N3 adjacent to each other in the vertical direction (Z direction) (i.e., between the first nanosheet N1 and the second nanosheet N2 and between the second nanosheet N2 and the third nanosheet N3), a plurality of sacrificial recesses 106R not filled with the gate dielectric film 145 and the gate electrode 150 can be defined.

[0062] A plurality of source / drain regions 160 can be formed on the plurality of fin-type active regions FA. Each of the plurality of source / drain regions 160 can be connected to one end of each of the plurality of nanosheets N1, N2, and N3 adjacent thereto.

[0063] A gate spacer 130 that sequentially covers the side surfaces of the gate electrode 150 can be formed on the plurality of nanosheet stack structures NSS. The gate spacer 130 can include a silicon nitride film, but is not limited thereto. The gate spacer 130 can cover the side surfaces of the main gate portion 150M within the gate electrode 150.

[0064] An inter-gate insulating film 172 and an interlayer insulating film 174 can be sequentially formed on the plurality of source / drain regions 160. Each of the inter-gate insulating film 172 and the interlayer insulating film 174 includes a silicon oxide film, but is not limited thereto.

[0065] A plurality of first contact plugs 192 can be connected to the plurality of source / drain regions 160. The first contact plugs 192 can pass through the interlayer insulating film 174 and the inter-gate insulating film 172 and be connected to the source / drain regions 160. A metal silicide film 182 can be located between the source / drain regions 160 and the first contact plugs 192. In some embodiments, the metal silicide film 182 can be omitted. A plurality of second contact plugs 194 can be connected to the plurality of gate electrodes 150. The second contact plugs 194 can pass through the interlayer insulating film 174 and be connected to the gate electrodes 150. Each of the first contact plugs 192 and the second contact plugs 194 can include a metal, a conductive metal nitride, or a combination thereof.

[0066] Each of the plurality of source / drain regions 160 can include a first source / drain layer 161, a second source / drain layer 163, a third source / drain layer 165, a fourth source / drain layer 167, and a source / drain capping layer 169.

[0067] The first source / drain layer 161 may be connected to the plurality of nanosheets N1, N2, and N3. In some embodiments, the first source / drain layer 161 may include a plurality of protrusions 161P that protrude toward the plurality of sub-gate portions 150S and are filled in the plurality of sacrificial recesses 106R. The plurality of protrusions 161P may face the plurality of sub-gate portions 150S, and the gate dielectric film 145 is located therebetween. The first source / drain layer 161 may have a first thickness T1 on the side surfaces of the plurality of nanosheets N1, N2, and N3, and may have a second thickness T2 on the fin-type active region FA. The first thickness T1 and the second thickness T2 may have substantially the same value. For example, each of the first thickness T1 and the second thickness T2 may be about 2 nm to about 5 nm. The first source / drain layer 161 may include SiGe. The first source / drain layer 161 may include SiGe having a relatively low Ge content ratio. For example, the first source / drain layer 161 may include SiGe having a Ge content ratio greater than 0% and about 10% or less.

[0068] The second source / drain layer 163 may have a third thickness T3 on the first source / drain layer 161. The third thickness T3 may have a value smaller than each of the first thickness T1 and the second thickness T2. For example, the third thickness T3 may be about 0.5 nm to about 1.5 nm. The second source / drain layer 163 may include a material different from that of each of the first source / drain layer 161 and the third source / drain layer 165. For example, the second source / drain layer 163 may include Si but not Ge. In some implementations, the second source / drain layer 163 may include undoped Si. In some implementations, the second source / drain layer 163 may include Si doped with an impurity such as B.

[0069] The third source / drain layer 165 may cover a portion of the second source / drain layer 163. For example, the third source / drain layer 165 may cover a portion of the lower side of the second source / drain layer 163. Based on the bottom surface of the source / drain region 160, the third source / drain layer 165 may have a fourth thickness T4 in a vertical direction (Z direction). The fourth thickness T4 may have a value greater than each of the first thickness T1, the second thickness T2, and the third thickness T3. For example, the fourth thickness T4 may be from about 6 nm to about 12 nm. In some embodiments, the third source / drain layer 165 may include the same material as the first source / drain layer 161. The third source / drain layer 165 may include SiGe. The third source / drain layer 165 may include SiGe having a relatively low Ge content ratio. For example, the third source / drain layer 165 may include SiGe having a Ge content ratio greater than 0% and about 10% or less. In some implementations, each of the first source / drain layer 161 and the third source / drain layer 165 may include SiGe having the same Ge content ratio.

[0070] The uppermost end of each of the first source / drain layer 161 and the second source / drain layer 163 may be at a first vertical level LV1. For example, the upper surface of the third nanosheet N3, which is the uppermost nanosheet among the plurality of nanosheets N1, N2, and N3, may be at the first vertical level LV1. The uppermost end of the third source / drain layer 165 may be at a second vertical level LV2 lower than the first vertical level LV1. The second vertical level LV2 may be lower than the uppermost end of the nanosheet stack structure NSS and higher than the lowermost end of the nanosheet stack structure NSS. For example, the second vertical level LV2 may be lower than the upper surface of the third nanosheet N3, which is the uppermost nanosheet among the plurality of nanosheets N1, N2, and N3, and may be higher than the lower surface of the first nanosheet N1, which is the lowermost nanosheet among the plurality of nanosheets N1, N2, and N3.

[0071] The uppermost end of the fourth source / drain layer 167 may be higher than the first vertical level LV1. The fourth source / drain layer 167 may include SiGe. In some embodiments, the fourth source / drain layer 167 may include SiGe having a relatively high Ge content ratio. For example, the fourth source / drain layer 167 may include SiGe having a Ge content ratio of about 40% to about 60%.

[0072] The source / drain capping layer 169 may be formed to have a thickness of about 1 nm to about 2 nm. The uppermost end of the source / drain region 160, i.e., the uppermost end of the source / drain capping layer 169, may be at a third vertical level LV3 that is higher than the first vertical level LV1. The source / drain capping layer 169 may include Si or SiGe. In some implementations, the source / drain capping layer 169 may include Si doped with an impurity such as B. When each of the second source / drain layer 163 and the source / drain capping layer 169 includes Si doped with an impurity such as B, the concentration of the impurity included in the second source / drain layer 163 may be higher than the concentration of the impurity included in the source / drain capping layer 169. In some embodiments, the source / drain capping layer 169 may have a higher Ge content ratio than each of the first source / drain layer 161 and the third source / drain layer 165, and may include SiGe having a relatively low Ge content ratio compared to the fourth source / drain layer 167. For example, the source / drain capping layer 169 may include SiGe having a Ge content ratio greater than about 20% and less than about 40%.

[0073] In the integrated circuit device 1, the first source / drain layer 161 and the third source / drain layer 165, which include SiGe having a relatively low Ge content ratio within the source / drain region 160, are formed to be thicker at the lower end of the source / drain region 160 than at the side portion of the source / drain region 160 to cover the side surfaces of each of the plurality of nanosheets N1, N2, and N3. The second source / drain layer 163 may extend between the first source / drain layer 161 and the third source / drain layer 165 and between the first source / drain layer 161 and the fourth source / drain layer 167 such that the shape of the first source / drain layer 161 remains unchanged during the process of forming the third source / drain layer 165. Accordingly, the electrical characteristics of the integrated circuit device 1 including the multi-gate MOSFET are improved, and operational reliability can be ensured.

[0074] Figure 16 is a cross-sectional view of an example of an integrated circuit device according to some embodiments. Specifically, Figure 16 is Figure 14B an enlarged cross-sectional view of region XV of

[0075] In Figure 16In the integrated circuit device 1a, the integrated circuit device 1a may include: a plurality of source / drain regions 160a, each source / drain region including a first source / drain layer 161a, a second source / drain layer 163, a third source / drain layer 165, a fourth source / drain layer 167, and a source / drain capping layer 169; a plurality of gate dielectric films 145a; and a plurality of gate electrodes 150a, including a main gate portion 150M covering an upper surface of a nanosheet stack structure NSS including a plurality of nanosheets N1, N2, and N3, and a plurality of sub-gate portions 150Sa connected to the main gate portion 150M and formed in spaces between each of the plurality of nanosheets N1, N2, and N3 and a fin-shaped active region FA.

[0076] The first source / drain layer 161a may cover side surfaces of each of the plurality of nanosheets N1, N2, and N3 and an upper surface of the fin-shaped active region FA located on a bottom surface of the recessed space RS. The plurality of sub-gate portions 150Sa and the plurality of gate dielectric films 145a covering the plurality of sub-gate portions 150Sa may pass through the first source / drain layer 161a. The plurality of gate dielectric films 145a may be in contact with the second source / drain layer 163. In the process of forming the plurality of gate spaces GS described with reference to Figure 11 and Figure 12 the first source / drain layer 161a may be formed by also removing the first source / drain layer 161 filled in the plurality of sacrificial recesses 106R, and the plurality of gate dielectric films 145a and the plurality of gate electrodes 150a may be formed to fill the plurality of gate spaces GS.

[0077] In the integrated circuit device 1a, even when the plurality of gate dielectric films 145a and the plurality of gate electrodes 150a pass through the first source / drain layer 161a, due to the second source / drain layer 163, portions of the first source / drain layer 161a in contact with the plurality of nanosheets N1, N2, and N3 may be retained. Accordingly, the electrical characteristics of the integrated circuit device 1a including the multi-gate MOSFET are improved, and operational reliability can be ensured.

[0078] Figure 17 and Figure 18 are cross-sectional views of examples of integrated circuit devices according to some embodiments. Specifically, Figure 17 is an X-Z vertical cross-sectional view, Figure 18 is Figure 17 an enlarged cross-sectional view of region XVIII of

[0079] In Figure 17 and Figure 18 the integrated circuit device 2 may include a first region R1 and a second region R2. A multi-gate PMOS may be provided in the first region R1, and a multi-gate NMOS may be provided in the second region R2.

[0080] In each of the first region R1 and the second region R2, the integrated circuit device 2 may include fin-type active regions FA that protrude upward from the main surface 102M of the substrate 102 in a vertical direction (Z direction) and extend in a first horizontal direction (X direction), and a plurality of nanosheet stack structures NSS that face the upper surface of the fin-type active regions FA at positions spaced apart from the upper surface of the fin-type active regions FA. A plurality of trenches TRE that define the plurality of fin-type active regions FA may be formed in the substrate 102. Side surfaces of the plurality of fin-type active regions FA may be covered with a device isolation film 118 filled in the plurality of trenches TRE. The plurality of nanosheet stack structures NSS may be spaced apart from the upper surface of the fin-type active regions FA. The plurality of nanosheet stack structures NSS may include a plurality of nanosheets N1, N2, and N3 that extend parallel to the upper surface of the fin-type active regions FA on the substrate 102. The plurality of nanosheets N1, N2, and N3 that form one nanosheet stack structure NSS may be stacked one by one in sequence on the upper surface of the fin-type active regions FA.

[0081] In each of the first region R1 and the second region R2, on the fin-type active regions FA, a plurality of gate electrodes 150 may extend in a second horizontal direction (Y direction) that intersects the first horizontal direction (X direction). The gate electrodes 150 may include a main gate portion 150M that covers the upper surface of the nanosheet stack structures NSS, and a plurality of sub-gate portions 150S that are connected to the main gate portion 150M and are formed in the space between the fin-type active regions FA and the plurality of nanosheets N1, N2, and N3 (i.e., formed on the lower side of each of the plurality of nanosheets N1, N2, and N3). A gate dielectric film 145 may be formed between the nanosheet stack structures NSS and the gate electrodes 150, and between the fin-type active regions FA and the gate electrodes 150.

[0082] In some embodiments, among the plurality of gate electrodes 150, at least a part of the gate electrodes 150 disposed in the first region R1 and formed on the nanosheet stack structures NSS including the plurality of nanosheets N1, N2, and N3 in contact with the first source / drain region 160-I, and at least a part of the gate electrodes 150 disposed in the second region R2 and formed on the nanosheet stack structures NSS including the plurality of nanosheets N1, N2, and N3 in contact with the second source / drain region 160-II, may include different materials. For example, among the plurality of gate electrodes 150, at least a part of the metal-containing layer for adjusting the work function included in the gate electrodes 150 disposed in the first region R1 and at least a part of the metal-containing layer for adjusting the work function included in the gate electrodes 150 disposed in the second region R2 may include different materials.

[0083] Between the fin-type active region FA and the nanosheet stack structure NSS (i.e., between the fin-type active region FA and the first nanosheet N1), and between the plurality of nanosheets N1, N2, and N3 adjacent to each other in the vertical direction (Z direction) (i.e., between the first nanosheet N1 and the second nanosheet N2 and between the second nanosheet N2 and the third nanosheet N3), a plurality of first sacrificial recesses 106R that are not filled with the gate dielectric film 145 and the gate electrode 150 and are located in the first region R1 and a plurality of second sacrificial recesses 106Ra that are not filled with the gate dielectric film 145 and the gate electrode 150 and are located in the second region R2 can be defined. In the first region R1, a plurality of first source / drain regions 160-I can be formed on the plurality of fin-type active regions FA, and in the second region R2, a plurality of second source / drain regions 160-II can be formed on the plurality of fin-type active regions FA. Each of the plurality of first source / drain regions 160-I and each of the plurality of second source / drain regions 160-II can be connected to one end of each of the plurality of nanosheets N1, N2, and N3 adjacent thereto.

[0084] A gate spacer 130 that sequentially covers the side surface of the gate electrode 150 can be formed on the plurality of nanosheet stack structures NSS. The gate spacer 130 can cover the side surface of the main gate portion 150M within the gate electrode 150.

[0085] The inter-gate insulating film 172 and the interlayer insulating film 174 can be sequentially formed on the plurality of first source / drain regions 160-I and the plurality of second source / drain regions 160-II.

[0086] A plurality of first contact plugs 192 can be connected to the plurality of first source / drain regions 160-I and the plurality of second source / drain regions 160-II. The plurality of first contact plugs 192 can pass through the interlayer insulating film 174 and the inter-gate insulating film 172 and be connected to the plurality of first source / drain regions 160-I and the plurality of second source / drain regions 160-II. The metal silicide film 182 can be located between the first source / drain region 160-I and the first contact plug 192 and between the second source / drain region 160-II and the first contact plug 192. The plurality of second contact plugs 194 as described above can be connected to the plurality of gate electrodes 150. The second contact plug 194 can pass through the interlayer insulating film 174 and be connected to the gate electrode 150.

[0087] Each of the plurality of first source / drain regions 160-I can include a first source / drain layer 161, a second source / drain layer 163, a third source / drain layer 165, a fourth source / drain layer 167, and a source / drain capping layer 169. The plurality of first source / drain regions 160-I can be Figure 14B and Figure 15For the multiple source / drain regions 160 shown, the multiple first sacrificial recesses 106R can be Figure 14B and Figure 15 the multiple sacrificial recesses 106R shown. In some implementations, similar to Figure 16 the source / drain region 160a shown, each of the multiple first source / drain regions 160-I can include a first source / drain layer 161a, a second source / drain layer 163, a third source / drain layer 165, a fourth source / drain layer 167, and a source / drain capping layer 169.

[0088] The first source / drain layer 161 may be connected to the plurality of nanosheets N1, N2, and N3. In some embodiments, the first source / drain layer 161 may include a plurality of protrusions 161P filled in the plurality of first sacrificial recesses 106R. The plurality of protrusions 161P may face the plurality of sub-gate portions 150S, with the gate dielectric film 145 therebetween. The first source / drain layer 161 may include SiGe having a relatively low Ge content ratio. For example, the first source / drain layer 161 may include SiGe having a Ge content ratio greater than 0% and about 10% or less. The second source / drain layer 163 may include a material different from that of each of the first source / drain layer 161 and the third source / drain layer 165. For example, the second source / drain layer 163 may include Si. In some embodiments, the second source / drain layer 163 may include undoped Si. In some embodiments, the second source / drain layer 163 may include Si doped with an impurity such as B. In some embodiments, the third source / drain layer 165 may include the same material as the first source / drain layer 161. The third source / drain layer 165 may include SiGe. The third source / drain layer 165 may include SiGe having a relatively low Ge content ratio. For example, the third source / drain layer 165 may include SiGe having a Ge content ratio greater than 0% and about 10% or less. In some embodiments, each of the first source / drain layer 161 and the third source / drain layer 165 may include SiGe having the same Ge content ratio. The fourth source / drain layer 167 may include SiGe. In some embodiments, the fourth source / drain layer 167 may include SiGe having a relatively high Ge content ratio. For example, the fourth source / drain layer 167 may include SiGe having a Ge content ratio of about 40% to about 60%. The source / drain capping layer 169 may include Si or SiGe. In some embodiments, the source / drain capping layer 169 may include Si doped with an impurity such as B. When each of the second source / drain layer 163 and the source / drain capping layer 169 includes Si doped with an impurity such as B, the concentration of the impurity included in the second source / drain layer 163 may be higher than the concentration of the impurity included in the source / drain capping layer 169. In some embodiments, the source / drain capping layer 169 may have a higher Ge content ratio than each of the first source / drain layer 161 and the third source / drain layer 165, and may include SiGe having a relatively low Ge content ratio compared to the fourth source / drain layer 167. For example, the source / drain capping layer 169 may include SiGe having a Ge content ratio greater than about 20% and less than about 40%.

[0089] Each of the plurality of second source / drain regions 160-II may include a fifth source / drain layer 162, a sixth source / drain layer 164, and a seventh source / drain layer 166. A plurality of internal insulating spacers 140 may be located between each of the plurality of second source / drain regions 160-II and the plurality of sub-gate portions 150. A portion of the gate dielectric film 145 may be between the plurality of sub-gate portions 150 and the plurality of internal insulating spacers 140 corresponding to each other. Each of the plurality of internal insulating spacers 140 may be in contact with the second source / drain region 160-II. The plurality of internal insulating spacers 140 may be located one by one between each of the plurality of nanosheets N1, N2, and N3. The plurality of internal insulating spacers 140 may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof.

[0090] The fifth source / drain layer 162 may cover the side surfaces of each of the plurality of nanosheets N1, N2, and N3 and the upper surface of the fin-shaped active region FA located on the bottom surface of the recessed space RS. The plurality of internal insulating spacers 140 may pass through the fifth source / drain layer 162 and be in contact with the seventh source / drain layer 166. The fifth source / drain layer 162 may be formed from the fin-shaped active region FA and the plurality of nanosheets N1, N2, and N3 exposed in the recessed space RS by using an epitaxial growth process. The fifth source / drain layer 162 may have a fifth thickness T5 on the side surfaces of each of the plurality of nanosheets N1, N2, and N3 and the upper surface of the fin-shaped active region FA. For example, the fifth thickness T5 may be about 0.5 nm to about 1.5 nm. In some embodiments, the fifth thickness T5 may have a value substantially the same as the third thickness T3.

[0091] The sixth source / drain layer 164 may cover the fifth source / drain layer 162. The sixth source / drain layer 164 may be formed from the fifth source / drain layer 162 by using an epitaxial growth process. The upper surface of the sixth source / drain layer 164 may have a convex shape. The maximum thickness of the sixth source / drain layer 164 may be a sixth thickness T6. The sixth thickness T6 may have a value greater than that of the fifth thickness T5. In some embodiments, the sixth thickness T6 may have a value smaller than that of the fourth thickness T4. The seventh source / drain layer 166 may be formed from the sixth source / drain layer 164 by using an epitaxial growth process. The seventh source / drain layer 166 may be formed to fill the recessed space RS and cover the sixth source / drain layer 164. The upper surface of the seventh source / drain layer 166 may protrude from the recessed space RS and may have a concave shape. The uppermost end of the seventh source / drain layer 166 may be higher than the uppermost end of the nanosheet stack structure NSS. The uppermost end of the portion of the sixth source / drain layer 164 disposed on the upper surface of the fin-shaped active region FA may be at a level lower than the uppermost end of the third source / drain layer 165. The uppermost end of the second source / drain region 160-II may be higher than the uppermost end of the nanosheet stack structure NSS. The uppermost end of the second source / drain region 160-II may be at substantially the same or similar vertical level as the uppermost end of the first source / drain region 160-I.

[0092] Each of the plurality of second source / drain regions 160-II may include Si but not Ge. Each of the fifth source / drain layer 162, the sixth source / drain layer 164, and the seventh source / drain layer 166 may include Si but not Ge. For example, the fifth source / drain layer 162 may include Si. In some embodiments, the fifth source / drain layer 162 may include Si without doping impurities. In some embodiments, the fifth source / drain layer 162 may include Si doped with an impurity such as B. In some embodiments, the fifth source / drain layer 162 and the second source / drain layer 163 may include the same material. For example, each of the sixth source / drain layer 164 and the seventh source / drain layer 166 may include one of SiAs, SiP, and SiC. In some embodiments, the sixth source / drain layer 164 may include SiGa, and the seventh source / drain layer 166 may include SiP.

[0093] Although this disclosure contains many specific implementation details, it should not be construed as limiting the scope of the claimed subject matter. Certain features described in the context of separate implementations in this disclosure can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately in multiple implementations or in any suitable sub-combination. Additionally, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be removed from that combination, and the combination can be directed to a sub-combination or a variant of a sub-combination.

[0094] This application claims priority to Korean Patent Application No. 10-2024-0005566, filed with the Korean Intellectual Property Office on January 12, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: A substrate; A fin-type active region extending in a first horizontal direction on the substrate; A nanosheet stack structure including a plurality of nanosheets spaced apart from each other in a vertical direction and extending parallel to the upper surface of the fin-type active region at a position spaced apart from the upper surface of the fin-type active region; A gate electrode surrounding the nanosheet stack structure on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction; And A source / drain region connected to one end of the plurality of nanosheets on the fin-type active region, Wherein the source / drain region includes: A first source / drain layer in contact with the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets; A second source / drain layer covering the first source / drain layer; A third source / drain layer covering a part of the second source / drain layer, the third source / drain layer having a top end lower than the top ends of each of the first source / drain layer and the second source / drain layer; and A fourth source / drain layer covering the second source / drain layer and the third source / drain layer.

2. The integrated circuit device according to claim 1, wherein the third source / drain layer has a concave upper surface with respect to the upper surface of the fin-type active region.

3. The integrated circuit device according to claim 2, wherein the fourth source / drain layer has a convex upper surface.

4. The integrated circuit device according to claim 1, Wherein the first source / drain layer has a first thickness on the side surfaces of the plurality of nanosheets and a second thickness on the upper surface of the fin-type active region, and Wherein the second source / drain layer has a third thickness, the third thickness being less than each of the first thickness and the second thickness.

5. The integrated circuit device according to claim 4, Wherein the third source / drain layer has a fourth thickness in the vertical direction on the upper surface of the fin-type active region, and Wherein the fourth thickness is greater than each of the first thickness and the second thickness.

6. The integrated circuit device according to claim 1, Wherein the first source / drain layer and the third source / drain layer include the same material, and Wherein the second source / drain layer includes a material different from the materials of each of the first source / drain layer and the third source / drain layer.

7. The integrated circuit device according to claim 1, Wherein the first source / drain layer and the third source / drain layer include silicon germanium (SiGe), Wherein the second source / drain layer includes silicon (Si), and The second source / drain layer does not include germanium (Ge).

8. The integrated circuit device according to claim 7, Wherein each of the first source / drain layer and the third source / drain layer includes SiGe having a first Ge content ratio, and Wherein the fourth source / drain layer includes SiGe having a second Ge content ratio higher than the first Ge content ratio.

9. The integrated circuit device according to claim 1, wherein the gate electrode includes a main gate portion extending in the second horizontal direction on the nanosheet stack structure and a plurality of sub-gate portions connected to the main gate portion and disposed between the fin-shaped active region and each of the plurality of nanosheets, and wherein the first source / drain layer includes a plurality of protrusions extending toward the plurality of sub-gate portions.

10. The integrated circuit device according to claim 1, further comprising a gate dielectric film surrounding the gate electrode, wherein the gate electrode includes a main gate portion extending in the second horizontal direction on the nanosheet stack structure and a plurality of sub-gate portions connected to the main gate portion and disposed between the fin-shaped active region and each of the plurality of nanosheets, and wherein the plurality of sub-gate portions and the portion of the gate dielectric film covering the plurality of sub-gate portions pass through the first source / drain layer such that the gate dielectric film contacts the second source / drain layer.

11. An integrated circuit device, comprising: a substrate having a first region and a second region; a fin-shaped active region extending in a first horizontal direction in each of the first region and the second region; a nanosheet stack structure including a plurality of nanosheets in each of the first region and the second region, the plurality of nanosheets being spaced apart in a vertical direction and extending parallel to the upper surface of the fin-shaped active region at a position spaced apart from the upper surface of the fin-shaped active region; a gate electrode surrounding the nanosheet stack structure in each of the first region and the second region on the fin-shaped active region and extending in a second horizontal direction intersecting the first horizontal direction; and a first source / drain region connected to one end of the plurality of nanosheets on the fin-shaped active region in the first region, wherein the first source / drain region includes a first source / drain layer in contact with the upper surface of the fin-shaped active region and the side surfaces of the plurality of nanosheets, the first source / drain layer having a first thickness on the side surfaces of the plurality of nanosheets and a second thickness on the upper surface of the fin-shaped active region, a second source / drain layer covering the first source / drain layer and having a third thickness smaller than each of the first thickness and the second thickness, a third source / drain layer covering a part of the second source / drain layer, the third source / drain layer having a top end lower than the top end of each of the first source / drain layer and the second source / drain layer, and a fourth source / drain layer covering the second source / drain layer and the third source / drain layer, and wherein the second source / drain layer extends between the first source / drain layer and the third source / drain layer and between the first source / drain layer and the fourth source / drain layer.

12. The integrated circuit device according to claim 11, wherein the top end of the third source / drain layer is lower than the top end of the nanosheet stack structure, and Wherein the uppermost end of the third source / drain layer is higher than the lowermost end of the nanosheet stack structure.

13. The integrated circuit device according to claim 12, wherein the third source / drain layer has a fourth thickness in the vertical direction on the upper surface of the fin-type active region, and wherein the fourth thickness is greater than the first thickness.

14. The integrated circuit device according to claim 11, wherein the third source / drain layer has a concave upper surface with respect to the upper surface of the fin-type active region, and wherein the fourth source / drain layer has a convex upper surface with respect to the upper surface of the fin-type active region.

15. The integrated circuit device according to claim 11, wherein each of the first source / drain layer and the third source / drain layer includes silicon germanium (SiGe) having a first germanium (Ge) content ratio, wherein the second source / drain layer includes silicon (Si), wherein the second source / drain layer does not include Ge, and wherein the fourth source / drain layer includes SiGe having a second Ge content ratio higher than the first Ge content ratio.

16. The integrated circuit device according to claim 11, further comprising a second source / drain region, the second source / drain region being connected to one end of the plurality of nanosheets on the fin-type active region in the second region, wherein the second source / drain region includes a fifth source / drain layer in contact with the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets, a sixth source / drain layer covering the fifth source / drain layer and having a convex upper surface, and a seventh source / drain layer covering the sixth source / drain layer and having a convex upper surface, wherein the uppermost end of the portion of the sixth source / drain layer disposed on the upper surface of the fin-type active region is at a vertical level lower than the uppermost end of the third source / drain layer, and wherein each of the uppermost ends of the fourth source / drain layer and the seventh source / drain layer is at a vertical level higher than the uppermost end of the nanosheet stack structure.

17. The integrated circuit device according to claim 16, wherein the second source / drain region includes silicon (Si), and wherein the second source / drain region does not include germanium (Ge).

18. The integrated circuit device according to claim 16, wherein the gate electrode includes a main gate portion extending in the second horizontal direction on the nanosheet stack structure and a plurality of sub-gate portions connected to the main gate portion and disposed between the fin-type active region and each of the plurality of nanosheets, and wherein a plurality of internal insulating spacers are between the second source / drain region and the plurality of sub-gate portions.

19. An integrated circuit device, comprising: a substrate having a first region and a second region; a fin-type active region extending in a first horizontal direction in each of the first region and the second region; A nanosheet stack structure, including a plurality of nanosheets in each of the first region and the second region, the plurality of nanosheets being spaced apart in a vertical direction and extending parallel to the upper surface of the fin-type active region at a position spaced apart from the upper surface of the fin-type active region; A gate electrode, surrounding the nanosheet stack structure in each of the first region and the second region on the fin-type active region, and extending in a second horizontal direction intersecting the first horizontal direction; A first source / drain region, connected to one end of the plurality of nanosheets on the fin-type active region in the first region; And A second source / drain region, connected to one end of the plurality of nanosheets on the fin-type active region in the second region, Wherein the first source / drain region includes A first source / drain layer, contacting the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets, the first source / drain layer having a first thickness on the side surfaces of the plurality of nanosheets and a second thickness on the upper surface of the fin-type active region, A second source / drain layer, covering the first source / drain layer and having a third thickness smaller than each of the first thickness and the second thickness, A third source / drain layer, covering a part of the second source / drain layer, the third source / drain layer having a top end lower than the top ends of each of the first source / drain layer and the second source / drain layer and a concave upper surface, and A fourth source / drain layer, covering the second source / drain layer and the third source / drain layer, Wherein the second source / drain region includes A fifth source / drain layer, contacting the upper surface of the fin-type active region and the side surfaces of the plurality of nanosheets, A sixth source / drain layer, covering the fifth source / drain layer and having a convex upper surface, and A seventh source / drain layer, covering the sixth source / drain layer, the seventh source / drain layer having a convex upper surface, and Wherein the top end of each of the fourth source / drain layer and the seventh source / drain layer is at a vertical level higher than the top end of the nanosheet stack structure.

20. The integrated circuit device according to claim 19, further including a gate dielectric film surrounding the gate electrode, Wherein the gate electrode includes a main gate portion extending in the second horizontal direction on the nanosheet stack structure, and includes a plurality of sub-gate portions connected to the main gate portion and disposed between the fin-type active region and each of the plurality of nanosheets, Among them, In the first region, the plurality of sub-gate portions and the portion of the gate dielectric film covering the plurality of sub-gate portions extend into the first source / drain layer such that the gate dielectric film contacts the second source / drain layer, and Wherein, in the second region, a plurality of internal insulating spacers are between the second source / drain region and the plurality of sub-gate portions.

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