Array substrate and display panel

Abstract

The invention relates to an array substrate and a display panel, the array substrate comprises a plurality of sub-pixels, and each sub-pixel comprises an opening area and a control area; the array substrate further comprises a first common electrode, a transparent shielding electrode and a pixel electrode, the pixel electrode is connected with the first common electrode through a first via hole, the transparent shielding electrode is connected with the pixel electrode through a second via hole, the first via hole and the second via hole are separately arranged, the first via hole is located in the control area, and the second via hole is located in the opening area; the second via hole is separated from the first via hole, and the second via hole is arranged in the opening region, so that the occupied space of the via hole in the control region can be reduced, the area of the control region is reduced, the area of the opening region is increased, and the pixel aperture ratio is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] In the pixels of a Thin Film Transistor-Liquid Crystal Display (TFT-LCD), the aperture ratio has a significant impact on aspects such as the brightness, contrast, and power consumption of the screen. Improving the aperture ratio of the pixels is the key to improving the quality of the liquid crystal display panel.

[0003] In a liquid crystal display panel of the Transparent Storage capacity and Shielding (TSS) architecture type, the use of a transparent shielding electrode to replace the original metal shielding electrode can greatly improve the transmittance, and thus improve the pixel aperture ratio. However, in the TSS architecture, the shallow holes for connecting the transparent shielding electrode and the pixel electrode and the deep holes for connecting the pixel electrode and the common electrode usually adopt a design of semi-overlapping holes, and this semi-overlapping hole structure occupies a large amount of space, which is disadvantageous to the aperture ratio of the liquid crystal display panel with a small-size pixel structure. Summary of the Invention

[0004] The present application provides an array substrate and a display panel, which can effectively improve the pixel aperture ratio of the array substrate, and thus improve the display quality of the display panel.

[0005] The present application provides an array substrate, the array substrate includes a plurality of sub-pixels, and each sub-pixel includes an opening area and a control area adjacent to the opening area;

[0006] The array substrate further includes:

[0007] A substrate;

[0008] A first metal layer, disposed above the substrate, and the first metal layer includes a first common electrode;

[0009] A transparent shielding electrode, disposed on a side of the first metal layer away from the substrate; and

[0010] A pixel electrode layer, disposed on a side of the transparent shielding electrode away from the first metal layer, the pixel electrode layer includes a plurality of pixel electrodes, the pixel electrodes are connected to the first common electrode through first vias, and the transparent shielding electrode is connected to the pixel electrodes through second vias;

[0011] Wherein, the first vias and the second vias are separated, and the first vias are located in the control area, and the second vias are located in the opening area.

[0012] In some embodiments, the opening region includes at least one main pixel opening region and at least one sub-pixel opening region, the pixel electrode includes at least one main pixel electrode and at least one sub-pixel electrode, the main pixel electrode is located in the main pixel opening region, and the sub-pixel electrode is located in the sub-pixel opening region;

[0013] The control region is located between the main pixel opening region and the sub-pixel opening region, and the second via is located in the main pixel opening region or the sub-pixel opening region and is disposed close to the control region.

[0014] In some embodiments, the first metal layer further includes a data line, and the data line extends along a first direction;

[0015] The transparent shielding electrode is located between the data line and the pixel electrode, and a positive projection of the transparent shielding electrode on the substrate covers at least a part of a positive projection of the data line on the substrate and at least a part of a positive projection of the pixel electrode on the substrate.

[0016] In some embodiments, the first metal layer further includes a first source electrode and a first drain electrode, and the first source electrode or the first drain electrode is connected to the pixel electrode through a third via. The third via is located in the control region, and the third via is located on one side of the first via in a second direction, and the second direction intersects with the first direction.

[0017] In some embodiments, the first metal layer further includes a second source electrode and a second drain electrode, and the second source electrode or the second drain electrode is connected to the pixel electrode through a fourth via. The fourth via is located in the control region, and the fourth via is located on one side of the first via in the second direction.

[0018] In some embodiments, the second via is located at an edge of the opening region and is adjacent to the control region.

[0019] In some embodiments, the second via is located on a center line of the opening region along the first direction.

[0020] In some embodiments, the second via is located at a corner of the opening region close to the data line.

[0021] In some embodiments, the array substrate further includes:

[0022] A second metal layer is located between the substrate and the first metal layer. The second metal layer includes data lines and a second common electrode. The data lines extend in a second direction, and the second common electrode is spaced apart from the data lines, where the second direction intersects the first direction.

[0023] The first common electrode is located between adjacent data lines and extends in the first direction.

[0024] The present application also provides a display panel, which includes the array substrate as described above.

[0025] The present application provides an array substrate and a display panel. The array substrate of the present application includes a first common electrode, a pixel electrode, and a transparent shielding electrode located between the two. Among them, the pixel electrode is connected to the first common electrode through a first via hole (i.e., a deep hole), and the transparent shielding electrode is connected to the pixel electrode through a second via hole (i.e., a shallow hole). The first via hole and the second via hole are separated, and the first via hole is located in the control area, and the second via hole is located in the opening area. The array substrate of the present application adopts a TSS architecture, separates the second via hole from the first via hole, and arranges the second via hole in the opening area, which can reduce the occupied space of the via holes in the control area, thereby reducing the area of the control area and increasing the opening area of the opening area, and further improving the pixel aperture ratio. Therefore, the array substrate of the present application effectively improves the problem of reduced aperture ratio caused by the large occupied space of the TSS deep and shallow holes in the control area in the prior art. Description of the Drawings

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] To more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0028] Figure 1 is a top view of an array substrate provided by the prior art;

[0029] Figure 2 is Figure 1 a cross-sectional view taken along line A-A' of an array substrate provided;

[0030] Figure 3 is a top view of an array substrate provided by an embodiment of the present application;

[0031] Figure 4 isFigure 3 A cross-sectional view taken along line B-B' of an array substrate provided;

[0032] Figure 5 is Figure 3 A cross-sectional view taken along line C-C' of an array substrate provided;

[0033] Figure 6 is Figure 3 A top view of the first metal layer of an array substrate provided;

[0034] Figure 7 is Figure 3 A top view of the second metal layer of an array substrate provided;

[0035] Figure 8 is Figure 3 A top view of the transparent shielding electrode of an array substrate provided;

[0036] Figure 9 is Figure 3 A top view of the pixel electrode layer of an array substrate provided;

[0037] Figure 10 is a top view of another array substrate provided by an embodiment of the present application;

[0038] Figure 11 is Figure 10 A cross-sectional view taken along line D-D' of an array substrate provided;

[0039] Figure 12 is Figure 10 A top view of the transparent shielding electrode of an array substrate provided;

[0040] Figure 13 is Figure 10 A top view of the pixel electrode layer of an array substrate provided;

[0041] Figure 14 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

[0042] Description of reference numerals:

[0043] 10-display panel; 100-array substrate; 101-sub-pixel; 102-opening area; 1021-main pixel opening area; 1022-sub-pixel opening area; 103-control area; 104-common electrode; 110-substrate; 120-first metal layer; 121-first common electrode; 123-data line; 130-transparent shielding electrode; 140-pixel electrode layer; 141-pixel electrode; 1411-main pixel electrode; 1412-sub-pixel electrode; 142-trunk electrode; 1421-first sub-trunk electrode; 1422-second sub-trunk electrode; 143 -branch electrode; 150-deep and shallow holes; 150'-connecting hole; 151-first via hole; 152-second via hole; 153-third via hole; 154-fourth via hole; 160-second metal layer; 161-scan line; 162-gate; 163-second common electrode; 171-first thin film transistor; 1711-first source; 1712-first drain; 172-second thin film transistor; 1721-second source; 181-gate insulating layer; 182-passivation layer; 183-color resist layer; 184-flat layer; 200-opposing substrate; 300-liquid crystal layer. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] Please refer to Figure 1 and Figure 2 , Figure 1 is a top view of an array substrate provided by the prior art. Figure 2 yes Figure 1 The A-A' cross-sectional view of the array substrate is provided. Please refer to Figure 2 The transparent shielding electrode 130 in the display panel structure is connected to the common electrode 104 through a half-overlapping hole 150, wherein the transparent shielding electrode 130 is connected to the pixel electrode 141 through a shallow hole, and the pixel electrode 141 is connected to the common electrode through a deep hole, and the deep hole is connected to the shallow hole to form the half-overlapping hole 150. Please refer to Figure 1 The deep and shallow holes 150 are arranged in the control area 103, and the control area 103 also includes other connecting holes 150'. Since the deep and shallow holes 150 in the form of half-overlapping holes occupy a larger space, the occupied area of the control area 103 is larger. Due to the limitation of the sub-pixel size, the area of the control area 103 increases, which will reduce the area of the opening area 102, resulting in a decrease in the pixel opening ratio.

[0046] To solve the above problems, the present application provides an array substrate 100. Please refer to Figures 3 - 5 , Figure 3 which is a top view of an array substrate 100 provided by an embodiment of the present application, Figure 4 and Figure 3 which is a cross-sectional view taken along line B-B' of an array substrate 100 provided by Figure 5 and Figure 3 which is a cross-sectional view taken along line C-C' of an array substrate 100 provided by

[0047] The array substrate 100 includes a plurality of sub-pixels 101. The plurality of sub-pixels 101 can be arranged in an array. The sub-pixels 101 can be red sub-pixels, green sub-pixels or blue sub-pixels. Among them, every three adjacent sub-pixels 101 form a pixel unit, and the array substrate 100 is composed of a plurality of pixel units arranged in an array. Please refer to Figure 3 , the sub-pixel 101 includes an opening area 102 and a control area 103 adjacent to the opening area 102. Among them, the opening area 102 allows light to pass through for image display, and the control area 103 is used to set control circuits such as thin-film transistors without displaying images.

[0048] Please refer to Figures 3 - 9 , the array substrate 100 further includes a substrate 110, a first metal layer 120, a transparent shielding electrode 130 and a pixel electrode layer 140. The first metal layer 120 is disposed above the substrate 110, and the first metal layer 120 includes a first common electrode 121; the transparent shielding electrode 130 is disposed on a side of the first metal layer 120 away from the substrate 110; the pixel electrode layer 140 is disposed on a side of the transparent shielding electrode 130 away from the first metal layer 120. The pixel electrode layer 140 includes a plurality of pixel electrodes 141. The pixel electrodes 141 are connected to the first common electrode 121 through a first via 151, and the transparent shielding electrode 130 is connected to the pixel electrodes 141 through a second via 152; wherein, the first via 151 and the second via 152 are separated, and the first via 151 is located in the control area 103, and the second via 152 is located in the opening area 102. The array substrate 100 of the present application adopts a TSS architecture, separates the second via 152 from the first via 151, and disposes the second via 152 in the opening area 102, which can reduce the occupied space of the via in the control area 103, thereby reducing the area of the control area 103 and increasing the opening area of the opening area 102 to improve the pixel aperture ratio.

[0049] Among them, the substrate 110 may be a rigid substrate, such as glass, or the substrate 110 may also be a flexible substrate, such as polyimide, but not limited thereto.

[0050] Please refer to Figure 6 , the first metal layer 120 further includes data lines 123, source electrodes, and drain electrodes. The data lines 123 extend along the first direction Y. The source electrode and the drain electrode are located in the control region 103, and one of the source electrode or the drain electrode is connected to the data line 123. The first common electrode 121 is located between adjacent data lines 123 and extends along the first direction Y.

[0051] Please refer to Figure 7 , the array substrate 100 further includes a second metal layer 160. The second metal layer 160 is located between the substrate 110 and the first metal layer 120. The second metal layer 160 includes scan lines 161, gate electrodes 162, and a second common electrode 163. The scan lines 161 extend along the second direction X. The gate electrodes 162 are located in the control region 103 and are connected to the scan lines 161. The second common electrode 163 is disposed at an interval from the data line 123 to be insulated from the scan line 161. The second common electrode 163 extends along the second direction X. The second common electrode 163 is used to form a storage capacitor with the metal layer above it. Among them, the second direction X intersects the first direction Y, and the included angle between the first direction Y and the second direction X is greater than 0° and less than or equal to 90°. Further, the first direction Y and the second direction X may be perpendicular.

[0052] In the present application, the array substrate 100 includes a plurality of data lines 123 extending along the first direction Y and a plurality of scan lines 161 extending along the second direction X. The plurality of data lines 123 and the plurality of scan lines 161 are arranged in a cross pattern to define a plurality of sub-pixels 101.

[0053] Please refer to Figure 3 , Figure 5 and Figure 8, the transparent shielding electrode 130 is at least located between the data line 123 and the pixel electrode 141. The orthographic projection of the transparent shielding electrode 130 on the substrate 110 covers at least a part of the orthographic projection of the data line 123 on the substrate 110 and at least a part of the orthographic projection of the pixel electrode 141 on the substrate 110. The transparent shielding electrode 130 is made of a transparent conductive material, which can shield the electric field coupling between the pixel electrode 141 and the data line 123, reduce the parasitic capacitance between the data line 123 and the pixel electrode 141, so as to reduce the influence of the parasitic capacitance on the screen display. At the same time, the transmittance is greatly improved. And a relatively large transparent storage capacitor is formed between the transparent shielding electrode 130 and the pixel electrode 141, which can further improve the performance of the array substrate 100. Specifically, the material of the transparent shielding electrode 130 can be a transparent metal oxide, such as Indium Tin Oxide (ITO), but not limited thereto.

[0054] Among them, the transparent shielding electrode 130 is connected to the pixel electrode 141 through the second via 152, and the pixel electrode 141 is connected to the first common electrode 121 through the first via 151 to realize the signal transmission between the first common electrode 121 and the transparent shielding electrode 130. The transparent shielding electrode 130 is connected to the pixel electrode 141 through the second via 152, and the pixel electrode 141 is connected to the first common electrode 121 through the first via 151, which can reduce the parasitic capacitance between the data line 123 and the pixel electrode 141, improve the vertical crosstalk (V-Crosstalk) problem. At the same time, a mesh structure can be formed to improve the horizontal crosstalk (H-Crosstalk) problem, so as to improve the display quality of the display panel 10. In this application, the first via 151 and the second via 152 are separately arranged, which can also avoid the coordination defect problem existing between the deep hole and the shallow hole in the TSS half-lap hole structure of the prior art.

[0055] Please refer to Figure 9, the pixel electrode layer 140 may include a plurality of the pixel electrodes 141 arranged in an array. The sub-pixels 101 are provided in one-to-one correspondence with the pixel electrodes 141, and the pixel electrodes 141 are located in the opening region 102. The pixel electrode 141 includes a main electrode 142 and a branch electrode 143. Among them, the main electrode 142 includes a first sub-main electrode 1421 and a second sub-main electrode 1422. The first sub-main electrode 1421 extends along the first direction Y, and the second sub-main electrode 1422 extends along the second direction X. The first sub-main electrode 1421 and the second sub-main electrode 1422 are arranged in a cross shape, for example, in a cross-shaped structure. The branch electrode 143 is located in the region surrounded by the main electrode 142. The branch electrode 143 is arranged at a certain inclination angle with respect to the main electrode 142, and the branch electrode 143 is connected to the main electrode 142. Among them, please refer to Figure 3 , Figure 6 and Figure 9 , in the opening region 102, the first common electrode 121 may be disposed directly below the first sub-main electrode 1421, that is, the orthographic projection of the first sub-main electrode 1421 on the substrate 110 covers the orthographic projection of the first common electrode 121 on the substrate 110, so as to reduce the influence of the first common electrode 121 on the transmittance of the opening region 102. In the control region 103, in order to avoid other traces, the first common electrode 121 may be arranged in a zigzag shape or in a straight line along the first direction Y.

[0056] In some embodiments, one pixel electrode 141 is provided in one opening region 102. The pixel electrode 141 may be an integral body. The control region 103 is located between adjacent pixel electrodes 141. The control region 103 includes a thin film transistor, and the thin film transistor is connected to the pixel electrode 141 to realize the control of the pixel electrode 141. Among them, the thin film transistor includes a gate 162, a source, a drain, and an active layer. The second via 152 is located in the opening region 102 and is disposed close to the control region 103, so that the second via 152 and the first via 151 are kept at a relatively close distance, avoiding affecting the signal transmission efficiency and at the same time reducing the influence on the aperture ratio of the opening region 102.

[0057] Specifically, the control region 103 includes a first thin film transistor 171. The first thin film transistor 171 includes a first source electrode 1711 and a first drain electrode 1712. The first source electrode 1711 and the first drain electrode 1712 are located in the first metal layer 120. Among them, the first source electrode 1711 or the first drain electrode 1712 is connected to the pixel electrode 141 through a third via 153. The third via 153 is located in the control region 103, and the third via 153 is located on one side of the first via 151 in the second direction X, that is, the first via 151 and the third via 153 are arranged along the second direction X. Since the second via 152 is provided in the opening region 102 and does not occupy the space of the control region 103, therefore, the arrangement of the first via 151 and the third via 153 located in the control region 103 can be adjusted so that the first via 151 and the third via 153 are arranged along the second direction X, so as to reduce the occupied area of the control region 103 in the first direction Y, thereby correspondingly increasing the area of the opening region 102 and improving the pixel aperture ratio.

[0058] In some embodiments, please refer to Figures 3 - 9 , the opening region 102 includes at least one main pixel opening region 1021 and at least one sub-pixel opening region 1022. The pixel electrode 141 includes at least one main pixel electrode 1411 and at least one sub-pixel electrode 1412. The main pixel electrode 1411 is located in the main pixel opening region 1021, and the sub-pixel electrode 1412 is located in the sub-pixel opening region 1022; the control region 103 is located between the main pixel opening region 1021 and the sub-pixel opening region 1022. The control region 103 includes at least one thin film transistor for controlling the pixel electrode 141; the second via 152 is located in the main pixel opening region 1021 or the sub-pixel opening region 1022 and is disposed close to the control region 103 so that a relatively short distance is maintained between the second via 152 and the first via 151 to avoid affecting the signal transmission efficiency.

[0059] Specifically, please refer to Figures 3 - 9, taking the example that the opening area 102 includes one main pixel opening area 1021 and one sub-pixel opening area 1022, the main pixel opening area 1021 and the sub-pixel opening area 1022 are arranged along the first direction Y, the control area 103 is located between the main pixel opening area 1021 and the sub-pixel opening area 1022, the control area 103 includes the first thin film transistor 171 and the second thin film transistor 172, the first thin film transistor 171 is connected to the main pixel electrode 1411 to control the main pixel electrode 1411, and the second thin film transistor 172 is connected to the sub-pixel electrode 1412 to control the sub-pixel electrode 1412. Among them, the second thin film transistor 172 includes a second source electrode 1721 and a second drain electrode, the second source electrode 1721 and the second drain electrode are located in the first metal layer 120, the second source electrode 1721 or the second drain electrode is connected to the pixel electrode 141 through a fourth via 154, the fourth via 154 is located in the control area 103, and the fourth via 154 is located on one side of the first via 151 in the second direction X, that is, the first via 151, the third via 153, and the fourth via 154 are arranged along the second direction X. Since the second via 152 is arranged in the opening area 102 and does not occupy the space of the control area 103, therefore, the arrangement of the first via 151, the third via 153, and the fourth via 154 located in the control area 103 can be adjusted so that the first via 151, the third via 153, and the fourth via 154 are arranged along the second direction X to reduce the occupied area of the control area 103 in the first direction Y, thereby correspondingly increasing the area of the opening area 102 and improving the pixel aperture ratio.

[0060] In some embodiments, please refer to Figure 3 and Figure 6 , the first thin film transistor 171 and the second thin film transistor 172 can share one source electrode or one drain electrode to further reduce the space occupied by the control area, thereby further improving the pixel aperture ratio. For example, please refer to Figure 3 , the first thin film transistor 171 may include the first source electrode 1711 and the first drain electrode 1712, the second thin film transistor 172 may include the second source electrode 1721 and the first drain electrode 1712, and the first thin film transistor 171 and the second thin film transistor 172 can share one first drain electrode 1712.

[0061] In the present application, especially for a small-sized pixel structure, and for the array substrate 100 where the control region 103 includes a plurality of thin film transistors, adopting the solution of the present application, after the second vias 152 are disposed in the opening region 102, it is beneficial to adjust the layout space of other vias in the control region 103, so that these vias in the control region 103 are arranged along the second direction X as much as possible. Furthermore, the width of the control region 103 in the first direction Y can be compressed, the occupied area of the control region 103 can be reduced, thereby increasing the opening area of the opening region 102, improving the transmittance, and further improving the pixel aperture ratio.

[0062] In some embodiments, please refer to Figure 3 and Figure 10 , the second vias 152 may be disposed at the edge of the opening region 102 and adjacent to the control region 103, that is, the second vias 152 are located at the edge of the opening region 102 adjacent to the control region 103; in the present application, the second vias 152 are disposed at the edge of the opening region 102 to avoid forming a common electrode sacrificial opening under the pixel electrode 141 in the middle region of the opening region 102, which affects the aperture ratio.

[0063] In some embodiments, please refer to Figure 3 , the second vias 152 may be located on the center line of the opening region 102 along the first direction Y, where the pixel electrode 141 is symmetric about the center line OO'. Disposing the second vias 152 on the center line OO' of the pixel electrode 141 and adjacent to the control region 103 can maintain the symmetry of the pixel electrode 141, ensure the uniformity of display, and provide a better viewing angle.

[0064] In some embodiments, please refer to Figure 10 , the second vias 152 may be located at the corner of the opening region 102 close to the data line 123. At this time, the aperture ratio of the array substrate 100 is higher.

[0065] Among them, Figure 11 is Figure 10 a cross-sectional view of the array substrate at D-D' provided by Figure 12 is Figure 10 a top view of the transparent shielding electrode of the array substrate provided by Figure 13 is Figure 10 a top view of the pixel electrode layer of the array substrate provided by Figure 10 A top view of the first metal layer of the array substrate provided by Figure 6 can be referred to Figure 10 A top view of the second metal layer of the array substrate provided by Figure 7 .

[0066] In the present application, please refer to Figures 4 - 5 , the array substrate 100 further includes an inorganic film layer or an organic film layer between the metal layers to insulate adjacent metal layers. For example, the array substrate 100 further includes a gate insulating layer 181, a passivation layer 182, a color resist layer 183, a planarization layer 184, etc. Among them, the gate insulating layer 181 is located between the second metal layer 160 and the first metal layer 120; the passivation layer 182 is located between the first metal layer 120 and the transparent shielding electrode 130; the color resist layer 183 is located between the passivation layer 182 and the transparent shielding electrode 130, and the color resist layer 183 may include red color groups, green color groups, and blue color groups arranged in an array; the planarization layer 184 is located between the transparent shielding electrode 130 and the pixel electrode layer 140.

[0067] Among them, the first via 151 sequentially penetrates the planarization layer 184, the color resist layer 183, and the passivation layer 182 in the thickness direction of the substrate 110; the second via 152 penetrates the planarization layer 184 in the thickness direction of the substrate 110; the third via 153 and the fourth via 154 both sequentially penetrate the planarization layer 184, the color resist layer 183, and the passivation layer 182 in the thickness direction of the substrate 110; therefore, in the thickness direction of the substrate 110, the depths of the first via 151, the third via 153, and the fourth via 154 are greater than the depth of the second via 152.

[0068] It should be noted that in the present application, other common film layers in the art may also be included between the metal layers of the array substrate 100, which are not limited herein.

[0069] The present application further provides a display panel 10, and the display panel 10 includes the array substrate 100 as described above.

[0070] Please refer to Figure 14 , the display panel 10 may be a liquid crystal display panel 10, and the display panel 10 includes the array substrate 100, a liquid crystal layer 300, and a counter substrate 200. The counter substrate 200 is disposed opposite to the array substrate 100, and the liquid crystal layer 300 is located between the array substrate 100 and the counter substrate 200.

[0071] The present application provides an array substrate and a display panel. The array substrate of the present application includes a first common electrode, a pixel electrode, and a transparent shielding electrode located therebetween. Among them, the pixel electrode is connected to the first common electrode through a first via hole (i.e., a deep hole), the transparent shielding electrode is connected to the pixel electrode through a second via hole (i.e., a shallow hole), the first via hole and the second via hole are separated, and the first via hole is located in the control region, and the second via hole is located in the opening region. The array substrate of the present application adopts a TSS architecture, separates the second via hole from the first via hole, and arranges the second via hole in the opening region, which can reduce the occupied space of the via holes in the control region, thereby reducing the area of the control region and increasing the opening area of the opening region, and further improving the pixel aperture ratio. Therefore, the array substrate of the present application effectively improves the problem of reduced aperture ratio caused by the large occupied space of the deep and shallow holes in the control region in the prior art in the form of half-overlapping holes.

[0072] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0073] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0074] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0075] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that, It includes a plurality of sub-pixels, and each sub-pixel includes an opening area and a control area adjacent to the opening area; The array substrate further includes: A substrate; A first metal layer disposed above the substrate, and the first metal layer includes a first common electrode; A transparent shielding electrode disposed on a side of the first metal layer away from the substrate; and A pixel electrode layer disposed on a side of the transparent shielding electrode away from the first metal layer. The pixel electrode layer includes a plurality of pixel electrodes. The pixel electrodes are connected to the first common electrode through first vias, and the transparent shielding electrode is connected to the pixel electrodes through second vias; Wherein, the first vias and the second vias are separately disposed, the first vias are located in the control area, and the second vias are located in the opening area.

2. The array substrate according to claim 1, wherein The opening area includes at least one main pixel opening area and at least one sub-pixel opening area. The pixel electrodes include at least one main pixel electrode and at least one sub-pixel electrode. The main pixel electrode is located in the main pixel opening area, and the sub-pixel electrode is located in the sub-pixel opening area; The control area is located between the main pixel opening area and the sub-pixel opening area. The second via is located in the main pixel opening area or the sub-pixel opening area and is disposed close to the control area.

3. The array substrate according to claim 2, wherein The first metal layer further includes data lines extending along a first direction; The transparent shielding electrode is at least located between the data lines and the pixel electrodes. A positive projection of the transparent shielding electrode on the substrate covers at least a part of a positive projection of the data lines on the substrate and at least a part of a positive projection of the pixel electrodes on the substrate.

4. The array substrate according to claim 3, wherein The first metal layer further includes a first source electrode and a first drain electrode. The first source electrode or the first drain electrode is connected to the pixel electrode through a third via. The third via is located in the control area and is on a side of the first via in a second direction, and the second direction intersects with the first direction.

5. The array substrate according to claim 4, wherein, The first metal layer further includes a second source electrode and a second drain electrode. The second source electrode or the second drain electrode is connected to the pixel electrode through a fourth via. The fourth via is located in the control area and is on a side of the first via in the second direction.

6. The array substrate according to claim 3, wherein The second via is located at an edge of the opening area and is disposed adjacent to the control area.

7. The array substrate according to claim 6, wherein The second via is located on a center line of the opening area along the first direction.

8. The array substrate according to claim 6, wherein The second via is located at a corner of the opening area close to the data lines.

9. The array substrate according to claim 3, wherein The array substrate further includes: A second metal layer. The second metal layer is located between the substrate and the first metal layer. The second metal layer includes scan lines and a second common electrode. The scan lines extend along a second direction, and the second common electrode is spaced apart from the scan lines, wherein the second direction intersects with the first direction; The first common electrode is located between adjacent data lines and extends along the first direction.

10. A display panel, characterized in that, An array substrate according to any one of claims 1 to 9.

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