IEEE754 standard single-precision floating-point number multiplier based on PLD

Abstract

The invention discloses an IEEE754 standard single-precision floating-point number multiplier based on PLD (programmable logic device), which belongs to the universal technical field of software of programmable logic devices, and comprises a sign bit calculation module of a product, which is used for obtaining a sign bit of the product according to an IEEE754 standard single-precision floating-point number to be multiplied input by a user; the final significant bit calculation module of the product is used for obtaining the final significant bit of the product according to the IEEE754 standard single-precision floating-point number to be multiplied input by the user; the product order calculation module is used for obtaining a product order according to the IEEE754 standard single-precision floating-point number to be multiplied input by a user; and the combined operation result module is used for outputting a multiplication result of the IEEE754 standard single-precision floating-point number to be multiplied according to the sign bit of the product, the final effective bit of the product and the order code of the product. The problems that an existing multiplier is unclear in design method, uncertain in occupied resource, poor in transportability, poor in modifiability, uncertain in reliability and the like are solved.

Description

Technical Field

[0001] The present invention belongs to the general technical field of programmable logic device software, and particularly relates to a single-precision floating-point multiplier based on the IEEE 754 standard for PLD. Background Art

[0002] Since the 1980s, the IEEE 754 floating-point arithmetic standard has become the most widely used related standard and has been adopted by many CPUs and floating-point arithmetic units. This standard stipulates four ways to represent floating-point values: single-precision (32 bits), double-precision (64 bits), extended single-precision (more than 43 bits), and extended double-precision (more than 79 bits). Compared with other precision floating-point value representation methods stipulated by the IEEE 754 standard, single-precision (32 bits) has the advantages of small memory occupation, fast calculation speed, and can save storage and transmission bandwidth, and can already meet the precision requirements of most application scenarios.

[0003] Currently, single-precision floating-point multipliers based on the IEEE 754 standard for PLD are all built into the development tools of PLD, and their design data has been encrypted. In some existing PLDs on the market, such as most CPLDs, their development tools do not even provide single-precision floating-point multipliers based on the IEEE 754 standard. This situation undoubtedly forces users to change the design scheme or choose other more expensive PLD chips.

[0004] As the difficulty faced in the implementation of PLD projects gradually increases and the engineering volume continues to grow, users have put forward more stringent requirements for the reliability, portability, modifiability, and even cost control of PLD projects. Currently, there are many problems with existing single-precision floating-point multipliers based on the IEEE 754 standard for PLD: their design methods lack clarity, resource occupation is difficult to determine, and they perform poorly in terms of portability, modifiability, and verifiability, thus making it difficult to effectively prove their reliability. Especially in the fields of civil aviation and integrated circuits in China, there are extremely high requirements for the reliability and safety of related devices and technologies, and sufficient verification has become a necessary condition to ensure that they meet the actual application requirements. Summary of the Invention

[0005] In view of the above deficiencies in the prior art, a single-precision floating-point multiplier based on the IEEE 754 standard for PLD provided by the present invention solves the problems of existing multipliers, such as unclear design methods, uncertain resource occupation, poor portability, poor modifiability, poor verifiability, and uncertain reliability.

[0006] To achieve the above invention purpose, the technical solution adopted by the present invention is: a single-precision floating-point multiplier based on the IEEE 754 standard for PLD, comprising: Sign bit calculation module of the product: Obtain the sign bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Final significant bit calculation module of the product: Obtain the final significant bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Exponent calculation module of the product: Obtain the exponent of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Combined operation result module: Output the multiplication result of the IEEE 754 standard single-precision floating-point numbers to be multiplied according to the sign bit of the product, the final significant bit of the product, and the exponent of the product.

[0007] Furthermore, the specific calculation process of the sign bit calculation module of the product is as follows: respectively take the sign bits of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied for exclusive OR operation. If the exclusive OR result is 1, the sign bit of the product is 1; if the exclusive OR result is 0, the sign bit of the product is 0.

[0008] Furthermore, the specific calculation process of the final significant bit calculation module of the product is as follows: split the lower 24 bits of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied into multiple segments respectively, multiply each segment of one number with each segment of the other number respectively and perform shift and addition calculations to obtain the final significant bit of the product.

[0009] Furthermore, the multiplication of each segment of one number with each segment of the other number respectively is specifically as follows: continue to split one segment of a number into multiple small segments, and multiply and perform shift and addition calculations with multiple small segments of the other number.

[0010] Furthermore, the specific calculation process of the exponent calculation module of the product is as follows: respectively take the exponent parts of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied, regard them as unsigned binary numbers and add them to obtain the original exponent, subtract 8'd127 from the original exponent for exponent correction, and then add the 35th bit of the final significant bit of the product to the corrected exponent to obtain the exponent of the product.

[0011] Furthermore, the multiplier can be replicated into multiple paths to simultaneously complete the multiplication operations of multiple pairs of 2 IEEE 754 standard single-precision floating-point numbers, and output the multiplication results of each path respectively, and the operation results of each path do not affect each other.

[0012] Furthermore, after completing one multiplication operation, the multiplier returns to the sign bit calculation module of the product again to perform multiplication operations in a loop, and the multiplication results of each loop do not affect each other.

[0013] The beneficial effects of the present invention are: (1) Significantly reduced resource occupancy. The present invention only calls the LUT resources in the PLD and deeply optimizes the logic resources. Through experimental verification, taking the IEEE 754 standard single-precision floating-point multiplier provided by the Vivado development tool as a reference (also only using the LUT resources in the PLD), in the synthesis stage of a single multiplier, the LUT resource occupancy of the present invention is reduced by 45.7%; after placement and routing, the LUT resource occupancy is reduced by 40%.

[0014] (2) Excellent portability. The present invention is completely designed using Verilog HDL. As a hardware description language that can be recognized by various PLD and ASIC development tools, Verilog HDL endows the present invention with the ability to be widely applied, mutually transplanted and replicated in all PLDs and ASICs. In addition, the internal modules of the present invention can be used independently or partially as needed. For modules that are not required, they can be directly removed.

[0015] (3) High reliability. The present invention is completely designed using Verilog HDL. Through functional simulation, it shows that when randomly inputting IEEE 754 standard single-precision floating-point numbers, the multiplication results output by the present invention are all accurate and error-free, and the code coverage rate (statements, branches, conditions, expressions) can reach 100%, without redundant code, which effectively guarantees the reliability. Description of the Drawings

[0016] Figure 1 It is a flowchart of an IEEE 754 standard single-precision floating-point multiplier based on a PLD. Specific Embodiments

[0017] The following further describes the present invention with reference to the drawings and specific embodiments.

[0018] As Figure 1 shown, an IEEE 754 standard single-precision floating-point multiplier based on a PLD includes: Sign bit calculation module of the product: Obtain the sign bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Final significant bit calculation module of the product: Obtain the final significant bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Exponent calculation module of the product: Obtain the exponent of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Combined operation result module: Output the multiplication result of the IEEE 754 standard single-precision floating-point numbers to be multiplied according to the sign bit of the product, the final significant bit of the product, and the exponent of the product.

[0019] In an embodiment of the present invention, taking the example that a user inputs two IEEE 754 standard single-precision floating-point numbers to be multiplied and wants to obtain the multiplication result, the specific implementation is as follows: The specific calculation process of the sign bit calculation module of the product is: respectively take the sign bits of the two IEEE 754 standard single-precision floating-point numbers to be multiplied for exclusive OR operation. If the exclusive OR result is 1, the sign bit of the product is 1; if the exclusive OR result is 0, the sign bit of the product is 0.

[0020] In this embodiment, after the user inputs two IEEE 754 standard single-precision floating-point numbers to be multiplied (hereinafter referred to as floating-point number A and floating-point number B), the sign bit calculation module respectively takes the sign bits (the 32nd bit) of floating-point number A and floating-point number B for exclusive OR operation. If the exclusive OR result is 1, it means that among floating-point numbers A and B, one is negative and the other is non-negative, and the multiplication result is obtained: the sign bit of the product is 1. If the exclusive OR result is 0, it means that floating-point numbers A and B are both negative or non-negative, and the sign bit of the product is 0.

[0021] This application uses exclusive OR operation to determine the sign bit of the product. The principle is that the sign bit of a floating-point number is only determined by the sign bits of the multiplicand and the multiplier. For an IEEE 754 standard single-precision floating-point number, the sign bit is 1 bit, 0 represents a positive number, and 1 represents a negative number. According to the exclusive OR operation rule (the same is 0, different is 1), when performing exclusive OR operation on the sign bits of the multiplicand and the multiplier, if the result is 0, the product is a positive number; if the result is 1, the product is a negative number. For example, if the sign bit of the multiplicand is 0 (positive number) and the sign bit of the multiplier is 1 (negative number), 0⊕1 = 1, so the product is a negative number.

[0022] The specific calculation process of the final significant bit calculation module of the product is: split the lower 24 bits of the two IEEE 754 standard single-precision floating-point numbers to be multiplied into multiple segments, and multiply and shift and add each segment of one number with each segment of the other number respectively to obtain the final significant bit of the product.

[0023] Multiplying each segment of one number with each segment of the other number respectively specifically means: further split one segment of a number into multiple small segments, and multiply and shift and add these small segments with multiple small segments of the other number.

[0024] In this embodiment, the final significant digit calculation module of the product respectively takes the 24th to 1st bits of the floating-point number A and the floating-point number B, and regards them as unsigned binary numbers. The floating-point numbers A and B are respectively split into C, D, E, and F of 12 bits each. The multiplication result of the floating-point numbers A and B is the shift addition of C×F, D×F, C×E, and D×E. C, D, E, and F can be respectively split into C1, C2, C3, C4, C5, C6, D1, D2, D3, D4, D5, D6, E1, E2, E3, E4, E5, E6, F1, F2, F3, F4, F5, and F6 of 2 bits each. The result of C×F is the shift addition of the products of C1, C2, C3, C4, C5, and C6 and F1, F2, F3, F4, F5, and F6 respectively to obtain the final significant digit of the product. The same applies to D×F, C×E, and D×E.

[0025] In this application, the lower 24 bits of the floating-point number are split into segments of every [X] bits (such splitting is based on the principle of binary multiplication, which is convenient for simplifying calculations and hardware implementation). After splitting, multiplication operations are performed on each segment respectively, which is based on the principle of the distributive law of multiplication. The results obtained by multiplication are then accumulated by means of shift addition. Specifically, according to the position weights of each segment in the original floating-point number, the multiplication results are left-shifted by the corresponding number of bits and then added together to obtain the final calculation result of the significant digits. In hardware implementation, circuit modules such as shift registers can be used to efficiently complete this operation.

[0026] The specific calculation process of the exponent calculation module of the product is as follows: respectively take the exponent parts of the two IEEE 754 standard single-precision floating-point numbers to be multiplied, regard them as unsigned binary numbers and add them to obtain the original exponent, subtract 8'd127 from the original exponent for exponent correction, and then add the 35th bit of the final significant digit of the product to the corrected exponent to obtain the exponent of the product.

[0027] In this embodiment, the exponent calculation module of the product respectively takes the 31st to 23rd bits of the floating-point number A and the floating-point number B, and regards them as unsigned binary numbers. The floating-point numbers A and B are added to form the original exponent, subtract 8'd127 from the original exponent for exponent correction, and add the 35th bit of the final significant digit of the product to the corrected exponent to obtain the exponent of the product.

[0028] This application performs an addition operation on the exponents of the floating-point numbers because in floating-point multiplication, the exponent of the product is theoretically the sum of the exponents of the multiplicand and the multiplier. However, due to special bias rules and other factors in the IEEE 754 standard, the result after addition needs to be corrected. The specific correction rule is: when the result of exponent addition exceeds the range specified by the standard (overflow or underflow boundaries), it is adjusted according to the saturation value specified by the standard; at the same time, the influence of hidden bits and other factors on the exponent needs to be considered for corresponding fine-tuning to ensure the accuracy of the final exponent.

[0029] Finally, the combined operation result module splices the sign bit of the product, the final significant bit of the product, and the exponent result of the product in sequence, and the user selects the multiplied result to be output according to the need for use.

[0030] The multiplier can be replicated into multiple paths to simultaneously complete the multiplication operations of two IEEE 754 standard single-precision floating-point numbers in multiple paths, and output the multiplied results of each path respectively, and the operation results of each path do not affect each other.

[0031] After the multiplier completes one multiplication operation, it returns to the sign bit calculation module of the product and performs the multiplication operation in a loop, and the multiplied results of each loop do not affect each other.

[0032] This application supports loop calculation, and its implementation mechanism is as follows: at the hardware level, an independent loop control logic circuit is designed, which can accurately control the start and end of each loop according to the preset number of loops or calculation conditions. In each loop, the data flows through a specific path, obtains the floating-point numbers participating in the operation from the data input port, and after being processed by the sign bit, significant bit, and exponent calculation modules, the results are temporarily stored in a dedicated register. At the same time, through a clever circuit design, it is ensured that the calculation results of this loop will not interfere with the multiplied results of subsequent loops. In addition, this application has a multi-path replication function, which can replicate the calculation module into multiple paths to parallelly process the multiplication operations of multiple paths of floating-point numbers. This feature is based on the principles of time-division multiplexing and resource sharing, and greatly improves the operation efficiency without significantly increasing the hardware resources, and is applicable to scenarios that require simultaneous processing of a large number of floating-point multiplications, such as large-scale data processing, graphics rendering and other fields.

[0033] Those of ordinary skill in the art will realize that the embodiments described herein are for helping the reader understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations without departing from the essence of the present invention according to the technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the invention.

Claims

1. A PLD-based IEEE754 standard single-precision floating-point multiplier, characterized in that, Including: Product sign bit calculation module: Obtain the sign bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Final significant bit calculation module of the product: Obtain the final significant bit of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Exponent calculation module of the product: Obtain the exponent of the product according to the IEEE 754 standard single-precision floating-point numbers to be multiplied input by the user; Combined operation result module: Output the multiplication result of the IEEE 754 standard single-precision floating-point numbers to be multiplied according to the sign bit of the product, the final significant bit of the product, and the exponent of the product.

2. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 1, wherein The specific calculation process of the product sign bit calculation module is as follows: XOR the sign bits of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied respectively. If the XOR result is 1, the sign bit of the product is 1; if the XOR result is 0, the sign bit of the product is 0.

3. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 1, characterized in that, The specific calculation process of the final significant bit calculation module of the product is as follows: Split the lower 24 bits of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied into multiple segments respectively, multiply each segment of one number with each segment of the other number respectively and perform shift-and-add calculations to obtain the final significant bit of the product.

4. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 3, characterized in that, The multiplication of each segment of one number with each segment of the other number respectively is specifically as follows: Continue to split a segment of one number into multiple small segments, and multiply and perform shift-and-add calculations with multiple small segments of the other number.

5. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 1, wherein The specific calculation process of the exponent calculation module of the product is as follows: Take the exponent parts of the 2 IEEE 754 standard single-precision floating-point numbers to be multiplied respectively, regard them as unsigned binary numbers and add them to obtain the original exponent, subtract 8'd127 from the original exponent for exponent correction, and then add the 35th bit of the final significant bit of the product to the corrected exponent to obtain the exponent of the product.

6. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 1, characterized in that The multiplier can be replicated into multiple paths, simultaneously complete the multiplication operations of multiple pairs of 2 IEEE 754 standard single-precision floating-point numbers, and output the multiplication results of each path respectively, and the operation results of each path do not affect each other.

7. The IEEE 754 standard single-precision floating-point multiplier based on PLD according to claim 1, characterized in that After the multiplier completes one multiplication operation, it returns to the product sign bit calculation module again, performs multiplication operations in a loop, and the multiplication results of each loop do not affect each other.

Images