Isomorphic in-memory calculation circuit based on spin Hall device and implementation method

Abstract

The embodiment of the invention provides an isomorphic in-memory calculation circuit based on spinning Hall devices and an implementation method, the isomorphic in-memory calculation circuit based on the spinning Hall devices comprises a plurality of spinning Hall device groups which are connected in parallel, each spinning Hall device group is connected to a next-stage spinning Hall device through a switch, each spin Hall device group comprises a plurality of cascaded spin Hall devices, and each spin Hall device structurally comprises a substrate, a strong spin orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a cap layer, a protective layer and a top metal electrode which are sequentially connected from bottom to top; and the spinning Hall device is used for realizing a nonvolatile storage function and a maximum value pooling function.

Description

Technical Field

[0001] This document relates to the field of electrical technologies, and particularly to a homogeneous in-memory computing circuit based on spin Hall devices and an implementation method thereof. Background Art

[0002] With the rapid development of artificial intelligence technologies, miniaturization, lightweight, and low power consumption have become the development trends of IoT intelligent terminal hardware. Due to the memory wall problem, the traditional von Neumann computing architecture has become difficult to be compatible with intelligent chips under advanced processes. The technology of in-memory computing has emerged as the times require and has become a current research hotspot.

[0003] Multiplication-accumulation operation and maximum pooling operation are two essential operation functions for various neural networks. In the technology of in-memory computing, multiplication-accumulation is usually implemented based on a resistive crossbar structure (such as RRAM, FeRAM, PCRAM, MRAM) and combined with Kirchhoff's law. The maximum pooling function is usually implemented using a CMOS-based majority voting circuit. The hardware carriers and structures of these two functional circuits are different, so it is difficult to achieve high-density integration.

[0004] In-memory computing based on new storage technologies is a current research hotspot. The commonly used method is to use the resistance of memristors to store weight information. At the same time, the crossbar formed by them sums the branch currents through Kirchhoff's law, and then through an analog-to-digital converter, the analog quantity obtained by summation is converted into a digital quantity and enters the extreme value comparison circuit to complete the maximum pooling function. The hardware media of the two functional circuits are different, and at the same time, the mutual conversion of analog signals and digital signals is required, which is the main problem restricting the chip integration density and energy efficiency. Summary of the Invention

[0005] The purpose of the present invention is to provide a homogeneous in-memory computing circuit based on spin Hall devices and an implementation method thereof, aiming to solve the above problems in the prior art.

[0006] The present invention provides a homogeneous in-memory computing circuit based on spin Hall devices, including:

[0007] Multiple groups of parallel-connected spin Hall device groups, each group of spin Hall device groups is respectively connected to the next-level spin Hall device through a switch. Among them, each spin Hall device group includes multiple cascaded spin Hall devices. The structure of the spin Hall device is successively connected from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protective layer, and a top metal electrode. The spin Hall device is used to implement a non-volatile storage function and a maximum pooling function.

[0008] The present invention provides an implementation method of a homogeneous in-memory computing circuit based on spin Hall devices, including:

[0009] A plurality of sets of parallel-connected spin Hall device groups are provided. Each spin Hall device group includes a plurality of cascaded spin Hall devices. The structure of the spin Hall device is successively connected from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protective layer, and a top metal electrode;

[0010] Each set of spin Hall device groups is respectively connected to the next-level spin Hall device through a switch to implement a non-volatile storage function and a maximum pooling function.

[0011] By adopting the embodiment of the present invention, through the cascaded design of spin Hall devices with multi-resistance state characteristics, high-density integration of multiply-accumulate and maximum pooling circuits is achieved. Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions in one or more embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 It is a schematic diagram of a homogeneous in-memory computing circuit based on spin Hall devices according to an embodiment of the present invention;

[0014] Figure 2 It is a schematic diagram of a preferred structure of a homogeneous in-memory computing circuit based on spin Hall devices according to an embodiment of the present invention

[0015] Figure 3 It is a schematic diagram of the structure of a spin Hall device according to an embodiment of the present invention;

[0016] Figure 4 It is a schematic diagram of the components of a spin Hall device according to an embodiment of the present invention;

[0017] Figure 5 It is a schematic diagram of the input current according to an embodiment of the present invention;

[0018] Figure 6 It is a flowchart of a method for implementing a homogeneous in-memory computing circuit based on spin Hall devices according to an embodiment of the present invention. Detailed Embodiments

[0019] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will clearly and completely describe the technical solutions in one or more embodiments of this specification in conjunction with the accompanying drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, rather than all of them. Based on one or more embodiments of this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this document.

[0020] Device embodiment

[0021] According to an embodiment of the present invention, a homogeneous in-memory computing circuit based on a spin Hall device is provided. Figure 1 It is a schematic diagram of the homogeneous in-memory computing circuit based on the spin Hall device according to the embodiment of the present invention, as Figure 1 shown. The homogeneous in-memory computing circuit based on the spin Hall device according to the embodiment of the present invention specifically includes:

[0022] Multiple groups of parallel spin Hall device groups 1, and each group of spin Hall device groups 1 is respectively connected to the next-level spin Hall device 2 through switches (S1 and S2 in the figure). Among them, each spin Hall device group 1 includes multiple cascaded spin Hall devices (three cascaded spin Hall devices in the figure). The structure of the spin Hall device is sequentially connected from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protective layer, and a top metal electrode. The spin Hall device is used to implement a non-volatile storage function and a maximum pooling function.

[0023] The spin Hall device is specifically used for:

[0024] When the characteristic size of the spin Hall device is in the micron order, the magnetic ferromagnetic layer exhibits a multi-domain state. Due to its perpendicular magnetic anisotropy, when there is no external magnetic field perpendicular to the device surface, by applying an input current, a Hall voltage is generated longitudinally in the spin Hall device, and the Hall voltage is determined according to Formula 1:

[0025] VH = R(I) × I Formula 1;

[0026] where R(I) is the Hall resistance of the spin Hall device, I is the input current, and VH is the Hall voltage;

[0027] The Hall resistance exhibits a multi-resistance state. When the applied input current exceeds a certain threshold, the change of R(I) with I is linear, and R(I) has a non-volatile holding characteristic. Only when the applied input current is greater than the previous current, the value of R(I) will change, realizing the maximum pooling function and the non-volatile storage function.

[0028] When writing weights, disconnect the switches connected to the next-level spin Hall devices. In response to multiple input currents respectively applied to each spin Hall device in the group, the Hall resistances in the spin Hall devices are respectively written into specific states, and the Hall resistances are used to represent the weights in the neural network;

[0029] When performing an inference operation, close the switches of this spin Hall device group and disconnect the switches of other spin Hall device groups. In response to multiple input currents respectively applied to each spin Hall device in the group, obtain the output currents, perform multiply-accumulate operations on the output currents of each spin Hall device, input the multiply-accumulate operation results into the next-level spin Hall device, and the next-level spin Hall device writes the Hall resistance;

[0030] Other spin Hall device groups perform the above operations in sequence, input the multiply-accumulate operation results obtained by this group into the next-level spin Hall device in the same way. The next-level spin Hall device saves the Hall resistance corresponding to the maximum current among the multiply-accumulate operation results of each spin Hall device group, completes the function of maximum pooling, and outputs the pooling result in the form of Hall voltage or Hall current.

[0031] Determine the output currents of each spin Hall device according to Formula 2:

[0032] IH = I × R(I) / Rc Formula 2;

[0033] Wherein, I is the input current applied to the spin Hall device in the group, R(I) is the Hall resistance of the spin Hall device, Rc is the wire resistance in the circuit and is a fixed value, and IH represents the output current of the spin Hall device.

[0034] Perform multiply-accumulate operations on the output currents of each spin Hall device according to Formula 3:

[0035] Isum1 = IH1 + IH2 + IH3 + …… + IHn Formula 3;

[0036] Wherein, Isum1 represents the multiply-accumulate operation result, IH1, ……, IHn represent the output currents of each spin Hall device, and n represents the number of spin Hall devices in the spin Hall device group.

[0037] The following combines the figures to illustrate the above technical solutions of the embodiments of the present invention by way of example.

[0038] In view of the complexity of the heterogeneous architecture of the in-memory computing circuit based on the memory, the embodiments of the present invention propose a homogeneous in-memory computing circuit based on spin Hall devices. Through the cascade design of spin Hall devices with multi-resistance state characteristics, high-density integration of multiply-accumulate and maximum pooling circuits is realized. The structure of the spin Hall device is as Figure 3As shown, the components of the spin Hall device are as follows Figure 4 As shown, the top metal electrode generally uses metals such as Al and Au. The protective layer uses a conductive material with oxidation resistance, generally TiN, TaN, etc. The capping layer uses a heavy metal material, generally Ta or Ru with a thickness exceeding 20 nm. The barrier layer uses a metal oxide with a body-centered cubic lattice structure, generally MgO with a thickness of 1 nm to 2 nm. The magnetic ferromagnetic layer uses a CoFeB ferromagnetic alloy with perpendicular magnetic anisotropy, generally 0.8 nm to 1.5 nm; the strong spin-orbit coupling layer generally uses a heavy metal such as W, Ta / W alloy, topological insulator, etc. with a thickness of 3 nm to 5 nm;

[0039] The working principle of the spin Hall device is as follows: When the characteristic size of the spin Hall device is in the micron range, the magnetic ferromagnetic layer exhibits a multi-domain state. Due to its perpendicular magnetic anisotropy, the device has an anomalous Hall effect, that is, in the absence of an external magnetic field perpendicular to the device surface, by applying a current I as shown in Figure 5 As shown, a Hall voltage can be generated longitudinally in the device. The Hall voltage VH = R(I) × I, where R(I) is the Hall resistance of the device, which is related to its own material properties. For a spin Hall device with a multi-domain state, its Hall resistance exhibits a multi-resistance state. When the applied current exceeds a certain threshold, the change of R(I) with I is linear, and R(I) has a non-volatile retention characteristic. Only when the applied current is greater than the previous current, the value of R(I) will change. Utilizing this characteristic, the spin Hall device can achieve the maximum pooling function and the non-volatile storage function.

[0040] Based on the above characteristics of the spin Hall device, the present invention proposes a circuit structure schematic diagram as shown in Figure 1 As shown, in this example, the circuit structure is as shown in Figure 2 As shown, taking three spin Hall devices as a group, Figure 2There are two groups. Taking the first group of Hall devices as an example, the working principle of the circuit is as follows: First is the weight writing. Currents I1, I2, and I3 are respectively applied to three devices. All three currents are in the linear region of the spin Hall devices. During this operation process, switches S1 and S2 are disconnected. Therefore, the Hall resistances of the three spin Hall devices are respectively written into specific states, and the Hall resistances at this time represent the weights in the neural network. When performing the inference operation, switch S1 is closed and S2 is disconnected. Currents I1, I2, and I3 are respectively input to the three spin Hall devices. All three currents are smaller than the currents during weight writing. At this time, IH1 = I1×R(I1) / Rc, IH2 = I2×R(I2) / Rc, IH3 = I3×R(I3) / Rc, where Rc is the wire resistance in the circuit and is a fixed value. At this time, Isum1 = IH1 + IH2 + IH3, that is, the multiply-accumulate operation is completed. Isum1 enters the next-level spin Hall device, and the Hall resistance is written to it, and this state will be stored in the spin Hall device. Thereafter, the second group of spin Hall devices performs a similar operation. The difference is that the intensity of the current can be different (depending on whether the data written into the neural network is the same). Therefore, Isum2 follows the operation timing of Isum1 and enters the next-level spin Hall device. At this time, as described above, the Hall resistance of the next-level spin Hall device will save the Hall resistance corresponding to the largest current among the two currents. Since this functional relationship is linear, the next-level Hall resistance completes the function of maximum pooling, and the pooling result will be output in the form of Hall voltage or Hall current.

[0041] By adopting the embodiment of the present invention, through the cascade design of spin Hall devices with multi-resistance state characteristics, the high-density integration of multiply-accumulate and maximum pooling circuits is realized.

[0042] Method embodiment

[0043] According to the embodiment of the present invention, a method for implementing a homogeneous in-memory computing circuit based on spin Hall devices is provided. Figure 6 It is a flowchart of the method for implementing a homogeneous in-memory computing circuit based on spin Hall devices according to the embodiment of the present invention, as Figure 6 shown. The method for implementing a homogeneous in-memory computing circuit based on spin Hall devices according to the embodiment of the present invention specifically includes:

[0044] Step S601, set multiple groups of parallel-connected spin Hall device groups, where each spin Hall device group includes multiple cascaded spin Hall devices. The structure of the spin Hall device is sequentially connected from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protection layer, and a top metal electrode;

[0045] Step S602: Connect each group of spin Hall devices to the next-level spin Hall devices through switches respectively to achieve non-volatile storage function and maximum pooling function.

[0046] Among them, achieving the non-volatile storage function and the maximum pooling function specifically includes:

[0047] When the characteristic size of the spin Hall device is in the micron order, the magnetic ferromagnetic layer exhibits a multi-domain state. Due to its perpendicular magnetic anisotropy, when there is no external magnetic field perpendicular to the device surface, by applying an input current, a Hall voltage is generated longitudinally in the spin Hall device, and the Hall voltage is determined according to Formula 1:

[0048] VH = R(I) × I Formula 1;

[0049] Wherein, R(I) is the Hall resistance of the spin Hall device, I is the input current, and VH is the Hall voltage;

[0050] The Hall resistance exhibits a multi-resistance state. When the applied input current exceeds a certain threshold, the change of R(I) with I is linear, and R(I) has a non-volatile retention characteristic. Only when the applied input current is greater than the previous current, the value of R(I) will change, realizing the maximum pooling function and the non-volatile storage function.

[0051] During weight writing, disconnect the switches connected to the next-level spin Hall devices. In response to multiple input currents respectively applied to each spin Hall device in the group, the Hall resistance in the spin Hall device is respectively written into a specific state, and the Hall resistance is used to represent the weights in the neural network;

[0052] During the inference operation, close the switches of the current spin Hall device group and disconnect the switches of other spin Hall device groups. In response to multiple input currents respectively applied to each spin Hall device in the group, an output current is obtained. Perform a multiply-accumulate operation on the output currents of each spin Hall device, and input the result of the multiply-accumulate operation into the next-level spin Hall device, and the next-level spin Hall device writes the Hall resistance;

[0053] Other spin Hall device groups perform the above operations in sequence, and also input the result of the multiply-accumulate operation obtained by this group into the next-level spin Hall device. The next-level spin Hall device saves the Hall resistance corresponding to the maximum current in the results of the multiply-accumulate operations of each spin Hall device group, completes the maximum pooling function, and outputs the pooling result in the form of Hall voltage or Hall current.

[0054] Among them, obtaining the output current specifically includes:

[0055] Determine the output current of each spin Hall device according to Formula 2:

[0056] The formula 2: IH = I×R(I) / Rc;

[0057] Wherein, I is the input current applied to the spin Hall device in the group, R(I) is the Hall resistance of the spin Hall device, Rc is the wire resistance in the circuit, which is a fixed value, and IH represents the output current of the spin Hall device.

[0058] The multiplication and accumulation operation on the output currents of each spin Hall device specifically includes:

[0059] Perform the multiplication and accumulation operation on the output currents of each spin Hall device according to formula 3:

[0060] The formula 3: Isum1 = IH1 + IH2 + IH3 + …… + IHn;

[0061] Wherein, Isum1 represents the result of the multiplication and accumulation operation, IH1, ……, IHn represent the output currents of each spin Hall device, and n represents the number of spin Hall devices in the spin Hall device group.

[0062] The embodiment of the present invention is a method embodiment corresponding to the above device embodiment. The specific operations of each processing step can be understood with reference to the description of the device embodiment, and will not be elaborated here.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A homogeneous in-memory computing circuit based on a spin Hall device, characterized in that Including: Multiple groups of parallel-connected spin Hall device groups, each group of spin Hall device groups is respectively connected to the next-level spin Hall device through a switch. Among them, each spin Hall device group includes multiple cascaded spin Hall devices. The structure of the spin Hall device is successively connected from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protective layer, and a top metal electrode. The spin Hall device is used to implement a non-volatile storage function and a maximum pooling function.

2. The homogeneous in-memory computing circuit based on the spin Hall device according to claim 1, wherein The spin Hall device is specifically used for: When the characteristic size of the spin Hall device is in the micron order of magnitude, the magnetic ferromagnetic layer exhibits a multi-domain state. Due to its perpendicular magnetic anisotropy, when there is no external magnetic field perpendicular to the device surface, by applying an input current, a Hall voltage is generated longitudinally in the spin Hall device, and the Hall voltage is determined according to Formula 1: VH = R(I) × I Formula 1; Wherein, R(I) is the Hall resistance of the spin Hall device, I is the input current, and VH is the Hall voltage; The Hall resistance exhibits a multi-resistance state. When the applied input current exceeds a certain threshold, the change of R(I) with I is linear, and R(I) has a non-volatile retention characteristic. Only when the applied input current is greater than the previous current, the value of R(I) will change, realizing the maximum pooling function and the non-volatile storage function.

3. The isomorphic in-memory computing circuit based on the spin Hall device according to claim 1, characterized in that, The spin Hall device is specifically used for: During weight writing, disconnect the switch connected to the next-level spin Hall device. In response to multiple input currents respectively applied to each spin Hall device in the group, the Hall resistance in the spin Hall device is respectively written into a specific state, and the Hall resistance is used to represent the weights in the neural network; During the inference operation, close the switch of this spin Hall device group, disconnect the switches of other spin Hall device groups. In response to multiple input currents respectively applied to each spin Hall device in the group, an output current is obtained. Perform a multiply-accumulate operation on the output currents of each spin Hall device, input the multiply-accumulate operation result into the next-level spin Hall device, and the next-level spin Hall device writes the Hall resistance; Other spin Hall device groups perform the above operations in sequence, and also input the multiply-accumulate operation result obtained by this group into the next-level spin Hall device. The next-level spin Hall device saves the Hall resistance corresponding to the maximum current in the multiply-accumulate operation results of each spin Hall device group, completes the maximum pooling function, and outputs the pooling result in the form of a Hall voltage or a Hall current.

4. The homogeneous in-memory computing circuit based on the spin Hall device according to claim 3, characterized in that, The spin Hall device is specifically used for: Determine the output current of each spin Hall device according to Formula 2: IH = I × R(I) / Rc Formula 2; Wherein, I is the input current applied to the spin Hall device in the group, R(I) is the Hall resistance of the spin Hall device, Rc is the wire resistance in the circuit, which is a fixed value, and IH represents the output current of the spin Hall device.

5. The homogeneous in-memory computing circuit based on a spin Hall device according to claim 4, wherein The spin Hall device is specifically used for: Perform a multiply-accumulate operation on the output currents of each spin Hall device according to Formula 3: Isum1 = IH1 + IH2 + IH3 + …… + IHn Formula 3; Among them, Isum1 represents the result of the multiply-accumulate operation, IH1, ……, IHn represent the output currents of each spin Hall device, and n represents the number of spin Hall devices in the spin Hall device group.

6. A method for implementing a homogeneous in-memory computing circuit based on a spin Hall device, characterized in that, It includes the following processing: Set multiple groups of parallel spin Hall device groups. Among them, each spin Hall device group includes multiple cascaded spin Hall devices. The structure of the spin Hall device is connected in sequence from bottom to top: a substrate, a strong spin-orbit coupling layer, a magnetic ferromagnetic layer, a barrier layer, a capping layer, a protective layer, and a top metal electrode; Connect each group of spin Hall device groups to the next-level spin Hall device through switches respectively to implement the non-volatile storage function and the maximum pooling function.

7. The method according to claim 6, wherein Implementing the non-volatile storage function and the maximum pooling function specifically includes: When the characteristic size of the spin Hall device is in the micron order of magnitude, the magnetic ferromagnetic layer shows a multi-domain state. Due to its perpendicular magnetic anisotropy, when there is no external magnetic field perpendicular to the device surface, by applying an input current, a Hall voltage is generated longitudinally in the spin Hall device, and the Hall voltage is determined according to Formula 1: VH = R(I) × I Formula 1; Among them, R(I) is the Hall resistance of the spin Hall device, I is the input current, and VH is the Hall voltage; The Hall resistance shows a multi-resistance state. When the applied input current exceeds a certain threshold, the change of R(I) with I is linear, and R(I) has a non-volatile retention characteristic. Only when the applied input current is greater than the previous current, the value of R(I) will change, realizing the maximum pooling function and the non-volatile storage function.

8. The method according to claim 7, characterized in that Implementing the non-volatile storage function and the maximum pooling function specifically includes: During weight writing, disconnect the switch connected to the next-level spin Hall device. In response to multiple input currents respectively applied to each spin Hall device in the group, the Hall resistance in the spin Hall device is written into a specific state respectively, and the Hall resistance is used to represent the weights in the neural network; During the inference operation, close the switch of this spin Hall device group and disconnect the switches of other spin Hall device groups. In response to multiple input currents respectively applied to each spin Hall device in the group, obtain the output current, perform a multiply-accumulate operation on the output currents of each spin Hall device, input the result of the multiply-accumulate operation into the next-level spin Hall device, and the next-level spin Hall device writes the Hall resistance; Other spin Hall device groups perform the above operations in sequence, and input the result of the multiply-accumulate operation obtained by this group into the next-level spin Hall device as well. The next-level spin Hall device saves the Hall resistance corresponding to the maximum current in the multiply-accumulate operation results of each spin Hall device group, completes the maximum pooling function, and outputs the pooling result in the form of Hall voltage or Hall current.

9. The method according to claim 8, wherein Obtaining the output current specifically includes: Determine the output current of each spin Hall device according to Formula 2: IH = I × R(I) / Rc Formula 2; Among them, I is the input current applied to the spin Hall device in the group, R(I) is the Hall resistance of the spin Hall device, Rc is the wire resistance in the circuit, which is a fixed value, and IH represents the output current of the spin Hall device.

10. The method according to claim 9, wherein The multiplication and accumulation operation on the output currents of each spin Hall device specifically includes: Performing the multiplication and accumulation operation on the output currents of each spin Hall device according to Equation 3: Isum1 = IH1 + IH2 + IH3 + …… + IHn Equation 3; Among them, Isum1 represents the result of the multiplication and accumulation operation, IH1, ……, IHn represent the output currents of each spin Hall device, and n represents the number of spin Hall devices in the spin Hall device group.

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