Preparation method of bonded wafer

Abstract

The invention provides a preparation method of a bonded wafer, which comprises the following steps of: forming a first oxide layer with a first thickness on one surface of a device wafer; a second oxide layer is formed on the surface of the defect enrichment layer, a third oxide layer is formed on the back face of the supporting wafer, the second oxide layer has a third thickness, and the third oxide layer has a fourth thickness; bonding the first oxide layer towards the third oxide layer to form a bonded wafer; carrying out stripping treatment on the bonding wafer; the third oxide layer is formed on the back surface of the support wafer, so that the stress on the back surface of the support wafer can be increased, and the stress generated by the third oxide layer can be mutually counteracted with the stress generated in the forming process of the defect enrichment layer, so that the warping and distortion deformation of the support wafer are reduced; therefore, the problem that the surface of the supporting wafer is scratched due to deformation in subsequent stripping treatment is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method for preparing a bonded wafer. Background Art

[0002] Silicon on insulator (SOI) technology has currently become the mainstream product in most fields of electronic materials. The core feature of this special silicon-based semiconductor manufacturing technology is to form a thin top layer of silicon on an insulator. This structure enables SOI devices to perform excellently in many aspects, such as low power consumption, radiation resistance, high speed, etc. In the process of preparing a bonded wafer, after the device wafer and the support wafer are bonded, a peeling process is usually required. Currently, in the peeling process, before the device wafer and the support wafer are bonded, hydrogen ions are first implanted into the device wafer to form an ion implantation layer, and then the device wafer and the support wafer are bonded. After that, peeling is performed at the ion implantation layer through heat treatment to form an SOI wafer. However, in the current method for preparing a bonded wafer, the hydrogen ions implanted after heat treatment aggregate to form defects such as bubbles and cracks, which will cause the peeling of the entire surface silicon layer of the device wafer. During this process, due to the close distance between the device wafer and the support wafer, contact scratches are generated on the surfaces of the device wafer and the support wafer. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for preparing a bonded wafer to solve the problem of surface scratching during the peeling process of the bonded wafer.

[0004] To solve the above technical problems, the present invention provides a method for preparing a bonded wafer, including:

[0005] Providing a device wafer and a support wafer, and the support wafer has a front surface and a back surface which are oppositely arranged;

[0006] Forming a first oxide layer on one surface of the device wafer, and the first oxide layer has a first thickness;

[0007] Forming a defect enrichment layer on the front surface of the support wafer, and the defect enrichment layer has a second thickness;

[0008] Forming a second oxide layer on the surface of the defect enrichment layer, and forming a third oxide layer on the back surface of the support wafer. The second oxide layer has a third thickness, and the third oxide layer has a fourth thickness;

[0009] Bonding the first oxide layer facing the third oxide layer to form a bonded wafer;

[0010] Performing a peeling process on the bonded wafer;

[0011] Among them, the first thickness, the second thickness, the third thickness, and the fourth thickness satisfy the following conditions:

[0012] The difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold; and / or

[0013] The second thickness is within a set range.

[0014] Optionally, in the method for preparing the bonded wafers, the preset threshold is greater than or equal to -0.4 μm and less than or equal to 0.4 μm.

[0015] Optionally, in the method for preparing the bonded wafers, the set range of the second thickness is less than 2 μm and greater than 0 μm.

[0016] Optionally, in the method for preparing the bonded wafers, the method for forming the defect enrichment layer on the front surface of the support wafer includes:

[0017] Adopting an epitaxial chemical vapor deposition process, and maintaining a first preset time under a first epitaxial temperature and a first epitaxial process gas condition to form an initial defect enrichment layer on the front surface of the support wafer;

[0018] Raising the temperature of the epitaxial chemical vapor deposition process from the first epitaxial temperature to a second epitaxial temperature, and maintaining a second preset time under a second epitaxial process gas condition to increase the thickness of the initial defect enrichment layer to the second thickness to form the defect enrichment layer.

[0019] Optionally, in the method for preparing the bonded wafers, the first epitaxial temperature is 400°C to 700°C, the second epitaxial temperature is 800°C to 1100°C, the first preset time is less than or equal to 3 min, the second preset time is less than or equal to 8 min, and both the first epitaxial process gas and the second epitaxial process gas include silane.

[0020] Optionally, in the method for preparing the bonded wafers, the method for forming the first oxide layer includes:

[0021] Performing pretreatment on the device wafer using a first oxidation temperature and a first process gas;

[0022] Performing a first thermal oxidation process to form the first oxide layer under a second oxidation temperature and a second process gas condition, where the second oxidation temperature is greater than the first oxidation temperature.

[0023] Optionally, in the method for preparing the bonded wafers, the first oxidation temperature is 300°C to 500°C, and the first process gas includes nitrogen or argon.

[0024] Optionally, in the method for preparing the bonded wafer, the second oxidation temperature is 850°C to 1050°C, and the second oxidation process gas includes hydrogen and oxygen.

[0025] Optionally, in the method for preparing the bonded wafer, the method for forming the second oxide layer and the third oxide layer includes:

[0026] Performing pretreatment on the support wafer using a first oxidation temperature and a first process gas;

[0027] Performing a second thermal oxidation process to form the second oxide layer and the third oxide layer under the conditions of the second oxidation temperature and the second process gas, and the process time of the second thermal oxidation process is different from that of the first thermal oxidation process.

[0028] Optionally, in the method for preparing the bonded wafer, the process time of the first thermal oxidation process is 30 min to 60 min, and the process time of the second thermal oxidation process is 140 min to 170 min.

[0029] In the method for preparing the bonded wafer provided by the present invention, a first oxide layer is first formed on one surface of the device wafer, and the first oxide layer has a first thickness; then, a second oxide layer is formed on the surface of the defect enrichment layer, and a third oxide layer is formed on the back surface of the support wafer, the second oxide layer has a third thickness, and the third oxide layer has a fourth thickness; then, the first oxide layer is bonded to face the third oxide layer to form a bonded wafer; and the bonded wafer is subjected to a peeling process; wherein, the first thickness, the second thickness, the third thickness, and the fourth thickness satisfy the following conditions: the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold; and / or the second thickness is within a set range. Since the third oxide layer is formed on the back surface of the support wafer, the stress on the back surface of the support wafer can be increased, so the stress generated by the third oxide layer can cancel out the stress generated during the formation of the defect enrichment layer, thereby reducing the warping and twisting deformation of the support wafer, and further reducing the scratching problem of the surface of the bonded wafer caused by deformation during the subsequent peeling process. In addition, the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold. After the bonding is completed subsequently, the superposition value of the bending of the bonded wafer caused by the thickness difference between the third oxide layer and the total thickness of the first oxide layer and the second oxide layer and the bending of the bonded wafer caused by the stress of the defect enrichment layer is less than 50 μm, thereby further reducing the scratching problem of the wafer surface. When the second thickness is within the set range, the defect occurrence ratio can be reduced. Description of the Drawings

[0030] Figure 1 is a schematic flow chart of the method for preparing the bonded wafer provided by the embodiment of the present invention;

[0031] Figures 2 to 5 It is a schematic structural diagram of a device wafer and a support wafer formed in the method for preparing a bonded wafer provided by an embodiment of the present invention;

[0032] Figure 6 It is a schematic diagram showing the relationship between the thicknesses of different oxide layers and the warpage and curvature of the wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention;

[0033] Figure 7 It is a schematic diagram showing the relationship between different thicknesses of a defect enrichment layer and the warpage and curvature of the wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention;

[0034] Figures 8 to 10 It is a schematic structural diagram after bonding the support wafer and the device wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention;

[0035] Among them, the reference numerals are explained as follows:

[0036] 100 - device wafer; 110 - first oxide layer;

[0037] 200 - support wafer; 210 - defect enrichment layer; 220 - second oxide layer; 230 - third oxide layer. Detailed implementation manners

[0038] The following further elaborates on the method for preparing a bonded wafer proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0039] Figure 1 It is a schematic flow diagram of the method for preparing a bonded wafer provided by an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for preparing a bonded wafer, including:

[0040] Step S1: Provide a device wafer and a support wafer, and the support wafer has a front surface and a back surface that are oppositely arranged;

[0041] Step S2: Form a first oxide layer on one surface of the device wafer, and the first oxide layer has a first thickness;

[0042] Step S3: Form a defect enrichment layer on the front surface of the support wafer, and the defect enrichment layer has a second thickness;

[0043] Step S4: Form a second oxide layer on the surface of the defect enrichment layer, and form a third oxide layer on the back surface of the support wafer. The second oxide layer has a third thickness, and the third oxide layer has a fourth thickness;

[0044] Step S5: Bond the first oxide layer facing the third oxide layer to form a bonded wafer;

[0045] Step S6: Perform a peeling process on the bonded wafer;

[0046] Wherein, the first thickness, the second thickness, the third thickness, and the fourth thickness satisfy the following conditions:

[0047] The difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold; and / or

[0048] The second thickness is within a set range.

[0049] Figures 2 to 5 FIG. is a schematic structural diagram of a device wafer and a support wafer formed in the method for preparing a bonded wafer provided by an embodiment of the present invention; Figure 6 FIG. is a schematic diagram showing the relationship between the thicknesses of different oxide layers and the warpage and curvature of a wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention; Figure 7 FIG. is a schematic diagram showing the relationship between different thicknesses of a defect enrichment layer and the warpage and curvature of a wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention; Figures 8 to 10 FIG. is a schematic structural diagram after bonding a support wafer and a device wafer in the method for preparing a bonded wafer provided by an embodiment of the present invention; The following will be combined with FIGS. 2 to Figure 10 The method for preparing the bonded wafer provided by this embodiment will be described in more detail.

[0050] First, referring to Figure 2 and Figure 3 shown, perform step S1 to provide a device wafer 100 and a support wafer 200, and the support wafer 200 has a front surface and a back surface disposed opposite to each other.

[0051] Wherein, the carrier wafer is mainly used to support or carry the device wafer 100, and the material of the device wafer 100 is the same as the material of the support wafer 200. For example, the material of the device wafer 100 and the support wafer 200 is both silicon.

[0052] Then, perform step S2 to form a first oxide layer 110 on one surface of the device wafer 100, and the first oxide layer 110 has a first thickness.

[0053] Specifically, the method for forming the first oxide layer 110 on one surface of the device wafer 100 includes: pretreating the device wafer 100 with a first oxidation temperature and a first process gas; wherein, the first oxidation temperature is 300°C to 500°C; the first process gas includes nitrogen or argon; the process time of the first thermal oxidation process is 40 min to 50 min.

[0054] Then, perform the first thermal oxidation process to form the first oxide layer 110 under the conditions of a second oxidation temperature and a second process gas. The second oxidation temperature is greater than the first oxidation temperature, that is, the first thermal oxidation process is used to form the first oxide layer 110. Wherein, the process time of the first thermal oxidation process is 40 min to 50 min, so that the thickness of the oxide layer is 90 nm to 100 nm.

[0055] Exemplarily, the first thermal oxidation process can be a furnace tube process. That is, when forming the first oxide layer 110, place the device wafer 100 in the annealing chamber of a high-temperature furnace tube, raise the temperature in the annealing chamber from the first oxidation temperature to the second oxidation temperature, and use the second process gas to form the first oxide layer 110. Wherein, the second oxidation temperature is 850°C to 1050°C, such as 900°C, 1000°C or 1020°C; the second oxidation process gas includes hydrogen and oxygen.

[0056] In this embodiment, the first oxide layer 110 covers one surface of the device wafer 100, and the material of the first oxide layer 110 can be silicon oxide.

[0057] Next, as Figure 4 shown, perform step S3 to form a defect enrichment layer 210 on the front surface of the support wafer 200. The defect enrichment layer 210 has a second thickness. Specifically, the method for forming the defect enrichment layer 210 includes: First, use the epitaxial chemical vapor deposition process and, under the conditions of a first epitaxial temperature and a first epitaxial process gas, maintain a first preset time to form an initial defect enrichment layer on the front surface of the support wafer 200. Wherein, the first epitaxial temperature is 400°C to 700°C, such as 450°C, 500°C, 600°C or 650°C, the first preset time can be less than or equal to 3 min, and the first epitaxial process gas includes silane. During this process, the initial defect enrichment layer is formed by a low-temperature and slow-growth method. The material of the initial defect enrichment layer is polysilicon, the inside of the initial defect enrichment layer is disordered, and the thickness of the initial defect enrichment layer is less than the second thickness.

[0058] Then, raise the temperature of the epitaxial chemical vapor deposition process from the first epitaxial temperature to the second epitaxial temperature, and maintain it for a second preset time under the second epitaxial process gas conditions, so that the thickness of the initial defect enrichment layer increases to a second thickness to form the defect enrichment layer 210. Wherein, the second epitaxial temperature is 800°C to 1100°C, such as 850°C, 900°C or 1000°C, the second epitaxial process gas includes silane, and the second preset time is less than or equal to 8 min. During this process, the thickness of the initial defect enrichment layer is increased to the second thickness by means of high-temperature rapid growth to form the defect enrichment layer 210.

[0059] Exemplarily, the setting range of the second thickness can be less than 2 μm and greater than 0 μm, that is, the thickness of the defect enrichment layer 210 is less than 2 μm and greater than 0 μm. If it is difficult to adjust the thicknesses of the second oxide layer and the third oxide layer, the thickness of the defect enrichment layer 210 can be reduced, thereby reducing the warpage and distortion caused by the defect enrichment layer 210, which is beneficial to reducing the scratch on the wafer surface during the subsequent peeling process. The thickness of the defect enrichment layer can be controlled by the epitaxial time, epitaxial temperature, type of gas passed during epitaxy, gas flow rate, etc.

[0060] After that, a chemical mechanical polishing process (CMP) is used to planarize the surface of the defect enrichment layer 210.

[0061] Next, step S4 is executed to form a second oxide layer 220 on the surface of the defect enrichment layer 210, and a third oxide layer 230 is formed on the back surface of the support wafer. The second oxide layer 220 has a third thickness, and the third oxide layer 230 has a fourth thickness.

[0062] In some embodiments, the first thickness, the second thickness, the third thickness, and the fourth thickness satisfy the following conditions: the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold. Among them, the thicknesses of the second oxide layer and the third oxide layer can be preset according to the first thickness, so that the difference between the thickness of the subsequently formed third oxide layer 230 and the sum of the thicknesses of the first oxide layer 110 and the second oxide layer is within a preset threshold.

[0063] Since the third oxide layer 230 is formed on the back surface of the support wafer 200, the stress on the back surface of the support wafer 200 can be increased. Therefore, the stress generated by the third oxide layer 230 can cancel out the stress generated during the formation of the defect enrichment layer 210, thereby reducing the warpage and distortion of the support wafer 200, and further reducing the scratch problem on the wafer surface of the support wafer 200 caused by deformation during the subsequent peeling process.

[0064] In addition, the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold. After subsequent bonding is completed, the superimposed value of the bonding wafer bending caused by the thickness difference between the third oxide layer 230 and the total thickness of the first oxide layer 110 and the second oxide layer 220 is less than 50 μm compared to the bonding wafer bending caused by the stress of the defect enrichment layer 210, thereby further reducing the problem of wafer surface scratching.

[0065] In this embodiment, the preset threshold is greater than -0.4 μm and less than or equal to 0.4 μm, that is, the difference between the fourth thickness and the sum of the first thickness and the third thickness is greater than or equal to -0.4 μm and less than or equal to 0.4 μm. In this way, wafer surface scratching can be further reduced.

[0066] Specifically, since stress is generated during the formation of the defect enrichment layer 210, which causes the support wafer to bend, the difference between the fourth thickness and the sum of the first thickness and the third thickness in this embodiment is greater than -0.4 μm and less than 0.4 μm, -0.4 μm < T4 - (T3 + T1) < 0.4 μm, where T4 represents the fourth thickness, T3 represents the third thickness, and T1 represents the first thickness. In this way, the stress on the back surface of the support wafer 200 can be increased, and the stress generated by the second oxide layer 220 can cancel out the stress generated during the formation of the defect enrichment layer 210, thereby reducing the warping and twisting deformation of the support wafer 200.

[0067] Furthermore, after subsequent bonding of the support wafer 200 and the device wafer 100 is completed, the superimposed value of the bonding wafer bending caused by the thickness difference between the third oxide layer 230 and the buried oxide layer (formed by the first oxide layer 110 and the third oxide layer 230) is less than 50 μm, preferably less than 40 μm.

[0068] In addition, when the difference between the fourth thickness and the sum of the first thickness and the third thickness is within the preset threshold, and the second thickness (i.e., the thickness of the defect enrichment layer) is not within the set range, that is, when the difference between the fourth thickness and the sum of the first thickness and the third thickness is greater than or equal to -0.4 μm and less than or equal to 0.4 μm, and the second thickness T2 is greater than or equal to 2 μm, the way to reduce scratching can be to modify the difference between the thickness of the third oxide layer 230 and the sum of the thicknesses of the first oxide layer 110 and the second oxide layer. Specifically, if the thickness of the defect enrichment layer (i.e., the second thickness) T2 is greater than or equal to 2 μm, then the difference between the thickness of the third oxide layer and the total thickness of the first oxide layer and the second oxide layer can be made equal to -0.4 μm. The larger the T2, the smaller the range of the difference (closer to 0), and the smaller the second thickness, the larger the selected range of the difference can be.

[0069] In some embodiments, the second thickness is within a set range, where the set range of the second thickness can be less than 2 μm and greater than 0 μm. Specifically, when it is difficult to modify the difference between the thickness of the third oxide layer 230 and the sum of the thicknesses of the first oxide layer 110 and the second oxide layer, that is, when the difference between the fourth thickness and the sum of the first thickness and the third thickness is not within the preset threshold, or when it is still difficult to reduce surface scratches after adjusting the difference between the thickness of the third oxide layer 230 and the sum of the thicknesses of the first oxide layer 110 and the second oxide layer, the thickness T2 of the defect enrichment layer can be reduced when forming the defect enrichment layer to reduce scratches. The smaller the thickness T2 of the defect enrichment layer, the fewer the surface scratches.

[0070] In some embodiments, the difference between the fourth thickness and the sum of the first thickness and the third thickness is within the preset threshold, and the second thickness is within the set range. Wherein, when forming the third oxide layer, the thickness of the third oxide layer 230 can be adjusted according to the second thickness, so as to adjust the difference between the thickness of the third oxide layer and the sum of the thickness of the first oxide layer (i.e., the first thickness) and the thickness of the second oxide layer (i.e., the third thickness), so that the superposition value of the bonding wafer bending caused by the thickness difference between the third oxide layer and the total thickness of the first oxide layer and the second oxide layer and the bonding wafer bending caused by the stress of the defect enrichment layer is less than 50 μm. Specifically, when the thickness (i.e., the second thickness) T2 of the defect enrichment layer is less than 2 microns and greater than 1 micron, the difference between the thickness of the third oxide layer and the sum of the thickness of the first oxide layer (i.e., the first thickness) and the thickness of the second oxide layer can be made less than 0.4 μm; when the thickness of the defect enrichment layer is less than or equal to 1 micron, the difference between the thickness of the third oxide layer and the sum of the thickness of the first oxide layer (i.e., the first thickness) and the thickness of the second oxide layer can be made less than 0 and greater than -0.4 μm. In this way, after the bonding is completed subsequently, the superposition value of the bonding wafer bending caused by the thickness difference between the third oxide layer and the total thickness of the first oxide layer and the second oxide layer and the bonding wafer bending caused by the stress of the defect enrichment layer is less than 50 μm, thereby further reducing the problem of wafer surface scratches.

[0071] In this embodiment, the formation methods of the second oxide layer 220 and the third oxide layer 230 include:

[0072] First, pretreat the support wafer 200 with a first oxidation temperature and a first process gas; wherein, the first oxidation temperature is 300 °C to 500 °C, and the first process gas includes nitrogen or argon.

[0073] Then, perform a second thermal oxidation process to form the second oxide layer 220 and the third oxide layer 230 under the conditions of the second oxidation temperature and the second process gas. The process time of the second thermal oxidation process is different from the time of the first thermal oxidation process.

[0074] Exemplarily, the second thermal oxidation process may be a furnace tube process. That is, when forming the second oxide layer 220 and the third oxide layer 230, the device wafer 100 and the support wafer 200 are simultaneously placed in the annealing chamber of a high-temperature furnace tube, and the temperature in the annealing chamber is raised from the first oxidation temperature to the second oxidation temperature, and a second process gas is used to form the second oxide layer 220 and the third oxide layer 230. At this time, the thickness of the second oxide layer 220 is the same as that of the third oxide layer 230. Among them, the second oxidation temperature is 850°C to 1050°C, such as 900°C, 1000°C or 1020°C; the second oxidation process gas includes hydrogen and oxygen.

[0075] In this embodiment, the process time of the second thermal oxidation process is 150 min to 160 min, so that the thicknesses of both the second oxide layer 220 and the third oxide layer 230 are 280 nm to 300 nm.

[0076] Next, step S4 is executed. As Figure 8 shown, bond the first oxide layer 110 facing the third oxide layer 230 to form a bonded wafer, that is, bond the support wafer 200 and the device wafer 100 to form a bonded wafer.

[0077] Specifically, before bonding the support wafer 200 and the device wafer 100, an ion implantation process is first performed on the device wafer 100 to form an ion implantation region (or a weakened region) in the device wafer 100. Among them, the ions used in the ion implantation process can be hydrogen ions and / or helium ions, the implantation energy can be 40 Kev to 60 kev, and the implantation dose can be, for example, 6.5E16 / m 2 .

[0078] Then, the device wafer 100 and the support wafer 200 are wet-cleaned to remove particles or metal residues on the surfaces of the device wafer 100 and the support wafer 200. Preferably, a tank cleaning machine is used for cleaning, and the cleaning solution includes hydrochloric acid, hydrogen peroxide and water.

[0079] Next, bond the first oxide layer 110 facing the third oxide layer 230 to form a bonded wafer. After forming the bonded wafer, the first oxide layer 110 and the third oxide layer 230 serve as the buried oxide layer of the bonded wafer.

[0080] After that, the bonded wafer is heat-treated. First, the bonded wafer is loaded into a boat and then sent into a horizontal furnace tube for heat treatment. A two-stage heat treatment can be adopted. The temperature of the first-stage heat treatment is between 200°C and 400°C, and the temperature is raised to 400°C to 700°C during the second-stage heat treatment. Among them, the process gas used during the heat treatment can be an inert gas, such as nitrogen (N2) or argon.

[0081] Next, step S6 is executed. As Figure 9 shown, the bonded wafer is subjected to a peeling process. Among them, after the peeling process, it is peeled and split from the ion implantation layer of the device wafer 100, that is, a part of the thickness of the device wafer 100 remains on the support wafer 200 and forms a bonded wafer with the support wafer 200.

[0082] Table 1 Correspondence table between the thickness difference between the thickness of the third oxide layer and the sum of the thicknesses of the first and second oxide layers and the defect occurrence ratio

[0083]

[0084] Referring to Table 1, T0 in Table 1 represents the sum of the first thickness and the third thickness, that is, the sum of the thickness of the first oxide layer and the thickness of the second oxide layer; T1 represents the first thickness, that is, the thickness of the first oxide layer; T2 represents the second thickness, that is, the thickness of the defect enrichment layer; T3 represents the third thickness, that is, the thickness of the second oxide layer, and T4 represents the fourth thickness, that is, the thickness of the third oxide layer; among them, the sum of the thicknesses of the first oxide layer and the second oxide layer is 0.4μm, and the thickness of the defect enrichment layer is 2μm.

[0085] Referring to Figure 6 , and combining Example 1 and Example 2 in Table 1, it can be seen that the back surface of the support wafer is provided with a third oxide layer, and when the thickness difference between the thickness of the third oxide layer (T4) and the total thickness (T0) of the first oxide layer and the second oxide layer is equal to the preset threshold (greater than -0.4μm and less than 0.4μm), the wafer twist value (warp) is less than or equal to 99.4, the wafer warp value (bow) is less than or equal to 45.2, and the defect occurrence ratio is less than or equal to 0.3%. Combining Comparative Example 1 and Figure 10 it can be seen that when the thickness of the third oxide layer is 0, that is, in the case of no third oxide layer, the surface of the bonded wafer will deform, resulting in a defect occurrence ratio of 2.80%. Therefore, in this embodiment, by forming a third oxide layer on the back surface of the support wafer and the difference between the fourth thickness of the third oxide layer and the sum of the first thickness and the third thickness is within the preset threshold, the defect occurrence ratio can be reduced, and the defect (i.e., wafer surface scratch) occurrence ratio can be reduced to 0.5%, thereby reducing the problem of wafer surface scratches during the peeling process.

[0086] In addition, referring to Figure 6, the preset threshold value (greater than or equal to -0.4μm and less than or equal to 0.4μm) needs to be considered comprehensively by combining the warpage value and the twist value. An excessive twist value will increase the scratch defects in the edge area of the wafer, and an excessive warpage value will increase the scratch defects in the central area of the wafer. Since an excessive twist value of the wafer will increase the proportion of scratch defects in the edge area of the wafer, and the relationship between the twist value of the wafer and the thickness difference between the thickness of the third oxide layer (T4) and the total thickness of the first and second oxide layers (T0) is relatively complex, not a simple direct or inverse proportion relationship. Therefore, special attention needs to be paid to the twist value of the wafer when selecting the preset threshold value. If it is greater than this preset threshold range, there will be a situation of excessive twist value, which will increase the scratches in the edge area of the wafer, thus increasing the defect proportion.

[0087] Table 2 Corresponding relationship table between the thickness of the defect enrichment layer and the defect occurrence proportion

[0088]

[0089] Referring to Table 2 and combining Figure 7 As shown, the thicknesses of the defect enrichment layers in Example 1, Comparative Example 1, Comparative Example 2, and Comparative Example 3 in Table 2 are different. In Example 1, the thickness of the defect enrichment layer is 0.5μm, the twist value (warp) of the bonded wafer is 72.9, the warpage value (bow) is 41.5, and the defect occurrence proportion < 0.3%. Combining Comparative Example 1 to Comparative Example 3, it can be seen that when the thickness of the defect enrichment layer is greater than or equal to 2μm, its defect occurrence proportion is greater than or equal to 2.80%. Therefore, in this embodiment, it is preferably to make the thickness of the defect enrichment layer less than 2μm to reduce the defect occurrence proportion.

[0090] In summary, in the method for preparing a bonded wafer provided in the embodiment of the present invention, a first oxide layer is first formed on one surface of the device wafer, and the first oxide layer has a first thickness; then, a second oxide layer is formed on the surface of the defect enrichment layer, and a third oxide layer is formed on the back surface of the support wafer. The second oxide layer has a third thickness, and the third oxide layer has a fourth thickness; the first oxide layer is bonded to face the third oxide layer to form a bonded wafer; the bonded wafer is subjected to a peeling process; wherein, the first thickness, the second thickness, the third thickness, and the fourth thickness satisfy the following conditions: the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold; and / or the second thickness is within a set range. Since a third oxide layer is formed on the back surface of the support wafer, the stress on the back surface of the support wafer can be increased. Therefore, the stress generated by the third oxide layer can cancel out the stress generated during the formation of the defect enrichment layer, thereby reducing the warping and twisting deformation of the support wafer, and further reducing the scratching problem of the bonded wafer surface caused by deformation during the subsequent peeling process. In addition, the difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold. After the bonding is completed, the superposition value of the bending of the bonded wafer caused by the thickness difference between the third oxide layer and the total thickness of the first oxide layer and the second oxide layer and the bending of the bonded wafer caused by the stress of the defect enrichment layer is less than 50 μm, thereby further reducing the scratching problem of the wafer surface. If the second thickness is within the set range, the defect occurrence ratio can be reduced.

[0091] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for preparing a bonded wafer, characterized in that, Comprising: Providing a device wafer and a support wafer, and the support wafer has a front surface and a back surface which are oppositely arranged; Forming a first oxide layer on one surface of the device wafer, and the first oxide layer has a first thickness; Forming a defect enrichment layer on the front surface of the support wafer, and the defect enrichment layer has a second thickness; Forming a second oxide layer on the surface of the defect enrichment layer, and forming a third oxide layer on the back surface of the support wafer, the second oxide layer has a third thickness, and the third oxide layer has a fourth thickness; Bonding the first oxide layer facing the third oxide layer to form a bonded wafer; Performing a peeling process on the bonded wafer; Wherein, the first thickness, the second thickness, the third thickness and the fourth thickness satisfy the following conditions: The difference between the fourth thickness and the sum of the first thickness and the third thickness is within a preset threshold; and / or The second thickness is within a set range.

2. The method for preparing a bonded wafer according to claim 1, wherein The preset threshold is greater than or equal to -0.4 μm and less than or equal to 0.4 μm.

3. The method for preparing a bonded wafer according to claim 1, wherein, The set range of the second thickness is less than 2 μm and greater than 0 μm.

4. The method for preparing a bonded wafer according to claim 1, wherein, The method for forming the defect enrichment layer on the front surface of the support wafer includes: Adopting an epitaxial chemical vapor deposition process, and maintaining a first preset time under a first epitaxial temperature and a first epitaxial process gas condition to form an initial defect enrichment layer on the front surface of the support wafer; Raising the temperature of the epitaxial chemical vapor deposition process from the first epitaxial temperature to a second epitaxial temperature, and maintaining a second preset time under a second epitaxial process gas condition to increase the thickness of the initial defect enrichment layer to the second thickness to form the defect enrichment layer.

5. The method for preparing a bonded wafer according to claim 4, wherein, The first epitaxial temperature is 400 °C to 700 °C, the second epitaxial temperature is 800 °C to 1100 °C, the first preset time is less than or equal to 3 min, the second preset time is less than or equal to 8 min, and both the first epitaxial process gas and the second epitaxial process gas include silane.

6. The method for preparing a bonded wafer according to claim 1, wherein, The method for forming the first oxide layer includes: Pre-treating the device wafer with a first oxidation temperature and a first process gas; Performing a first thermal oxidation process to form the first oxide layer under a second oxidation temperature and a second process gas condition, and the second oxidation temperature is higher than the first oxidation temperature.

7. The method for preparing a bonded wafer according to claim 6, wherein The first oxidation temperature is 300 °C to 500 °C, and the first process gas includes nitrogen or argon.

8. The method for preparing a bonded wafer according to claim 6, wherein The second oxidation temperature is 850 °C to 1050 °C, and the second oxidation process gas includes hydrogen and oxygen.

9. The method for preparing a bonded wafer according to claim 7 or 8, wherein The method for forming the second oxide layer and the third oxide layer includes: Pre-treating the support wafer with a first oxidation temperature and a first process gas; Performing a second thermal oxidation process to form the second oxide layer and the third oxide layer under the second oxidation temperature and the second process gas condition, and the process time of the second thermal oxidation process is different from that of the first thermal oxidation process.

10. The method for preparing a bonded wafer according to claim 9, wherein, The process time of the first thermal oxidation process is 30 min to 60 min, and the process time of the second thermal oxidation process is 140 min to 170 min.

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