Anti-interference semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to an anti-interference semiconductor structure and a preparation method thereof, and electronic equipment. The anti-interference semiconductor structure comprises a first electrode, a second electrode and an electrode field plate structure which extend along a first direction; in the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects with the second direction; the electrode field plate structure comprises a first field plate structure and a second field plate structure which are connected with each other, the first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction; the third direction and the fourth direction at least intersect with the first direction; and the first field plate structure and the second field plate structure are jointly used for inhibiting induced current generated by the anti-interference semiconductor structure in a high-power microwave radiation environment. Induced current generated on the first field plate structure and the second field plate structure counteracts each other, so that the stability of the semiconductor structure in an HPM irradiation environment can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to an anti-interference semiconductor structure, a preparation method thereof, and an electronic device. Background Art

[0002] Important power electronic systems such as the power management module and the motor drive converter in an unmanned aerial vehicle are components vulnerable to high-power microwave (HPM) pulse interference and damage, resulting in power supply or power failure and crashing of the aircraft. Among them, power devices are the key core components of these power electronic systems.

[0003] The main form of HPM attack is to transmit and couple pulse energy into the internal of the unmanned aerial vehicle electronic system, such as the power electronic system, and then transfer the energy to the internal power semiconductor devices, generating instantaneous interference and surge impact on these devices through electrical effects, thermal effects, and their combined effects, resulting in device degradation or even burnout. Summary of the Invention

[0004] Based on this, it is necessary to provide an anti-interference semiconductor structure, a preparation method thereof, and an electronic device that can resist current impact generated in an HPM irradiation environment.

[0005] In a first aspect, the present application provides an anti-interference semiconductor structure, including: a first electrode, a second electrode, and an electrode field plate structure extending along a first direction respectively; wherein,

[0006] Along a second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects with the second direction;

[0007] The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction; the third direction and the fourth direction intersect with at least the first direction;

[0008] The first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the anti-interference semiconductor structure in a high-power microwave radiation environment.

[0009] In one embodiment, the third direction and the fourth direction are different, and both the third direction and the fourth direction intersect with the second direction; wherein, one end of the first field plate structure close to the first target electrode is connected to one end of the second field plate structure close to the first target electrode, and the first target electrode includes the first electrode or the second electrode.

[0010] In one embodiment, the electrode field plate structure includes a plurality of first field plate units arranged along the first direction, and the plurality of first field plate units respectively include the first field plate structure and the second field plate structure;

[0011] Among any two adjacent first field plate units, one end of the second field plate structure of one first field plate unit close to the second target electrode is connected to one end of the first field plate structure of the other first field plate unit close to the second target electrode; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

[0012] In one embodiment, the third direction and the fourth direction are respectively the same as or intersect with the second direction; wherein, the electrode field plate structure further includes a first connection structure, and one end of the first field plate structure close to the first target electrode and one end of the second field plate structure close to the first target electrode are connected through the first connection structure; the first target electrode includes the first electrode or the second electrode.

[0013] In one embodiment, the electrode field plate structure includes a second connection structure and a plurality of second field plate units arranged along the first direction, and the plurality of second field plate units include the first field plate structure and the second field plate structure;

[0014] Any two adjacent second field plate units are connected through the second connection structure, wherein, one end of the second field plate structure in one second field plate unit close to the second target electrode is connected to one end of the second connection structure, and one end of the first field plate structure in the other second field plate unit close to the second target electrode is connected to the other end of the second connection structure; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

[0015] In one embodiment, the electrode field plate structure further includes a third field plate structure and a fourth field plate structure, both the third field plate structure and the fourth field plate structure extend along the second direction, one end of the third field plate structure close to the second electrode is connected to one end of a first field plate structure close to the second electrode, and one end of the fourth field plate structure close to the second electrode is connected to one end of a second field plate structure close to the second electrode.

[0016] In one embodiment, the shape of the first field plate structure is one of a straight line type and a curve type, and the shape of the second field plate structure is one of a straight line type and a curve type.

[0017] In one embodiment, the anti-interference semiconductor structure further includes a third electrode;

[0018] In the second direction, the third electrode is located between the first electrode and the first field plate structure or the second field plate structure.

[0019] In a second aspect, the present application further provides a method for manufacturing a semiconductor structure, including:

[0020] Providing a substrate;

[0021] Forming a first electrode, a second electrode, and an electrode field plate structure respectively extending along a first direction on the substrate; wherein,

[0022] Along a second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction;

[0023] The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other, the first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction; the third direction and the fourth direction at least intersect the first direction;

[0024] The first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the semiconductor structure in a high-power microwave radiation environment.

[0025] In a third aspect, the present application further provides an electronic device, including the anti-interference semiconductor structure provided in any of the above embodiments, or manufactured by the method for manufacturing a semiconductor structure provided in any of the above embodiments.

[0026] In the above anti-interference semiconductor structure, its preparation method, and the electronic device, the anti-interference semiconductor structure includes a first electrode, a second electrode, and an electrode field plate structure that extend along a first direction respectively; wherein, along a second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects with the second direction; the electrode field plate structure includes a first field plate structure and a second field plate structure that are connected to each other, the first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction; the third direction and the fourth direction intersect with at least the first direction; the first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the semiconductor structure in a high-power microwave radiation environment. The electrode field plate structure can improve the electric field distribution on the device surface and increase the breakdown voltage of the device. In addition, in a high-power microwave radiation environment, the induced current directions on the first field plate structure and the second field plate structure are opposite and can cancel each other out, effectively suppressing the interference effect of HPM radiation on the device and improving the reliability of the semiconductor structure. In addition, compared with a rectangular field plate structure that covers the entire gate and source / drain surfaces, the field plate structure of the present application has a small area and can reduce the parasitic capacitance generated due to the introduction of the field plate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is one of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0029] Figure 2 It is the second of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0030] Figure 3 It is the third of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0031] Figure 4 It is the fourth of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0032] Figure 5 It is the fifth of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0033] Figure 6 It is the sixth of the top-view structure schematic diagrams of the anti-interference semiconductor structure provided in an embodiment;

[0034] Figure 7 Seventh top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0035] Figure 8 Eighth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0036] Figure 9 Ninth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0037] Figure 10 Tenth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0038] Figure 11 Eleventh top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0039] Figure 12 Twelfth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0040] Figure 13 Thirteenth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0041] Figure 14 Fourteenth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0042] Figure 15 Fifteenth top - view structural schematic diagram of the anti - interference semiconductor structure provided in an embodiment;

[0043] Figure 16 Flow schematic diagram of the preparation method of the semiconductor structure provided in an embodiment;

[0044] Figure 17 Cross - sectional structural schematic diagram of a gallium nitride power device provided in an embodiment. Detailed implementation manners

[0045] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various layers and electrodes, these layers and electrodes should not be limited by these terms. These terms are only used to distinguish one layer or electrode from another. Thus, without departing from the teachings of the present invention, the first layer or electrode discussed below may be referred to as the second layer or electrode; for example, the first electrode may be referred to as the second electrode, and similarly, the second electrode may be referred to as the first electrode; the first electrode and the second electrode are different electrodes. For example, the first electrode may be a source electrode and the second electrode may be a drain electrode, or the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0048] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0049] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0050] In one embodiment, as Figure 1As shown, the present application provides an anti-interference semiconductor structure, including a first electrode 100, a second electrode 200, and an electrode field plate structure 300 that extend along a first direction respectively. Along a second direction, the electrode field plate structure 300 is located between the first electrode 100 and the second electrode 200. The first direction intersects the second direction. Exemplarily, the first direction can be Figure 1 the longitudinal direction in Figure 1 , and the second direction can be the transverse direction in

[0051] . The first electrode 100 can be one of the source electrode or the drain electrode, and the second electrode 200 can be the other of the source electrode or the drain electrode. The electrode field plate structure 300 can be a source field plate or a drain field plate.

[0052] The electrode field plate structure 300 includes a first field plate structure 310 and a second field plate structure 320 that are connected to each other. The first field plate structure 310 and the second field plate structure 320 can be directly connected or indirectly connected through other structures. The first field plate structure 310 extends along a third direction, and the second field plate structure 320 extends along a fourth direction. The third direction and the fourth direction intersect at least with the first direction. It can be understood that the third direction is parallel to or intersects with the fourth direction.

[0052] The first field plate structure 310 and the second field plate structure 320 are jointly used to suppress the induced current generated by the anti-interference semiconductor structure in a high-power microwave radiation environment. In a high-power microwave environment, the induced current generated on the first field plate structure 310 flows from the first electrode 100 to the second electrode 200, or from the second electrode 200 to the first electrode 100. Similarly, the induced current generated on the second field plate structure 320 flows from the first electrode 100 to the second electrode 200, or from the second electrode 200 to the first electrode 100. As Figure 1 shown, the arrows indicate the flow direction of the induced current. The induced currents on the first field plate structure 310 and the second field plate structure 320 are out of phase and cancel each other at the connection of the first field plate structure 310 and the second field plate structure 320.

[0053] In an embodiment of the present application, the anti-interference semiconductor structure includes a first electrode 100, a second electrode 200, and an electrode field plate structure 300 that respectively extend along a first direction. The electrode field plate structure 300 can improve the electric field distribution on the surface of the device and increase the breakdown voltage of the device. The electrode field plate structure 300 includes a first field plate structure 310 and a second field plate structure 320 that are connected to each other. The first field plate structure 310 extends along a third direction, and the second field plate structure 320 extends along a fourth direction; the first target electrode includes the first electrode 100 or the second electrode 200. The third direction and the fourth direction intersect at least with the first direction, that is, the third direction is parallel to or intersects with the fourth direction. In this way, in a high-power microwave radiation environment, the induced current directions generated on the first field plate structure 310 and the second field plate structure 320 are opposite and can cancel each other out, effectively suppressing the interference of HPM radiation on the device and improving the reliability of the semiconductor structure. In addition, compared with a rectangular field plate structure that covers the entire gate and source / drain surfaces, the field plate structure of the present application has a small area and can reduce the parasitic capacitance generated due to the introduction of the field plate structure.

[0054] In one embodiment, the third direction and the fourth direction are different, and both the third direction and the fourth direction intersect with a second direction. Among them, one end of the first field plate structure 310 close to the first target electrode is connected to one end of the second field plate structure 320 close to the first target electrode, and the first target electrode includes the first electrode 100 or the second electrode 200.

[0055] Taking the first target electrode as the first electrode 100 as an example, as Figure 1 or Figure 2 shown, one end of the first field plate structure 310 and the second field plate structure 320 close to the first electrode 100 are connected to each other. The electrode field plate structure formed by the first field plate structure 310 and the second field plate structure 320 can be triangular arc-shaped, as Figure 2 shown, or can be triangular, as Figure 1 shown.

[0056] In one embodiment, as Figure 3 or Figure 4 shown, the electrode field plate structure 300 includes a plurality of first field plate units arranged along the first direction, Figure 3 neutralize Figure 4 The part enclosed by the dotted line in

[0057] In one embodiment, the third direction and the fourth direction are respectively the same as or intersect with the second direction; wherein, the electrode field plate structure 300 further includes a first connection structure 330, and one end of the first field plate structure 310 close to the first target electrode is connected to one end of the second field plate structure 320 close to the first target electrode through the first connection structure 330.

[0058] Exemplarily, as Figure 5 and Figure 6 shown, the third direction and the fourth direction are respectively the same as the second direction. The first connection structure 330 can be Figure 5 the linear structure shown, or can be Figure 6 the triangular structure shown. One end of the first field plate structure 310 close to the first target electrode is connected to one end of the second field plate structure 320 close to the first target electrode through the first connection structure 330.

[0059] Exemplarily, as Figure 7 shown, the third direction and the fourth direction respectively intersect with the second direction, and one end of the first field plate structure 310 close to the first target electrode is connected to one end of the second field plate structure 320 close to the first target electrode through the first connection structure 330.

[0060] In one embodiment, as Figures 8 - 10 shown, the electrode field plate structure 300 includes a second connection structure 340 and a plurality of second field plate units arranged along the first direction, and the plurality of second field plate units include a first field plate structure 310 and a second field plate structure 320. Figures 8 - 10 In, the boxed rectangular area represents a second field plate unit, and the boxed circular area represents a second connection structure 340. The shape of the second connection structure 340 can be linear or triangular.

[0061] Any two adjacent second field plate units are connected through the second connection structure 340, wherein, one end of the second field plate structure 320 close to the second target electrode in one second field plate unit is connected to one end of the second connection structure 340, and one end of the first field plate structure 310 close to the second target electrode in the other second field plate unit is connected to the other end of the second connection structure. Wherein, one of the first target electrode and the second target electrode is the first electrode 100, and the other is the second electrode 200.

[0062] In one embodiment, as Figures 11 - 15As shown, the electrode field plate structure 300 further includes a third field plate structure 350 and a fourth field plate structure 360. Both the third field plate structure 350 and the fourth field plate structure 360 extend in the second direction. One end of the third field plate structure 350 close to the second electrode 200 is connected to one end of a first field plate structure 310 close to the second electrode 200, and one end of the fourth field plate structure 360 close to the second electrode 200 is connected to one end of a second field plate structure 320 close to the second electrode 200. In this embodiment, in the HPM irradiation environment, the induced current directions generated on the third field plate structure 350 and the connected first field plate structure 310 are opposite, and can cancel each other out at the connection; the induced current directions generated on the fourth field plate structure 360 and the connected second field plate structure 320 are opposite, and can cancel each other out at the connection. In addition, the third field plate structure 350 and the fourth field plate structure 360 can be connected to the first target electrode or can be floatingly arranged.

[0063] In one embodiment, the shape of the first field plate structure 310 is one of a straight line type and a curve type, and the shape of the second field plate structure 320 is one of a straight line type and a curve type.

[0064] In one embodiment, the semiconductor structure further includes an anti-interference third electrode. In the second direction, the third electrode is located between the first electrode 100 and the first field plate structure 310 or the second field plate structure 320. The third electrode is a gate electrode.

[0065] In one embodiment, the present application further provides a method for manufacturing a semiconductor structure, as Figure 16 shown, including steps S1602 - S1604.

[0066] S1602, provide a substrate.

[0067] S1604, form a first electrode, a second electrode, and an electrode field plate structure on the substrate, which respectively extend in the first direction.

[0068] In the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction. The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends in the third direction, and the second field plate structure extends in the fourth direction. The third direction and the fourth direction at least intersect the first direction. The first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the semiconductor structure in a high-power microwave radiation environment. For the specific description of this semiconductor structure, reference can be made to the definitions of the anti-interference semiconductor structure in the above embodiments, and details are not described herein again.

[0069] The anti-interference semiconductor structure provided by the present application can cover wide-bandgap semiconductor power devices such as gallium nitride and silicon carbide, as well as silicon-based power devices, etc. Exemplarily, taking a gallium nitride power device as an example, as Figure 17As shown in the figure, the gallium nitride power device includes a substrate 400, a channel layer 500, a barrier layer 600, a first electrode 100, a second electrode 200, a third electrode 1000, a first passivation layer 700, a second passivation layer 800, a third passivation layer 900, and an electrode field plate structure 300. The first electrode 100 is the source electrode, the second electrode 200 is the drain electrode, the third electrode 1000 is the gate electrode, the third electrode 1000 includes a P-GaN layer 1010 and a gate metal layer 1020, and the electrode field plate structure 300 is the source field plate. Among them, the channel layer 500 is located between the substrate 400 and the barrier layer 600, the P-GaN layer 1010 is located on the side of the barrier layer 600 away from the channel layer 500, the gate metal layer 1020 is located on the side of the P-GaN layer 1010 away from the barrier layer 600, and the first passivation layer 700 is located on the side of the barrier layer 600 away from the channel layer 500 and the sidewalls of the gate. The source electrode and the drain electrode are respectively located on the side of the first passivation layer 700 away from the barrier layer 600, penetrate the first passivation layer 700, and are in contact with the barrier layer 600. In the second direction, the gate is disposed between the source electrode and the drain electrode. The second passivation layer 800 is located on the side of the source electrode, the drain electrode, and the gate away from the first passivation layer 700 and on the exposed surface of the first passivation layer 700. The source field plate is located on the side of the second passivation layer 800 away from the first passivation layer 700, and one end of the source field plate is connected to the source electrode. The third passivation layer is located on the side of the source plate away from the second passivation layer.

[0070] Among them, the material of the substrate can be any suitable substrate material known in the art, such as silicon, silicon carbide, etc. The material of the channel layer is GaN, the material of the barrier layer is AlGaN, and the channel layer and the barrier layer can form a heterojunction. The structure of the source field plate on the side of the second passivation layer 800 away from the first passivation layer 700 can refer to the definition of the electrode field plate structure 300 in the above embodiments.

[0071] Since the directions of the induced currents generated by the adjacent first field plate structure 310 and second field plate structure 320 in the source field plate are opposite in the HPM irradiation environment and can cancel each other out, the survivability and reliability of the gallium nitride power device in a strong electromagnetic environment can be improved. In addition, the source field plate extends from near the drain end to the gate end and forms a spaced non-closed structure near the drain end. While effectively modulating the electric field, it can further reduce the parasitic capacitance, thereby effectively improving the breakdown voltage and fast turn-off speed of the device and enhancing the efficiency of the power electronic system.

[0072] Furthermore, the manufacturing method of the gallium nitride power device may include the following steps:

[0073] S1, providing a substrate.

[0074] S2, growing a channel layer on the substrate. The material of the channel layer can be GaN.

[0075] S3. Grow a barrier layer on the side of the channel layer away from the substrate. The material of the barrier layer can be AlGaN.

[0076] S4. Grow a p-GaN layer on the side of the barrier layer away from the channel layer.

[0077] S5. Grow a first passivation layer on the side of the barrier layer away from the channel layer and on the side of the p-GaN layer away from the barrier layer.

[0078] S6. Etch the first passivation layer to form a first opening, a second opening, and a third opening.

[0079] S7. Form a source electrode in the first opening, form a gate metal layer in the second opening, and form a drain electrode in the third opening.

[0080] S8. Grow a second passivation layer on the side of the source electrode, the drain electrode, and the gate away from the barrier layer and on the exposed surface of the first passivation layer.

[0081] S9. Etch the second passivation layer to form a fourth opening and a fifth opening.

[0082] S10. Form a source field plate in the fourth opening and on the side of the second passivation layer away from the first passivation layer. Among them, the source field plate formed on the side of the second passivation layer away from the first passivation layer can refer to the electrode field plate structure provided in any of the above embodiments.

[0083] S11. Form a drain connector in the fifth opening.

[0084] S12. Form a third passivation layer on the side of the source field plate away from the second passivation layer and on the exposed surface of the second passivation layer.

[0085] In one embodiment, the present application also provides an electronic device, which can be prepared by the preparation method of the semiconductor structure provided in any of the above embodiments, or can include the anti-interference semiconductor structure provided in any of the above embodiments.

[0086] It should be understood that unless there is a clear description in this article, the execution of the above steps does not have a strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the above steps can include multiple steps or multiple stages. These steps or stages do not necessarily need to be executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0087] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0088] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0089] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. An anti-interference semiconductor structure, characterized in that, Comprising: A first electrode, a second electrode, and an electrode field plate structure extending respectively along a first direction; wherein, Along a second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects with the second direction; The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends along a third direction, and the second field plate structure extends along a fourth direction; the third direction and the fourth direction at least intersect with the first direction; The first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the anti-interference semiconductor structure in a high-power microwave radiation environment.

2. The anti-interference semiconductor structure according to claim 1, characterized in that, The third direction and the fourth direction are different, and both the third direction and the fourth direction intersect with the second direction; wherein, one end of the first field plate structure close to the first target electrode is connected to one end of the second field plate structure close to the first target electrode, and the first target electrode includes the first electrode or the second electrode.

3. The anti-interference semiconductor structure according to claim 2, wherein The electrode field plate structure includes a plurality of first field plate units arranged along the first direction, and the plurality of first field plate units respectively include the first field plate structure and the second field plate structure; Among any two adjacent first field plate units, one end of the second field plate structure of one first field plate unit close to the second target electrode is connected to one end of the first field plate structure of another first field plate unit close to the second target electrode; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

4. The anti-interference semiconductor structure according to claim 1, characterized in that, The third direction and the fourth direction are respectively the same as or intersect with the second direction; wherein, the electrode field plate structure further includes a first connection structure, and one end of the first field plate structure close to the first target electrode is connected to one end of the second field plate structure close to the first target electrode through the first connection structure; the first target electrode includes the first electrode or the second electrode.

5. The anti-interference semiconductor structure according to claim 4, characterized in that, The electrode field plate structure includes a second connection structure and a plurality of second field plate units arranged along the first direction, and the plurality of second field plate units include the first field plate structure and the second field plate structure; Any two adjacent second field plate units are connected through the second connection structure. Among them, one end of the second field plate structure in one second field plate unit close to the second target electrode is connected to one end of the second connection structure, and one end of the first field plate structure in another second field plate unit close to the second target electrode is connected to the other end of the second connection structure; wherein, one of the first target electrode and the second target electrode is the first electrode, and the other is the second electrode.

6. The anti-interference semiconductor structure according to any one of claims 1-5, characterized in that The electrode field plate structure further includes a third field plate structure and a fourth field plate structure. Both the third field plate structure and the fourth field plate structure extend along the second direction. One end of the third field plate structure close to the second electrode is connected to one end of the first field plate structure close to the second electrode, and one end of the fourth field plate structure close to the second electrode is connected to one end of the second field plate structure close to the second electrode.

7. The anti-interference semiconductor structure according to any one of claims 1-5, characterized in that, The shape of the first field plate structure is one of a straight line type and a curve type, and the shape of the second field plate structure is one of a straight line type and a curve type.

8. The anti-interference semiconductor structure according to any one of claims 1-5, characterized in that, The anti-interference semiconductor structure further includes a third electrode; In the second direction, the third electrode is located between the first electrode and the first field plate structure or the second field plate structure.

9. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a first electrode, a second electrode, and an electrode field plate structure respectively extending along the first direction on the substrate; wherein, In the second direction, the electrode field plate structure is located between the first electrode and the second electrode; the first direction intersects the second direction; The electrode field plate structure includes a first field plate structure and a second field plate structure connected to each other. The first field plate structure extends along the third direction, and the second field plate structure extends along the fourth direction; the third direction and the fourth direction at least intersect the first direction; The first field plate structure and the second field plate structure are jointly used to suppress the induced current generated by the semiconductor structure in a high-power microwave radiation environment.

10. An electronic device, characterized in that, Comprising the anti-interference semiconductor structure according to any one of claims 1-8, or prepared by the preparation method of the semiconductor structure according to claim 9.

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