Spread spectrum clock generator and electronic device

Abstract

The application provides a spread spectrum clock generator and an electronic device, the spread spectrum clock generator adds a second loop on the basis of a traditional clock generator loop (i.e. a first loop), the second loop draws a corresponding voltage from a loop filter in the traditional clock generator loop, and generates a corresponding second voltage to control the modulation frequency and modulation depth of the spread spectrum of the output of a ring oscillator in the traditional clock generator loop, the scheme is simple and easy to implement, can effectively improve the electromagnetic interference (EMI) problem, and can avoid using a sigma-delta modulator, greatly reduces the clock jitter of the output of the first loop, improves the reliability, and is suitable for the application requirements of a spread spectrum phase-locked loop. Further, the second loop is implemented by using a pure analog circuit, and has a simple structure, a small area and low cost. In addition, by adjusting the parameters in the second loop, the modulation frequency and modulation depth of the spread spectrum can be changed with process, voltage and temperature (PVT).

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock generator technology, and particularly relates to a spread spectrum clock generator and an electronic device. BACKGROUND

[0002] With the rapid development of CMOS (Complementary Metal Oxide Semiconductor) technology, the working frequency of electronic systems is constantly increasing, and the requirements for high-speed clocks are more stringent. Today, the data rate of wired communication systems such as DDR (Double Data Rate), PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) or HDMI (High Definition Multimedia Interface) is rapidly increasing, and the EMI (Electromagnetic Interference) problem caused by high-speed clocks is becoming increasingly important. It can interfere with normal data transmission and even cause data errors.

[0003] Spread spectrum clock generators (SSCG) can disperse energy concentrated in a narrow frequency band to a set wide frequency band through frequency modulation, thereby effectively reducing EMI.

[0004] Existing spread spectrum clock generators can effectively reduce EMI, but still have the disadvantages of low reliability, complex circuit structure, and high cost. SUMMARY

[0005] The purpose of the present application is to provide a spread spectrum clock generator and an electronic device with a simple circuit structure, low cost, and high reliability.

[0006] To achieve the above purpose, the present application provides a spread spectrum clock generator, which comprises:

[0007] A first loop comprising a loop filter and a ring oscillator, and configured to generate a first voltage for controlling the oscillation frequency of the output of the ring oscillator based on the voltage output by the first output end of the loop filter;

[0008] A second loop coupled to the second output end of the loop filter and configured to generate a second voltage for controlling the modulation frequency and modulation depth of the spread spectrum of the output of the ring oscillator based on the voltage output by the second output end of the loop filter.

[0009] Optionally, the first loop further comprises a phase frequency detector, a charge pump, a first gain amplifier and a frequency divider, the phase frequency detector, the charge pump, the loop filter and the first gain amplifier are sequentially coupled, a first input terminal of the phase frequency detector is coupled to an output terminal of the frequency divider, a second input terminal of the phase frequency detector is coupled to an input clock signal, the first gain amplifier is configured to convert a voltage outputted by a first output terminal of the loop filter into the first voltage and provide the first voltage to a first control terminal of the ring oscillator, and an output terminal of the ring oscillator is coupled to an input terminal of the frequency divider and an input terminal of the ring oscillator.

[0010] Optionally, the charge pump comprises an operational amplifier, a first MOS transistor, a second MOS transistor and a first adjustable resistor, a first input terminal of the operational amplifier is coupled to a bandgap reference voltage, a second input terminal of the operational amplifier is coupled to a first terminal of the first adjustable resistor and a drain of the first MOS transistor, an output terminal of the operational amplifier is coupled to a gate of the first MOS transistor and a gate of the second MOS transistor, a second terminal of the first adjustable resistor is grounded, and a drain of the second MOS transistor is coupled to an input terminal of the loop filter to provide a charge-discharge current.

[0011] Optionally, the loop filter comprises a filter resistor and a first filter capacitor, a first terminal of the filter resistor is configured as the first output terminal of the loop filter, a second terminal of the filter resistor is configured as the second output terminal of the loop filter and coupled to one terminal of the first filter capacitor and the second loop, and another terminal of the first filter capacitor is grounded.

[0012] Optionally, the loop filter is a multi-stage filter of two or more stages, and at least further comprises a second filter capacitor, one terminal of the second filter capacitor is coupled to the first terminal of the filter resistor, and another terminal of the second filter capacitor is grounded.

[0013] Optionally, the second loop comprises a triangular wave generator and a second gain amplifier, wherein a first input terminal of the triangular wave generator is coupled to the second output terminal of the loop filter, a second input terminal of the triangular wave generator is coupled to a corresponding reference voltage, the triangular wave generator is configured to output a voltage outputted by the second output terminal of the loop filter as a triangular wave voltage, and a period of the triangular wave voltage is used to control a modulation frequency of the output of the ring oscillator for spread spectrum, and an amplitude of the triangular wave voltage is used to control a modulation depth of the output of the ring oscillator for spread spectrum, and an input terminal of the second gain amplifier is coupled to an output terminal of the triangular wave generator and configured to convert the triangular wave voltage into the second voltage to provide the second voltage to a second control terminal of the ring oscillator.

[0014] Optionally, the triangular wave generator comprises a trans-impedance amplifier and an integration capacitor, a first input of the trans-impedance amplifier is coupled to the second output of the loop filter, a second input of the trans-impedance amplifier is coupled to the reference voltage, the trans-impedance amplifier is configured to convert a difference between the voltage of the second output of the loop filter and the reference voltage into an error current, and the integration capacitor is coupled to an output of the trans-impedance amplifier and an input of the second gain amplifier and is configured to integrate the error current to generate the triangular wave voltage.

[0015] Optionally, the error current △I = △V CTRL_R / R2, an amplitude △V of the triangular wave voltage = VBG / k, and a period T of the triangular wave voltage = a*R2*C2, wherein △VCTRL_R is the difference between the voltage of the second output of the loop filter and the reference voltage, 1 / R2 is a trans-impedance value of the trans-impedance amplifier, C2 is a capacitance value of the integration capacitor, VBG is a bandgap reference voltage, a is a constant, and k is a coefficient.

[0016] Optionally, k = a*R2*C2 / (2*C1*R), the ratio of R2 and R and the ratio of C2 and C1 are adjusted so that the coefficient k does not change with process, voltage, and temperature, and thus the modulation depth does not change with process, voltage, and temperature, wherein R = VBG / ICP, ICP is a charge and discharge current of the loop filter, and C1 is a capacitance value of a first filter capacitor at the second output of the loop filter.

[0017] Optionally, the trans-impedance amplifier comprises:

[0018] a differential input circuit coupled to the reference voltage and the second output of the loop filter and configured to convert the voltage of the second output of the loop filter into a first current and convert the reference voltage into a second current;

[0019] a first current mirror coupled to the differential input circuit and configured to mirror output the first current;

[0020] a second current mirror coupled to the differential input circuit and an output of the trans-impedance amplifier and configured to mirror output the second current;

[0021] a third current mirror coupled to the first current mirror and the output of the trans-impedance amplifier and configured to mirror output the current output by the first current mirror again, so that the output of the trans-impedance amplifier outputs the error current.

[0022] Optionally, the differential input circuit comprises a first input transistor, a second input transistor and a second adjustable resistor, a gate of the first input transistor is coupled to the second output terminal of the loop filter, a gate of the second input transistor is coupled to the reference voltage, a source of the first input transistor is coupled to one end of the second adjustable resistor, a source of the second input transistor is coupled to another end of the second adjustable resistor, wherein the second adjustable resistor determines the transconductance value of the transconductance amplifier.

[0023] Optionally, the spread spectrum clock generator further comprises at least one of (1) to (4) as follows:

[0024] (1) the first current mirror comprises a first mirror transistor and a second mirror transistor, a gate of the first mirror transistor and a gate of the second mirror transistor are both coupled to a drain of the first input transistor, a drain of the second mirror transistor is coupled to a source of the first input transistor, a drain of the first mirror transistor is an output terminal of the first current mirror and is coupled to an input terminal of the third current mirror;

[0025] (2) the second current mirror comprises a third mirror transistor and a fourth mirror transistor, a gate of the third mirror transistor and a gate of the fourth mirror transistor are both coupled to a drain of the second input transistor, a drain of the third mirror transistor is coupled to a source of the second input transistor, a drain of the fourth mirror transistor is an output terminal of the second current mirror and is coupled to an output terminal of the third current mirror and an output terminal of the transconductance amplifier;

[0026] (3) the third current mirror comprises a fifth mirror transistor and a sixth mirror transistor, a gate of the fifth mirror transistor, a drain of the fifth mirror transistor and a gate of the sixth mirror transistor are mutually coupled, as an input terminal of the third current mirror and are coupled to the output terminal of the first current mirror, a drain of the sixth mirror transistor is an output terminal of the third current mirror and is coupled to the output terminal of the second current mirror and the output terminal of the transconductance amplifier;

[0027] (4) the differential input circuit further comprises a first current source, a second current source, a third current source and a fourth current source, one end of the first current source is coupled to the drain of the first input transistor, one end of the second current source is coupled to the source of the first input transistor, one end of the third current source is coupled to the drain of the second input transistor, one end of the fourth current source is coupled to the source of the second input transistor.

[0028] Optionally, adjusting the reference voltage can change the spread spectrum mode of the spread spectrum clock generator, wherein:

[0029] when the reference voltage is adjusted to a set value, the spread spectrum clock generator realizes center spread spectrum;

[0030] when the reference voltage is adjusted to be lower than the set value, the spread spectrum clock generator implements down spread spectrum;

[0031] when the reference voltage is adjusted to be higher than the set value, the spread spectrum clock generator implements up spread spectrum.

[0032] Based on the same inventive concept, the present application also provides an electronic device comprising the spread spectrum clock generator as described in the present application.

[0033] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0034] 1. By adding a second loop on the basis of the traditional clock generator loop (i.e. the first loop), and the second loop draws a corresponding voltage from the loop filter in the traditional clock generator loop, and generates a corresponding second voltage based on the voltage, which is used to control the modulation frequency and modulation depth of the output of the ring oscillator in the traditional clock generator loop for spread spectrum, the scheme is simple, easy to implement, can effectively improve the electromagnetic interference (EMI) problem, and can avoid using a sigma-delta modulator, thereby greatly reducing the clock jitter of the output of the first loop, improving reliability, and being very suitable for the application requirements of spread spectrum phase-locked loop.

[0035] 2. The second loop includes a triangular wave generator and a gain amplifier, which is realized by pure analog circuit, and has simple circuit structure, small area, low cost and low power consumption.

[0036] 3. The modulation frequency of the output of the ring oscillator for spread spectrum can be changed by adjusting or trimming the resistance value of the transconductance amplifier and the capacitance value of the integration capacitor in the second loop, and the modulation frequency is not changed with PVT (i.e. process, voltage, temperature), and the modulation depth of the output of the ring oscillator for spread spectrum can also be changed by adjusting or trimming the bias current of the transconductance amplifier to adjust the corresponding coefficient, and the modulation depth is also not changed with PVT. BRIEF DESCRIPTION OF DRAWINGS

[0037] Those skilled in the art will understand that the provided drawings are for better understanding of the present application, and do not constitute any limitation on the scope of the present application. Among them:

[0038] Figure 1 is a schematic diagram of the architecture of the spread spectrum clock generator of an embodiment of the present application,

[0039] Figure 2 is an example circuit schematic diagram of a charge pump in the spread spectrum clock generator of an embodiment of the present application.

[0040] Figure 3is an exemplary circuit schematic of a loop filter in a spread spectrum clock generator of an embodiment of the present invention.

[0041] Figure 4 is an exemplary circuit schematic of a ring oscillator in a spread spectrum clock generator of an embodiment of the present invention.

[0042] Figure 5 is an exemplary circuit schematic of a triangular wave generator in a spread spectrum clock generator of an embodiment of the present invention.

[0043] Figure 6 is an exemplary circuit schematic of a trans-impedance amplifier in a spread spectrum clock generator of an embodiment of the present invention.

[0044] Figure 7 is an exemplary schematic of a triangular wave voltage in a triangular wave generator in a spread spectrum clock generator of an embodiment of the present invention.

[0045] Figure 8 is an exemplary schematic of some signal timing in a spread spectrum clock generator of an embodiment of the present invention.

[0046] Figure 9 is an exemplary schematic of a change in spread spectrum mode when changing a reference voltage in a spread spectrum clock generator of an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known features are not described in detail in order to avoid obscuring the application. Unless otherwise specifically indicated, the drawings are not to scale. Accordingly, it should be understood that the application can be practiced with modification and alteration, and that the application be limited by the terms of the claims. It should also be understood that the

[0048] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0049] Please refer to Figure 1 An embodiment of the present invention provides a spread spectrum clock generator, which includes a first loop (loop1) and a second loop (loop2). The first loop (loop1) is the main loop and controls the oscillation frequency (also known as the "clock frequency") of the ring oscillator (ringOSC) 14 through a first voltage (Vc1). The second loop (loop2) is an auxiliary loop, which is led out from the second output terminal (not marked in the figure) of the loop filter 12 in the first loop (loop1) and controls the modulation frequency and modulation depth of the output of the ring oscillator 14 through the generation of a second voltage (Vc2).

[0050] The first loop, loop1, can be a conventional clock generator loop, which may include a frequency and phase detector 10, a charge pump 11, a loop filter 12, a first gain amplifier (AMP1) 13, a ring oscillator (ring OSC) 14, and a frequency divider (DIV) 15.

[0051] The first input terminal of the frequency and phase detector 10 is coupled to the output terminal of the frequency divider 15 to receive the feedback clock signal CLK_FB provided by the frequency divider 15. The second input terminal of the frequency and phase detector 10 receives the input clock signal CLK_IN. The frequency and phase detector 10 is used to compare the phase of the input clock signal CLK_IN and the feedback clock signal CLK_FB.

[0052] The input terminal of charge pump 11 is coupled to the output terminal of frequency and phase detector 10, and is used to perform charging or discharging based on the output result of frequency and phase detector 10. Specifically, when the phase of the input clock signal CLK_IN leads the feedback clock signal CLK_FB output by frequency divider 15, it indicates the current output frequency of ring oscillator 14 (i.e., the oscillation frequency output by ring oscillator 14, such as...). Figure 8 The frequency of fout in the middle is lower than the target frequency (e.g., fout) Figure 8When the phase of the feedback clock signal CLK FB lags behind the phase of the input clock signal CLK IN, it means that the output frequency of the ring oscillator 14 is lower than the target frequency, the phase detector 10 controls the charge pump 11 to output a larger charging current I CP to increase the output frequency of the ring oscillator 14, and vice versa. Finally, the output frequency of the ring oscillator 14 periodically varies in a triangular waveform shape, and the working timing is as shown in FIG. 3. Figure 8

[0053] The input end of the loop filter 12 is coupled to the output end of the charge pump 11, and is used to filter the output of the charge pump 11. The first output end of the loop filter 12 is coupled to the output end of the first gain amplifier 13 to provide the voltage V CTRL to the first gain amplifier 13. The second output end of the loop filter 12 is coupled to the second loop loop2 to provide the voltage V CTRL_R to the second loop loop2. Wherein, V CTRL is different from V CTRL_R .

[0054] The first input end (for example, the "+" input end) of the first gain amplifier 13 is coupled to the first output end of the loop filter 12. The output end of the first gain amplifier 13 is coupled to the second input end (for example, the "-" input end) of the first gain amplifier 13 and the first control end (not marked in the figure) of the ring oscillator 14. The first gain amplifier 13 is used to convert (for example, amplify) the voltage V CTRL output by the first output end of the loop filter 12 into the first voltage Vc1, and provide the first voltage Vc1 to the first control end of the ring oscillator 14 to control the oscillation frequency of the ring oscillator 14.

[0055] The ring oscillator 14 is used to oscillate and spread spectrum under the control of the first voltage Vc1 output by the first gain amplifier 13 and the second voltage Vc2 output by the second loop loop2, and further generate a signal with a corresponding output frequency. Wherein, the first voltage Vc1 controls the oscillation frequency of the ring oscillator 14, and the second voltage Vc2 controls the modulation frequency and the modulation depth of the spread spectrum of the output of the ring oscillator 14.

[0056] The input end of the frequency divider 15 is coupled to the output end of the ring oscillator 14, and the output end of the frequency divider 15 is coupled to the first input end of the phase detector 10. The frequency divider 15 is used to divide the frequency of the output of the ring oscillator 14 after the spread spectrum, and output the feedback clock signal CLK FB to the phase detector 10.

[0057] ​The second loop loop2 includes a triangle wave generator 16 and a second gain amplifier (AMP2) 17. A first input of the triangle wave generator 16 is coupled to a second output of the loop filter 12 to access the voltage V CTRL_R , a second input of the triangle wave generator 16 is coupled to a corresponding reference voltage VREF, and an output of the triangle wave generator 16 is coupled to a first input (e.g., a "+" input) of the second gain amplifier 17. The triangle wave generator 16 is configured to convert the voltage V CTRL_R output by the loop filter 12 into a triangle wave voltage V CTRL_C , and please refer to Figure 7 , a period T of the triangle wave voltage V CTRL_C is used to control the modulating frequency of the spread spectrum of the output of the ring oscillator 14, and an amplitude ⊿V of the triangle wave voltage V CTRL_C is used to control the modulating depth of the spread spectrum of the output of the ring oscillator 14.

[0058] The first input (e.g., the "+" input) of the second gain amplifier 17 is coupled to the output of the triangle wave generator 16, and a second input (e.g., a "-" input) of the second gain amplifier 17 is coupled to a second control terminal (not shown) of the ring oscillator 14. The second gain amplifier 17 is configured to convert (e.g., "amplify") the triangle wave voltage V CTRL_C output by the triangle wave generator 16 into a second voltage Vc2 to provide to the second control terminal of the ring oscillator 14.

[0059] It should be understood that the frequency and phase detector 10, the charge pump 11, the loop filter 12, the first gain amplifier 13, the frequency divider 15, the ring oscillator 14, the triangle wave generator 16, and the second gain amplifier 17 described above can be implemented by any suitable circuit design.

[0060] In an example, please refer to Figure 2The charge pump 11 includes an operational amplifier OP, a first MOS transistor P1, a second MOS transistor P2, and a first adjustable resistor R. A first input terminal (e.g., "-") of the operational amplifier OP is coupled to a bandgap reference voltage VBG. A second input terminal (e.g., "+") of the operational amplifier OP is coupled to a first terminal of the first adjustable resistor R and a drain of the first MOS transistor P1. An output terminal of the operational amplifier OP is coupled to a gate of the first MOS transistor P1 and a gate of the second MOS transistor P2. A second terminal of the first adjustable resistor R is grounded. A drain of the second MOS transistor P2 is coupled to an input terminal of the loop filter 13 to provide a charge / discharge current ICP. In the example, a source of the first MOS transistor P1 and a source of the second MOS transistor P2 are both coupled to a power supply voltage (not shown). The first MOS transistor P1 and the second MOS transistor P2 are both PMOS transistors. In other examples of the present application, one or both of the first MOS transistor P1 and the second MOS transistor P2 can be replaced by an NMOS transistor.

[0061] In an example, referring to Figure 3 The loop filter 12 includes a filter resistor R1 and a first filter capacitor C1. A first terminal of the filter resistor R1 serves as a first output terminal of the loop filter 12 and is coupled to an input terminal (e.g., a "+" input terminal) of the first gain amplifier 13. A second terminal of the filter resistor R1 serves as a second output terminal of the loop filter 12 and is coupled to one terminal of the first filter capacitor C1 and a second loop loop2. The other terminal of the first filter capacitor C1 is grounded.

[0062] In other examples, the loop filter 12 can be a two-order or more multi-order filter. The loop filter 12 can be formed by connecting a plurality of first-order RC filters in series, connecting a first-order RC filter and a plurality of filter capacitors in parallel, or connecting other suitable filters in series or in parallel. The present application does not limit the loop filter 12 to any specific form. The first output terminal and the second output terminal of the loop filter 12 formed by the multi-order filter are output terminals of two different order filters in the multi-order filter. For example, the first output terminal of the loop filter 12 is an output terminal of a last order filter in the multi-order filter, and the second output terminal is an output terminal of any order filter before the last order filter in the multi-order filter.

[0063] In another example, referring to Figure 3 The loop filter 12 is a two-order filter including a filter resistor R1, a first filter capacitor C1, and a second filter capacitor C0. The filter resistor R1 and the first filter capacitor C1 form a first order filter in series, and the filter resistor R1 and the second filter capacitor C0 form a second order filter. A first terminal of the filter resistor R1 is coupled to one terminal of the second filter capacitor C0 to form an output terminal of the two-order filter (i.e., the first output terminal of the loop filter 12) and output a voltage V CTRL, the second end of the filter resistor R1 is coupled to one end of the first filter capacitor C1 and serves as an output end of a first-order filter therein, to form a second output end of the loop filter 12 and output a voltage V CTRL_R , the other end of the first filter capacitor C1 is grounded. Figure 3 The loop filter 12 is a second-order filter, and the transfer function is, for example:

[0064]

[0065] The filter resistor R1, the first filter capacitor C1 and the second filter capacitor C0 jointly determine the zero point, pole position and frequency response characteristics of the second-order loop filter 12. By adjusting the filter resistor R1, the first filter capacitor C1 and the second filter capacitor C0, the cutoff frequency, stability and noise suppression capability of the loop filter 12 can be optimized. The denominator of the transfer function H(s) of the loop filter 12 in the above formula has two poles (the denominator is a quadratic polynomial s 2 term, so there are two poles), so it is a second-order filter. Of course, the loop filter 12 can also be a multi-order filter of two or more orders, and several poles in the denominator of the transfer function H(s) can realize a multi-order filter.

[0066] In an example, referring to Figure 4 The ring oscillator 14 includes n cascaded inverters INV1-INVn, INV1 being the first-stage inverter in the ring oscillator 14 and INVn being the last-stage inverter (or the “nth-stage inverter”) in the ring oscillator 14. The control end of each inverter is coupled to the output end of the first gain amplifier 13 to access the first voltage Vc1, and the other control end of each inverter is coupled to the output end of the second gain amplifier 17 to access the second voltage Vc2. The input end of the first-stage inverter INV1 is the input end in of the ring oscillator 14, and the output end of the last-stage inverter INVn is the output end out of the ring oscillator 14.

[0067] In an example, referring to Figure 5 The triangular wave generator 16 includes a transconductance amplifier OTA and an integration capacitor C2. The first input end (for example, the “-” input end) of the transconductance amplifier OTA is coupled to the second output end of the loop filter 12 to access the voltage V CTRL_R The second input end (for example, the “+” input end) of the transconductance amplifier OTA is coupled to the reference voltage VREF, and the transconductance amplifier OTA is used to convert the difference AV CTRL_R between the voltage V CTRL_Rto an error current △I. The integral capacitor C2 is coupled between the output of the transconductance amplifier OTA and the input of the second gain amplifier 17, and is used to integrate the error current △I output by the transconductance amplifier OTA to generate a triangular wave voltage V CTRL_C , where the error current △I is equal to the difference △V between the VCTRL_R and the reference voltage VREF CTRL_R multiplied by the transconductance value 1 / R2 of the transconductance amplifier OTA. The error current △I forms a triangular wave voltage V CTRL_C on the integral capacitor C2, and the result is equal to [△I(T / 2)] / C2. By substituting T=a*R2C2, it is simplified to △V CTRL_C =a*△V CTRL_R , where a is a constant.

[0068] The transconductance amplifier OTA can be implemented by any suitable circuit design. For example, VREF and VBG have a coefficient relationship, and the transconductance amplifier OTA can use source degeneration technology to make the current amplification coefficient strongly related to the inverse R2 of the transconductance value (1 / R2).

[0069] As an example, please refer to Figure 6 , the transconductance amplifier OTA includes a differential input circuit 161, a first current mirror 162, a second current mirror 163, and a third current mirror 164. The differential input circuit 161 is coupled to the reference voltage VREF and the second output of the loop filter 12, and is used to convert the voltage V CTRL_R of the second output of the loop filter 12 into a first current (not shown), and convert the reference voltage VREF into a second current (not shown). The first current mirror 162 is coupled to the differential input circuit 161 and is used to mirror output the first current (not shown). The second current mirror 163 is coupled to the differential input circuit 161 and the output out of the transconductance amplifier OTA, and is used to mirror output the second current. The third current mirror 164 is coupled to the output of the first current mirror 162 and the output of the transconductance amplifier OTA, and is used to mirror output the current output by the first current mirror 162 again. Thus, at the output of the transconductance amplifier OTA, the difference between the mirror current of the second current mirror 163 and the mirror current of the third current mirror 164 is obtained as the error current △I.

[0070] Optionally, the differential input circuit 161 includes a first input tube N1, a second input tube N2, and a second adjustable resistor R0. The gate of the first input tube N1 is coupled to the second output of the loop filter 12 to access the voltage V CTRL_RThe gate of the second input tube N2 is coupled with a reference voltage VREF, the source of the first input tube N1 is coupled with one end of a second adjustable resistor R0, and the source of the second input tube N2 is coupled with the other end of the second adjustable resistor R0. The resistance of the second adjustable resistor R0 can determine the transconductance value (1 / R2) of the transconductance amplifier OTA, which can be selected as any suitable value according to requirements, and the present application does not make specific limitation thereon. In an example, the resistance of the second adjustable resistor R0 can be equal to 2*R2, and R2 is the inverse of the transconductance value (1 / R2) of the transconductance amplifier OTA. The first input tube N1 and the second input tube N2 have the same conductivity type, for example, both are NMOS tubes or both are PMOS tubes.

[0071] Further, the differential input circuit 161 further includes a first current source I1, a second current source I2, a third current source I3, and a fourth current source I4. One end of the first current source I1 is coupled with the drain of the first input tube N1, one end of the second current source I2 is coupled with the source of the first input tube N1, one end of the third current source I3 is coupled with the drain of the second input tube N2, and one end of the fourth current source I4 is coupled with the source of the second input tube N2. The other end of the first current source I1 and the other end of the third current source I3 are both coupled with a power supply voltage (not shown), and the other end of the second current source I2 and the other end of the fourth current source I4 are both grounded.

[0072] Optionally, the first current mirror 162 includes a first mirror tube M1 and a second mirror tube M2. The gate of the first mirror tube M1 and the gate of the second mirror tube M2 are both coupled with the drain of the first input tube N1, the drain of the second mirror tube M2 is coupled with the source of the first input tube N1, and the drain of the first mirror tube M1 is the output end of the first current mirror 162 and is coupled with the input end of the third current mirror 164. Further, the first mirror tube M1 and the second mirror tube M2 have the same conductivity type and are opposite to the conductivity type of the first input tube N1, for example, the first input tube N1 is an NMOS tube, and the first mirror tube M1 and the second mirror tube M2 are both PMOS tubes.

[0073] Optionally, the second current mirror 163 includes a third mirror tube M3 and a fourth mirror tube M4. The gate of the third mirror tube M3 and the gate of the fourth mirror tube M4 are both coupled with the drain of the second input tube N2, the drain of the third mirror tube M3 is coupled with the source of the second input tube N2, the drain of the fourth mirror tube M4 is the output end of the second current mirror 163 and is coupled with the output end of the third current mirror 164 and the output end out of the transconductance amplifier OTA. Further, the third mirror tube M3 and the fourth mirror tube M4 have the same conductivity type and are opposite to the conductivity type of the second input tube N2, for example, the second input tube N2 is an NMOS tube, and the third mirror tube M3 and the fourth mirror tube M4 are both PMOS tubes.

[0074] Optionally, the third current mirror 164 comprises a fifth mirror tube N3 and a sixth mirror tube N4, the gate of the fifth mirror tube N3, the drain of the fifth mirror tube N3 and the gate of the sixth mirror tube N4 are coupled to each other as the input terminal of the third current mirror 164, and are coupled to the output terminal of the first current mirror 162, the drain of the sixth mirror tube N4 is the output terminal of the third current mirror 164, and is coupled to the output terminal of the second current mirror 163 and the output terminal out of the transconductance amplifier OTA.

[0075] It should be understood that, Figure 6 In the embodiment, N1-N4 are NMOS tubes, and M1-M4 are PMOS tubes, but the technical solution of the present application is not limited to this, in other embodiments of the present application, one or more NMOS tubes can be replaced by PMOS tubes, BJT tubes or triodes, etc., and one or more PMOS tubes can be replaced by NMOS tubes, BJT tubes or triodes, etc.

[0076] In addition, each circuit module in the first loop loop1 and the second loop loop2 described above can be integrated in a spread spectrum clock generator chip, or at least one circuit module can be arranged on the periphery of the spread spectrum clock generator chip, and the present application does not make specific limitation thereto.

[0077] For example, the spread spectrum clock generator composed of the circuit shown in Figures 1 to 6 The waveform of the triangular wave voltage V CTRL_C of the spread spectrum clock generator of the embodiment is shown in Figure 8 The period T=a*R2*C2 of the triangular wave voltage V CTRL_C , by adjusting or trimming the size of R2 and C2, the modulation frequency fout of the output of the ring oscillator 14 for spreading can be changed (the corresponding base frequency is fcenter).

[0078] The error current △I generated by the transconductance amplifier OTA is △V CTRL_R *1 / R2, the triangular wave voltage V CTRL_C formed by the error current △I on the integration capacitor C2 is [△I(T / 2)] / C2, and by substituting T=a*R2*C2 and simplifying, we get: △V CTRL_C =a*△V CTRL_R When the voltage V CTRL_R at the second output terminal of the loop filter 12 changes by △V CTRL_R , the charge pump 11 of the first loop loop1 will charge the loop filter 12 with a charging current ICP, and the result is [(ICP)*(T / 2)] / C1, and ICP=VBG / R, substituting the above formula gives △V CTRL_R =[VBG / R*(a*R2*C2 / 2)] / C1, it can be seen that △VCTRL_R The value is proportional to VBG, i.e., the coefficient k = a*R2*C2 / (2*C1*R), where R is the resistance of the first adjustable resistor in charge pump 11, and R = VBG / ICP.

[0079] Obviously, by adjusting or trimming the ratio of R2 to R and the ratio of C2 to C1, the coefficient k can be made to remain unchanged with PVT (i.e., process, voltage, temperature), thereby further realizing that the modulation depth of the ring oscillator 14 spread spectrum does not change with PVT.

[0080] In other words, the triangular wave voltage V CTRL_C The amplitude ΔV = VBG / k, and the coefficient k can be adjusted by trimming the bias current of the transconductance amplifier OTA, thereby obtaining ΔV that does not change with PVT, which is used to change the modulation depth of the output of the ring oscillator 14 for spread spectrum.

[0081] Therefore, by adjusting the three parameters R2, C2, and coefficient k before the product (chip or electronic device) leaves the factory, the modulation frequency and modulation depth required for spreading the output of the ring oscillator can be determined.

[0082] Further, please refer to Figure 9 Adjusting the reference voltage VREF changes the spreading mode of the spreading clock generator in this embodiment. For example, when the reference voltage VREF is equal to a set value (not marked), the spreading clock generator can perform center spreading; when the reference voltage VREF is lower than the set value, the spreading clock generator can perform downward spreading; and when the reference voltage VREF is higher than the set value, the spreading clock generator can perform upward spreading.

[0083] In conclusion, the spread spectrum clock generator disclosed in the present application adds a second loop on the basis of the traditional clock generator loop (i.e. the first loop), and the second loop adopts a pure analog circuit design and is led out from the second output end of the loop filter of the first loop, and can generate the second voltage of the modulation frequency and the modulation depth for controlling the output of the ring oscillator to spread spectrum, the scheme is simple and easy to implement, the circuit structure is simple, small in area, low in cost and low in power consumption, and can effectively improve the electromagnetic interference (EMI) problem, and can avoid using the sigma-delta modulator, thereby greatly reducing the clock jitter of the output of the first loop, improving the reliability, and being very suitable for the application requirements of the spread spectrum phase-locked loop. In addition, the modulation frequency of the output of the ring oscillator for spread spectrum can be changed by adjusting or trimming the resistance value of the transconductance amplifier and the capacitance value of the integration capacitor in the second loop, and the modulation frequency is not changed with PVT (process, voltage, temperature), and the modulation depth of the output of the ring oscillator for spread spectrum can be changed by adjusting or trimming the bias current of the transconductance amplifier to adjust the corresponding coefficient, and the modulation depth is also not changed with PVT.

[0084] Based on the same inventive concept, the present application also provides an electronic device comprising the spread spectrum clock generator as described in the present application. The specific process of generating spread spectrum of the electronic device can refer to the corresponding content of the spread spectrum clock generator in the above-mentioned embodiments, and will not be described here.

[0085] The electronic device can be a device or a functional module or an interface (such as a high-speed interface adopting a standard such as DDR, PCIe or HDMI, such as a register clock driver (RCD) or a data buffer (DB), etc.) in any suitable application field, such as the field of system on chip (SOC), the field of storage (such as standards such as DDR4, DDR5, LPDDR4, LPDDR5, etc.), the field of communication equipment, the field of portable equipment, etc. As long as a chip or an electronic device requiring a high-speed clock can adopt the spread spectrum clock generator of the present application to improve the EMI of the high-speed clock signal.

[0086] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, and any modification or modification of the present application by a person skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.

Claims

1. A spread spectrum clock generator, comprising: The application relates to a phase-locked loop (PLL) circuit, comprising: a first loop comprising a loop filter and a ring oscillator, and configured to generate a first voltage for controlling an oscillation frequency of an output of the ring oscillator based on a voltage output by a first output terminal of the loop filter; a second loop coupled to a second output terminal of the loop filter and configured to generate a second voltage for controlling a modulation frequency and a modulation depth of a spread spectrum of the output of the ring oscillator based on a voltage output by the second output terminal of the loop filter; wherein the second loop comprises a triangular wave generator and a second gain amplifier, a first input terminal of the triangular wave generator is coupled to the second output terminal of the loop filter, a second input terminal of the triangular wave generator is coupled to a corresponding reference voltage, the triangular wave generator is configured to output the voltage output by the second output terminal of the loop filter as a triangular wave voltage, a period of the triangular wave voltage is used to control the modulation frequency of the spread spectrum of the output of the ring oscillator, and an amplitude of the triangular wave voltage is used to control the modulation depth of the spread spectrum of the output of the ring oscillator; and an input terminal of the second gain amplifier is coupled to an output terminal of the triangular wave generator and configured to convert the triangular wave voltage into the second voltage to be provided to a second control terminal of the ring oscillator. The first loop further comprises a phase-frequency detector, a charge pump, a first gain amplifier, and a frequency divider, the phase-frequency detector, the charge pump, the loop filter, and the first gain amplifier are sequentially coupled, a first input terminal of the phase-frequency detector is coupled to an output terminal of the frequency divider, a second input terminal of the phase-frequency detector is coupled to an input clock signal, the first gain amplifier is configured to convert the voltage output by the first output terminal of the loop filter into the first voltage to be provided to a first control terminal of the ring oscillator, and an output terminal of the ring oscillator is coupled to an input terminal of the frequency divider and an input terminal of the ring oscillator.

2. The spread spectrum clock generator of claim 1, wherein, The charge pump comprises an operational amplifier, a first MOS transistor, a second MOS transistor, and a first adjustable resistor, a first input terminal of the operational amplifier is coupled to a bandgap reference voltage, a second input terminal of the operational amplifier is coupled to a first terminal of the first adjustable resistor and a drain of the first MOS transistor, an output terminal of the operational amplifier is coupled to a gate of the first MOS transistor and a gate of the second MOS transistor, a second terminal of the first adjustable resistor is grounded, and a drain of the second MOS transistor is coupled to an input terminal of the loop filter to provide a charging and discharging current.

3. The spread spectrum clock generator of claim 2, wherein, The loop filter comprises a filter resistor and a first filter capacitor, a first terminal of the filter resistor serves as the first output terminal of the loop filter, a second terminal of the filter resistor serves as the second output terminal of the loop filter and is coupled to one terminal of the first filter capacitor and the second loop, and the other terminal of the first filter capacitor is grounded.

4. The spread spectrum clock generator of claim 1, wherein, The loop filter is a multi-stage filter with two or more stages, and at least comprises a second filter capacitor, one terminal of the second filter capacitor is coupled to the first terminal of the filter resistor, and the other terminal of the second filter capacitor is grounded.

5. The spread spectrum clock generator of claim 4, wherein, ​ 6. The spread spectrum clock generator of any of claims 1-5, wherein, The triangular wave generator comprises a trans-impedance amplifier and an integration capacitor, a first input end of the trans-impedance amplifier is coupled with the second output end of the loop filter, a second input end of the trans-impedance amplifier is coupled with the reference voltage, the trans-impedance amplifier is used for converting a difference between the voltage of the second output end of the loop filter and the reference voltage into an error current, and the integration capacitor is coupled with an output end of the trans-impedance amplifier and an input end of the second gain amplifier and is used for integrating the error current to generate the triangular wave voltage.

7. The spread spectrum clock generator of claim 6, wherein, The error current ΔI = ΔV CTRL_R / R2, the amplitude ΔV = VBG / k of the triangular wave voltage, and the period T = a*R2*C2 of the triangular wave voltage, wherein ΔV CTRL_R is a difference between a voltage of the second output end of the loop filter and the reference voltage, 1 / R2 is a transconductance value of the transconductance amplifier, C2 is a capacitance value of the integration capacitor, VBG is a bandgap reference voltage, a is a constant, and k is a coefficient.

8. The spread spectrum clock generator of claim 7, wherein, k=a*R2*C2 / (2*C1*R), the ratio of R2 and R and the ratio of C2 and C1 are adjusted, so that the coefficient k does not change with process, voltage and temperature, and then the modulation depth does not change with the process, voltage and temperature, wherein R=VBG / ICP, ICP is a charge and discharge current of the loop filter, and C1 is a capacitance value of a first filter capacitor at the second output end of the loop filter.

9. The spread spectrum clock generator of claim 6, wherein, The trans-impedance amplifier comprises: a differential input circuit coupled with the reference voltage and the second output end of the loop filter and used for converting the voltage of the second output end of the loop filter into a first current and converting the reference voltage into a second current; a first current mirror coupled with the differential input circuit and used for mirror outputting the first current; a second current mirror coupled with the differential input circuit and an output end of the trans-impedance amplifier and used for mirror outputting the second current; a third current mirror coupled with the first current mirror and the output end of the trans-impedance amplifier and used for mirror outputting the current outputted by the first current mirror again, so that the output end of the trans-impedance amplifier outputs the error current.

10. The spread spectrum clock generator of claim 9, wherein, The differential input circuit comprises a first input tube, a second input tube and a second adjustable resistor, a gate of the first input tube is coupled with the second output end of the loop filter, a gate of the second input tube is coupled with the reference voltage, a source of the first input tube is coupled with one end of the second adjustable resistor, and a source of the second input tube is coupled with the other end of the second adjustable resistor, wherein the second adjustable resistor determines a trans-impedance value of the trans-impedance amplifier.

11. The spread spectrum clock generator of claim 10, wherein, Further comprising at least one of the following (1) to (4): (1) the first current mirror comprises a first mirror tube and a second mirror tube, a gate of the first mirror tube and a gate of the second mirror tube are both coupled with a drain of the first input tube, a drain of the second mirror tube is coupled with a source of the first input tube, and a drain of the first mirror tube is used as an output end of the first current mirror and is coupled with an input end of the third current mirror; (2) the second current mirror comprises a third mirror tube and a fourth mirror tube, a gate of the third mirror tube and a gate of the fourth mirror tube are both coupled with a drain of the second input tube, a drain of the third mirror tube is coupled with a source of the second input tube, a drain of the fourth mirror tube is used as an output end of the second current mirror and is coupled with an output end of the third current mirror and an output end of the trans-impedance amplifier; (3) the third current mirror comprises a fifth mirror tube and a sixth mirror tube, a gate of the fifth mirror tube and a gate of the sixth mirror tube are both coupled with a drain of the first mirror tube, a drain of the fifth mirror tube is coupled with a source of the first mirror tube, and a drain of the sixth mirror tube is used as an output end of the third current mirror and is coupled with the output end of the trans-impedance amplifier; (4) the first input tube, the second input tube, the first mirror tube, the second mirror tube, the third mirror tube, the fourth mirror tube, the fifth mirror tube and the sixth mirror tube are all N-type metal-oxide-semiconductor (NMOS) tubes. (3) the third current mirror comprises a fifth mirror tube and a sixth mirror tube, a gate of the fifth mirror tube, a drain of the fifth mirror tube and a gate of the sixth mirror tube are coupled to each other as an input terminal of the third current mirror, and are coupled to an output terminal of the first current mirror, a drain of the sixth mirror tube is an output terminal of the third current mirror, and is coupled to an output terminal of the second current mirror and an output terminal of the trans-impedance amplifier; (4) the differential input circuit further comprises a first current source, a second current source, a third current source and a fourth current source, one end of the first current source is coupled to a drain of the first input tube, one end of the second current source is coupled to a source of the first input tube, one end of the third current source is coupled to a drain of the second input tube, and one end of the fourth current source is coupled to a source of the second input tube.

12. The spread spectrum clock generator of claim 1, wherein, Adjusting the reference voltage size can change the spread spectrum clock generator spread spectrum mode, wherein: When the reference voltage is adjusted to be equal to the set value, the spread spectrum clock generator realizes center spread spectrum; When the reference voltage is adjusted to be lower than the set value, the spread spectrum clock generator realizes downward spread spectrum; When the reference voltage is adjusted to be higher than the set value, the spread spectrum clock generator realizes upward spread spectrum.

13. An electronic device, comprising: The spread spectrum clock generator comprises any one of claims 1-12.

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