Method and system for transmitting and receiving data between upper computer and single-chip microcomputer

Abstract

The invention relates to the technical field of industrial automation control, in particular to a data transceiving method and system for an upper computer and a single-chip microcomputer. The method comprises the steps that N data buffer areas are set for the single chip microcomputer, and an initialization pointer points to n data buffer areas; the upper computer sends a data frame to the single-chip microcomputer, and the data buffer area pointed by the pointer serves as a data receiving buffer area to receive the data frame; the data receiving buffer area is converted into a data processing buffer area after being fully occupied; the n data buffer areas and the N-n data buffer areas alternately receive and process the data frames until all the data frames are transmitted; according to the method and the device, a plurality of data buffers are established, one part of the data buffers are used for receiving the data, and the other part of the data buffers are used for processing the received data, so that the data is received and processed alternately, the problem that the data is easy to lose in the prior art is effectively solved, and the data transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial automation control, and particularly relates to a data transceiver method and system for a host computer and a single-chip microcomputer. Background Art

[0002] In an industrial automation control system, the communication between a host computer and a single-chip microcomputer is crucial. In the prior art, the host computer and the single-chip microcomputer usually adopt a single buffer receiving method for data frame transmission. However, in the process of high-speed and continuous data transmission, the traditional single buffer receiving method cannot receive data and process output simultaneously. When receiving data in the single buffer, the received data cannot be processed, and processing can only start after receiving is completed, resulting in low processing efficiency. Moreover, the single buffer receiving method is prone to data loss. During the data processing process, since new data continuously comes in, but the capacity of the single buffer is limited, when the received data frame cannot be processed in time, the new data frame will overwrite the unprocessed data frame, causing data loss. Summary of the Invention

[0003] The object of the present invention is to provide a data transceiver method for a host computer and a single-chip microcomputer to solve the above technical problems;

[0004] The object of the present invention is also to provide a data transceiver system for a host computer and a single-chip microcomputer to solve the above technical problems.

[0005] The technical problems solved by the present invention can be realized by adopting the following technical solutions:

[0006] A data transceiver method for a host computer and a single-chip microcomputer includes:

[0007] Step S1: Set N data buffers for the single-chip microcomputer, and initialize the pointer to point to n of the data buffers;

[0008] Step S2: The host computer sends a data frame to the single-chip microcomputer, and the data buffer pointed to by the pointer is used as a data receiving buffer to receive the data frame;

[0009] Step S3: After the data receiving buffer is full, it is converted into a data processing buffer, and the data frame in the data processing buffer is processed. At the same time, the data buffer not pointed to by the pointer is converted into the data receiving buffer to receive the data frame;

[0010] Step S4: After each data receiving buffer is full, it is converted into the data processing buffer. At the same time, the data processing buffer performing data processing is converted into the data receiving buffer, and the n data buffers and the N - n data buffers alternately receive and process the data frame until all the data frames are transmitted;

[0011] Where N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 1.

[0012] Preferably, N is an even number, and the value of n is N / 2.

[0013] Preferably, in step S2, after the data receiving buffer receives the valid data frame, it sends a response frame to the host computer, checks whether the host computer receives the response frame within a predetermined time. If received, the corresponding data frame is retained; if not received, it is confirmed that the data frame is invalid, the resources occupied by the data frame are released, and the host computer resends the data frame.

[0014] Preferably, when the host computer resends the data frame in step S2, a unique identifier is added to the resended data frame.

[0015] Preferably, in step S2, both the data frame and the response frame include a device address, a function code, a data length, and a check code.

[0016] Preferably, in step S3, data processing of the data frame includes verifying the data frame. If the verification passes, the data frame is retained; if the verification fails, the data frame is discarded.

[0017] Preferably, step S1 further includes configuring protocol parameters of the communication protocol between the host computer and the single-chip microcomputer, including a device address, a function code, a starting address, and a quantity.

[0018] Preferably, the communication protocol is the MODBUS protocol.

[0019] Preferably, step S1 further includes configuring interface parameters of the communication interface between the host computer and the single-chip microcomputer, including a baud rate, a data bit, a parity check, a stop bit, a communication timeout, and a frame interval time.

[0020] A data transceiver system between a host computer and a single-chip microcomputer includes

[0021] A host computer for sending a data frame;

[0022] A single-chip microcomputer connected to the host computer for receiving and processing the data frame;

[0023] A cache module is provided inside the single-chip microcomputer. The cache module includes N data buffers, where the initial n data buffers are data reception buffers for receiving the data frames. When the data reception buffers are full, they are converted into data processing buffers for processing the data frames; the remaining idle data buffers are converted into data reception buffers for receiving the data frames.

[0024] Advantages of the present invention: Due to the above technical solutions, by establishing multiple data buffers, the present invention uses a part of the data buffers to receive data and another part of the data buffers to process the received data, thereby alternately receiving and processing data, effectively solving the problem of easy data loss in the prior art and improving the data transmission efficiency. Description of the Drawings

[0025] Figure 1 It is a schematic diagram of the steps of the data sending and receiving method between the host computer and the single-chip microcomputer in the embodiment of the present invention;

[0026] Figure 2 It is an architecture diagram of the data sending and receiving system in the embodiment of the present invention including two data buffers. Detailed Embodiments

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0028] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0029] Next, the present invention will be further described in conjunction with the drawings and specific embodiments, but it is not a limitation of the present invention.

[0030] A data sending and receiving method between a host computer and a single-chip microcomputer, as Figure 1 , Figure 2 shown, includes,

[0031] Step S1: Set N data buffers for the single-chip microcomputer 2, and initialize the pointer to point to n of the data buffers;

[0032] Step S2: The host computer 1 sends a data frame to the single-chip microcomputer 2, and the data buffer pointed to by the pointer is used as the data reception buffer to receive the data frame;

[0033] Step S3, after the data reception buffer finishes receiving, it is converted into a data processing buffer, and the data frames in the data processing buffer are processed. At the same time, the data buffer not pointed to by the pointer is converted into a data reception buffer to receive data frames;

[0034] Step S4, every time after the data reception buffer finishes receiving, it is converted into a data processing buffer. At the same time, the data processing buffer that is performing data processing is converted into a data reception buffer. The n data buffers and the N - n data buffers alternately receive and process data frames until all data frames are transmitted;

[0035] Where N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 1.

[0036] Specifically, the present invention effectively solves the problem of easy data loss in the prior art and improves data transmission efficiency by establishing multiple data buffers, using a part of the data buffers to receive data and another part of the data buffers to process the received data, and alternately receiving and processing data in this way.

[0037] In a preferred embodiment, N is an even number, and the value of n is N / 2.

[0038] Specifically, in the present invention, an even number of data buffers are set. Half of the data buffers are initialized as data reception buffers to receive data frames. When the data reception buffer finishes receiving, it is converted into a data processing buffer, and the other half of the data buffers not pointed to by the pointer are converted into data reception buffers to receive data frames;

[0039] In this way, the N / 2 data buffers and the N / 2 data buffers alternately receive and process data frames, ensuring that the data capacities of the data reception buffer and the data processing buffer always remain quite the same, and trying to ensure relatively balanced data processing capabilities and data reception capabilities, and preventing system errors caused by different data capacities during long-term data reception and processing.

[0040] It should be noted that the data reception buffer finishing receiving means reaching a preset data volume or receiving a specific end flag.

[0041] Further specifically, please refer to Figure 2 As shown, in the present invention, N takes the value of 2, and the data buffer includes two data buffers, namely the first data buffer 21 and the second data buffer 22;

[0042] On the single-chip microcomputer 2 side, a first data buffer 21 and a second data buffer 22 are set up to alternately receive and process data from the host computer 1. When the first data buffer 21 is receiving data, the second data buffer 22 can be processed; when the first data buffer 21 finishes receiving data and switches to the second data buffer 22 to receive data, the data in the first data buffer 21 can be processed. In this way, data reception and processing can be carried out simultaneously, improving the efficiency and reliability of data transmission.

[0043] The present invention takes two data buffers as a specific embodiment, and the steps of data processing are as follows:

[0044] Step 1: Set up a first data buffer 21 and a second data buffer 22, and initialize a pointer to point to one of the data buffers (for example, the first data buffer 21).

[0045] Configure the parameters of the MODBUS protocol, including device address, function code, starting address, quantity, etc.;

[0046] Step 2: When the pointer points to the first data buffer 21, use the first data buffer 21 to receive the data sent from the host computer 1. At this time, the second data buffer 22 can be processed.

[0047] When the first data buffer 21 finishes receiving data, reaches the preset data volume or receives a specific end flag, immediately switch to the second data buffer 22 to receive data, and at the same time start processing the data in the first data buffer 21.

[0048] The operations for processing data include data parsing, verification, and storage.

[0049] Step 3: Continuously repeat the above process, that is, when the second data buffer 22 finishes receiving data, switch to the first data buffer 21 to receive data, and at the same time process the data in the second data buffer 22.

[0050] In this way, the first data buffer 21 and the second data buffer 22 continuously alternate to receive and process data, realizing the continuous flow and efficient processing of data.

[0051] In a preferred embodiment, in step S2, after the data reception buffer receives a valid data frame, it sends a response frame to the host computer 1, checks whether the host computer 1 receives the response frame within a predetermined time. If it receives, retain the corresponding data frame; if not, confirm that the data frame is invalid, release the resources occupied by the data frame, and the host computer 1 resends the data frame.

[0052] Specifically, when a request or data packet is sent, if no response or confirmation is received within a predetermined time, the system will trigger the timeout mechanism and attempt to resend the request or data frame. By setting a reasonable timeout and resending strategy, the reliability of data transmission and the fault tolerance of the system can be improved. The timeout mechanism includes,

[0053] Detection failure: By setting the timeout, if the system fails to receive the data frame within the specified time, it is determined that the data frame has failed.

[0054] Resource release: When the data frame times out, the system releases the resources associated with it to avoid long-term resource occupation.

[0055] Trigger resend: When the data frame times out, the system will resend the data frame.

[0056] In a preferred embodiment, in step S2, when the host computer 1 resends the data frame, a unique identifier is added to the resended data frame.

[0057] Specifically, during the resend process, in order to ensure that the receiving party can correctly identify and process duplicate data frames, a unique identifier, such as a data register, needs to be added to the data frame.

[0058] After receiving the data frame, the microcontroller 2 can determine whether the data frame has been received based on the data register, thus avoiding duplicate processing.

[0059] In a preferred embodiment, in step S2, both the data frame and the response frame include the device address, function code, data length, and checksum.

[0060] Specifically, in the present invention, the microcontroller 2, as a slave device, parses the data frame sent by the host computer 1 according to the MODBUS protocol, including the device address, function code, data address, data length, and CRC checksum, etc. After receiving the valid data, it stores it in the currently idle buffer. At the same time, the microcontroller 2 also sends a response data frame to the host computer 1 according to the MODBUS protocol, including the device address, function code, data length, and CRC checksum, etc.

[0061] In a preferred embodiment, in step S3, data processing of the data frame includes verifying the data frame. If the verification passes, the data frame is retained; if the verification fails, the data frame is discarded.

[0062] Specifically, when processing data, it is necessary to perform device address, function code, and CRC verification on the received data to ensure the accuracy and integrity of the data. If the verification fails, the microcontroller 2 resends the data. If the verification still fails after three resends, the frame data is discarded, and an error response is sent to the host computer 1.

[0063] Meanwhile, to maintain the real-time nature of the data and ensure that data reception and processing can be completed within the polling cycle. If the processing time is too long, it is necessary to adjust the polling cycle or optimize the data processing algorithm.

[0064] In a preferred embodiment, step S1 further includes configuring the protocol parameters of the communication protocol between the host computer 1 and the single-chip microcomputer 2, including device address, function code, starting address, and quantity.

[0065] In a preferred embodiment, the communication protocol is the MODBUS protocol.

[0066] Specifically, as a simple, open, and reliable communication protocol, the MODBUS protocol is widely used in the communication between industrial devices. In the present invention, the host computer 1 serves as the master device and the single-chip microcomputer 2 serves as the slave device, and they communicate through the MODBUS protocol.

[0067] Preferably, since the standard MODBUS protocol is adopted for communication, there is no need to develop a special communication protocol and driver program, which reduces the maintenance cost of the system.

[0068] In a preferred embodiment, step S1 further includes configuring the interface parameters of the communication interface between the host computer 1 and the single-chip microcomputer 2, including baud rate, data bits, parity check, stop bits, communication timeout, and frame interval time.

[0069] The system architecture of the present invention mainly includes a host computer 1, a single-chip microcomputer 2, and a communication interface connecting the two. The communication interface uses an RS485 interface or an RS232 interface.

[0070] The communication interface (such as RS485, RS-232, etc.) between the host computer 1 and the single-chip microcomputer 2 needs to be configured accordingly, including setting parameters such as baud rate, data bits, parity check, stop bits, etc. At the same time, parameters such as communication timeout and frame interval time also need to be set to ensure the stability and reliability of communication.

[0071] Preferably, the present invention can be applied to the communication between different types of host computers 1 and single-chip microcomputers 2, and only needs to be configured accordingly according to the specific hardware platform and communication interface.

[0072] A data transceiver system for a host computer and a single-chip microcomputer includes

[0073] A host computer 1 for sending data frames;

[0074] A single-chip microcomputer 2 connected to the host computer 1 for receiving and processing data frames;

[0075] The cache module is provided inside the single-chip microcomputer 2. The cache module includes N data buffers, where the initial n data buffers are data reception buffers for receiving data frames. In the state where the data reception buffer ends the reception, it is converted into a data processing buffer for processing the data frames; the remaining idle data buffers are converted into data reception buffers for receiving data frames.

[0076] Specifically, as Figure 2 shown, the cache module of the present invention is provided with a total of 2 data buffers, including a first data buffer 21 and a second data buffer 22;

[0077] At the single-chip microcomputer 2 side, the first data buffer 21 and the second data buffer 22 are set up to alternately receive and process data from the host computer 1. When the first data buffer 21 is receiving data, the second data buffer 22 can be processed; when the first data buffer 21 finishes receiving and switches to the second data buffer 22 to receive data, the data in the first data buffer 21 can be processed. In this way, receiving and processing data can be carried out simultaneously, improving the efficiency and reliability of data transmission.

[0078] Taking two data buffers as a specific embodiment of the present invention, the steps of data processing are as follows:

[0079] Step 1, set up the first data buffer 21 and the second data buffer 22, and initialize a pointer to point to one of the data buffers (for example, the first data buffer 21).

[0080] Configure the parameters of the MODBUS protocol, including device address, function code, starting address, quantity, etc.;

[0081] Step 2, when the pointer points to the first data buffer 21, use the first data buffer 21 to receive the data sent from the host computer 1. At this time, the second data buffer 22 can be processed.

[0082] When the first data buffer 21 finishes receiving data, reaches the preset data volume or receives a specific end flag, immediately switch to the second data buffer 22 for data reception, and at the same time start processing the data in the first data buffer 21.

[0083] The operations of processing data include data parsing, verification, and storage.

[0084] Step 3, continuously repeat the above process, that is, when the second data buffer 22 finishes receiving data, switch to the first data buffer 21 for data reception, and at the same time process the data in the second data buffer 22.

[0085] By setting two data buffers at the single-chip microcomputer 2, data reception and processing can be carried out simultaneously. When a part of the data buffer is used as a data reception buffer to receive data, the other part of the data buffer can be used as a data processing buffer to process data; after the data reception buffer finishes receiving data, it is converted into a data processing buffer, and at the same time, the original data processing buffer is converted into a data reception buffer to receive data.

[0086] The alternating working mode of the two data buffers avoids the situation where data reception and processing wait for each other in the traditional single-buffer reception mode, reduces data processing delay, ensures that data is not lost during high-speed and continuous transmission, and improves data transmission efficiency.

[0087] The above are only the preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be realized that any equivalent replacement and obvious changes made by using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A data sending and receiving method between a host computer and a single-chip microcomputer, characterized in that including Step S1: Set N data buffers for the single-chip microcomputer, and initialize the pointer to point to n of the data buffers; Step S2: The host computer sends a data frame to the single-chip microcomputer, and the data buffer pointed to by the pointer serves as a data reception buffer to receive the data frame; Step S3: After the data reception buffer finishes receiving, it is converted into a data processing buffer, and the data frame in the data processing buffer is processed. At the same time, the data buffers not pointed to by the pointer are converted into data reception buffers to receive the data frame; Step S4: After each data reception buffer finishes receiving, it is converted into a data processing buffer. At the same time, the data processing buffer that executes data processing is converted into a data reception buffer. The n data buffers and the N - n data buffers alternately receive and process the data frame until all the data frames are transmitted; where N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 1.

2. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 1, characterized in that N is an even number, and the value of n is N / 2.

3. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 1, characterized in that In step S2, after the data reception buffer receives a valid data frame, it sends a response frame to the host computer, checks whether the host computer receives the response frame within a predetermined time. If received, the corresponding data frame is retained; if not received, it is confirmed that the data frame is invalid, and the resources occupied by the data frame are released, and the host computer resends the data frame.

4. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 3, characterized in that, In step S2, when the host computer resends the data frame, a unique identifier is added to the resended data frame.

5. The data receiving and transmitting method between the host computer and the single-chip microcomputer according to claim 4, characterized in that, In step S2, both the data frame and the response frame include a device address, a function code, a data length, and a check code.

6. The data transceiver method between the host computer and the single-chip microcomputer according to claim 1, characterized in that In step S3, data processing of the data frame includes checking the data frame. If the check passes, the data frame is retained; if the check fails, the data frame is discarded.

7. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 1, characterized in that Step S1 further includes configuring the protocol parameters of the communication protocol between the host computer and the single-chip microcomputer, including the device address, function code, starting address, and quantity.

8. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 7, characterized in that, The communication protocol is the MODBUS protocol.

9. The data receiving and sending method between the host computer and the single-chip microcomputer according to claim 1, characterized in that, Step S1 further includes configuring the interface parameters of the communication interface between the host computer and the single-chip microcomputer, including the baud rate, data bits, parity check, stop bits, communication timeout, and frame interval time.

10. A data transceiver system between a host computer and a single-chip microcomputer, characterized in that, including A host computer, used for sending data frames; A single-chip microcomputer, connected to the host computer for receiving and processing the data frames; A cache module, provided inside the single-chip microcomputer. The cache module includes N data buffers, where the initial n data buffers are data reception buffers for receiving the data frames. In the state where the data reception buffer finishes receiving, it is converted into a data processing buffer for processing the data frames; The remaining idle data buffers are converted into data reception buffers for receiving the data frames.

Images